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| author | Corey Swenson <cswenson@us.ibm.com> | 2015-07-08 12:57:22 -0500 |
|---|---|---|
| committer | Patrick Williams <iawillia@us.ibm.com> | 2015-12-11 15:30:29 -0600 |
| commit | eb551fdd12e4ec25b302ec0f69be51720908e156 (patch) | |
| tree | 1573eb484fdb22dc790d810b1ab965eb97f0dd5b /src/build/simics/combined.simics | |
| parent | 56e0928053eecfd25832306b6283521462b4e412 (diff) | |
| download | talos-hostboot-eb551fdd12e4ec25b302ec0f69be51720908e156.tar.gz talos-hostboot-eb551fdd12e4ec25b302ec0f69be51720908e156.zip | |
P9 page table changes
Change-Id: Ic5f234e0ce0747f887a706054f82372c9a96258c
RTC:126640
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19041
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/build/simics/combined.simics')
| -rwxr-xr-x | src/build/simics/combined.simics | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/build/simics/combined.simics b/src/build/simics/combined.simics index 9d87c493c..72597f973 100755 --- a/src/build/simics/combined.simics +++ b/src/build/simics/combined.simics @@ -21,18 +21,6 @@ try { } } except { echo "ERROR: Failed to load tools in combined.simics." } -# Workaround to set the sim_ctrl1 reg to enable the -# old HPT SDR1 translation, not the new PTCR translation -# SIM_CTRL1_P9_SDR1 0x0010000000000000 -# @todo-RTC:126640 Remove with P9 page table support -system_cmp0.cpu0_0_00_0.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_00_1.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_00_2.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_00_3.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_0.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_1.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_2.write-reg sim_ctrl1 0x4230000000000000 -system_cmp0.cpu0_0_01_3.write-reg sim_ctrl1 0x4230000000000000 system_cmp0.cpu0_0_00_0.disable |
