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| author | Christian Geddes <crgeddes@us.ibm.com> | 2019-01-30 11:22:50 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-05 16:55:41 -0600 |
| commit | d054b917fa8bd693a248628519c81b9143e87af1 (patch) | |
| tree | 93a900d1889bd769a1e6a81842d0a494e6dc48cc /src/build/configs/simics_axone.config | |
| parent | de881124f74c2a869e633fafa9a574ef8ea45ce8 (diff) | |
| download | talos-hostboot-d054b917fa8bd693a248628519c81b9143e87af1.tar.gz talos-hostboot-d054b917fa8bd693a248628519c81b9143e87af1.zip | |
Add temporary Axone simics workarounds to progress IPL
Currently there is no VRM hooked up to the other side of the AVSbus
in simics. The simics team is working on this but for now we need
to skip the istep that calls setup evid to set voltages. This can
be removed when Simics gets this working. Also for now we are will
skip starting checkstop handling early on in the IPL because the
OCC model is not finished. This also can be changed when the model
starts working.
Change-Id: Ia0df49fedae97acceefe07e3f3c903bbe6aac83d
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71097
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/configs/simics_axone.config')
| -rw-r--r-- | src/build/configs/simics_axone.config | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/build/configs/simics_axone.config b/src/build/configs/simics_axone.config index 965b1dc60..206d65e49 100644 --- a/src/build/configs/simics_axone.config +++ b/src/build/configs/simics_axone.config @@ -1 +1,9 @@ set DJVPD_READ_FROM_HW + +#skip enabling checkstop analysis until OCC is ready in simics +unset IPLTIME_CHECKSTOP_ANALYSIS + +#Try to keep a list of things this does +# - skipping setting voltages in istep 8.12, nothing on other side of AVSbus +# in simics currently. +set AXONE_BRING_UP
\ No newline at end of file |
