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| author | Matt Derksen <mderkse1@us.ibm.com> | 2019-04-04 16:04:21 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-04-25 12:43:48 -0500 |
| commit | 7f0b6fddf3f8097bc952699ab16b53fcf965b625 (patch) | |
| tree | 68b1d92d191cb83d9fbbc0453d7213b93e281306 /src/build/configs/simics_axone.config | |
| parent | 0f03814d62a6693df5b0c3118662e00a5b79b24a (diff) | |
| download | talos-hostboot-7f0b6fddf3f8097bc952699ab16b53fcf965b625.tar.gz talos-hostboot-7f0b6fddf3f8097bc952699ab16b53fcf965b625.zip | |
Enable IPLTIME_CHECKSTOP_ANALYSIS in axone
Simics now supports the enablement so we
now pass istep 6.11 (host_start_occ_xstop_handler)
Change-Id: Ibc57795d645e98d7585eb45a122e3d127f16bbf1
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75563
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/configs/simics_axone.config')
| -rw-r--r-- | src/build/configs/simics_axone.config | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/build/configs/simics_axone.config b/src/build/configs/simics_axone.config index 3d044edcc..0b54948c0 100644 --- a/src/build/configs/simics_axone.config +++ b/src/build/configs/simics_axone.config @@ -1,4 +1,4 @@ -# Force DJVPD read/write to use EEPROM layer instead of VPD cache +# Force DJVPD read/write to use EEPROM layer instead of VPD cache set DJVPD_READ_FROM_HW set DJVPD_WRITE_TO_HW unset DJVPD_READ_FROM_PNOR @@ -20,8 +20,8 @@ set MVPD_WRITE_TO_PNOR #set to run cxx testcases during boot unset EARLY_TESTCASES -#skip enabling checkstop analysis until OCC is ready in simics -unset IPLTIME_CHECKSTOP_ANALYSIS +#Enable checkstop analysis for IPL failures +set IPLTIME_CHECKSTOP_ANALYSIS #enable EEPROM caching set SUPPORT_EEPROM_CACHING @@ -32,4 +32,4 @@ set SUPPORT_EEPROM_CACHING set AXONE_BRING_UP # Set this to pull in Axone on code (such as P9A/EXP MSS code) -set AXONE
\ No newline at end of file +set AXONE |
