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| author | Roland Veloz <rveloz@us.ibm.com> | 2019-01-29 16:57:38 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-03-07 21:59:14 -0600 |
| commit | 6e84cce39773b6409d2d0ab2a8f6ea5065684a3a (patch) | |
| tree | 4f531f53c4c5785f996c76936e352f29418a46a0 /src/build/configs/simics_axone.config | |
| parent | 4470dc33a126dfdbd7db7b30e499c1d6dc63e16e (diff) | |
| download | talos-hostboot-6e84cce39773b6409d2d0ab2a8f6ea5065684a3a.tar.gz talos-hostboot-6e84cce39773b6409d2d0ab2a8f6ea5065684a3a.zip | |
Force VPD IO through HW (Axone) ,add plat function to get OCMB VPD
This commit follows up on previous work that pulled in the code
that can find the correct EFD given a SPD blob of data which has
the DDR SPD and the EFD for the DDIMM. This commit adds ocmb_spd.C
which provides a DeviceFW::SPD read interface for OCBM targets,
and hooks is up to the platform implementation of the FAPI
interface platGetVPD for OCMB target. Also this commit forces all
VPD IO in Axone to go through HW, which will actually read from
the new EEPROM cache in pnor.
RTC: 203718
Change-Id: I270500898c422d4c78daa3b917b1b2e5b049e856
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72165
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/configs/simics_axone.config')
| -rw-r--r-- | src/build/configs/simics_axone.config | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/src/build/configs/simics_axone.config b/src/build/configs/simics_axone.config index 385c86063..2c8dda895 100644 --- a/src/build/configs/simics_axone.config +++ b/src/build/configs/simics_axone.config @@ -1,8 +1,22 @@ -#fetch dimm spd via i2c +# Force DJVPD read/write to use EEPROM layer instead of VPD cache set DJVPD_READ_FROM_HW +set DJVPD_WRITE_TO_HW +unset DJVPD_READ_FROM_PNOR +unset DJVPD_WRITE_TO_PNOR -# You can enabled MVPD read from HW but adds time to IPL +# Force MEMVPD read/write to PNOR ( No actual hardware ) +set MEMVPD_READ_FROM_PNOR +set MEMVPD_WRITE_TO_PNOR +unset MEMVPD_READ_FROM_HW +unset MEMVPD_WRITE_TO_HW + +# Force MVPD read/write to use EEPROM layer instead of VPD cache +# (not working because shoddy MVPD currently) #set MVPD_READ_FROM_HW +#set MVPD_WRITE_TO_HW +set MVPD_READ_FROM_PNOR +set MVPD_WRITE_TO_PNOR + #skip enabling checkstop analysis until OCC is ready in simics unset IPLTIME_CHECKSTOP_ANALYSIS |
