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authorDean Sanner <dsanner@us.ibm.com>2017-06-09 09:25:39 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-06-13 11:03:54 -0400
commitc3e473a9069d8d3554cdcad6886fffaebc26b205 (patch)
treebfb65ef14dfd379c32fef9b2156a8043b90abcfe /src/build/citest/etc/workarounds.postsimsetup
parentbfe431dd5361f4754ac9b9001873ca54d8b9e94e (diff)
downloadtalos-hostboot-c3e473a9069d8d3554cdcad6886fffaebc26b205.tar.gz
talos-hostboot-c3e473a9069d8d3554cdcad6886fffaebc26b205.zip
Update simulation backing build
Change-Id: I612ae04f39b8876a7b5670f861ef858a23d009b0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41610 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/citest/etc/workarounds.postsimsetup')
-rwxr-xr-xsrc/build/citest/etc/workarounds.postsimsetup8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 7aee7e160..6095b331a 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -34,11 +34,3 @@
#patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File
#pull in new actions in p9_memory.act RTC 171066
-
-#pull in new sbe image
-echo "+++ Updating sbe image"
-sbex -t 1023244
-chmod 777 $sb/sbei/sbfw/img/*
-mkdir -p $sb/engd/href/
-cd $sb/engd/href
-mk -a -k
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