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author | Nick Bofferding <bofferdn@us.ibm.com> | 2018-11-28 16:07:16 -0600 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-11-29 10:28:45 -0600 |
commit | 9744e664b6eeeac308dcea51d251cef95fc09708 (patch) | |
tree | 2934e0036f1ec9a954769be45297ee8ac1f171b7 /src/build/buildpnor/defaultPnorLayout.xml | |
parent | 19a6643807b0c01638d0fe1371ad17bc72ef0fc8 (diff) | |
download | talos-hostboot-9744e664b6eeeac308dcea51d251cef95fc09708.tar.gz talos-hostboot-9744e664b6eeeac308dcea51d251cef95fc09708.zip |
Increase HBI partition to 12 MB (w/o ECC), up from 11
HBI partition size is too small to fit all the code, so bumping it by logical
1 MB to provide breathing room
Change-Id: I78cf10d033aee2ff904db101dde6d27fb3c00fca
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69209
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matthew Raybuck <mraybuc@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/buildpnor/defaultPnorLayout.xml')
-rw-r--r-- | src/build/buildpnor/defaultPnorLayout.xml | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/src/build/buildpnor/defaultPnorLayout.xml b/src/build/buildpnor/defaultPnorLayout.xml index 371c3fbd8..33a9e53b6 100644 --- a/src/build/buildpnor/defaultPnorLayout.xml +++ b/src/build/buildpnor/defaultPnorLayout.xml @@ -140,10 +140,10 @@ Layout Description <ecc/> </section> <section> - <description>Hostboot Extended image (11MB w/o ECC)</description> + <description>Hostboot Extended image (12MB w/o ECC)</description> <eyeCatch>HBI</eyeCatch> <physicalOffset>0x451000</physicalOffset> - <physicalRegionSize>0xC60000</physicalRegionSize> + <physicalRegionSize>0xD80000</physicalRegionSize> <sha512Version/> <side>sideless</side> <ecc/> @@ -151,7 +151,7 @@ Layout Description <section> <description>SBE-IPL (Staging Area) (752K)</description> <eyeCatch>SBE</eyeCatch> - <physicalOffset>0x10B1000</physicalOffset> + <physicalOffset>0x11D1000</physicalOffset> <physicalRegionSize>0xBC000</physicalRegionSize> <sha512perEC/> <sha512Version/> @@ -161,7 +161,7 @@ Layout Description <section> <description>HCODE Ref Image (1.125MB)</description> <eyeCatch>HCODE</eyeCatch> - <physicalOffset>0x116D000</physicalOffset> + <physicalOffset>0x128D000</physicalOffset> <physicalRegionSize>0x120000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -170,7 +170,7 @@ Layout Description <section> <description>Hostboot Runtime Services for Sapphire (7.0MB)</description> <eyeCatch>HBRT</eyeCatch> - <physicalOffset>0x128D000</physicalOffset> + <physicalOffset>0x13AD000</physicalOffset> <physicalRegionSize>0x700000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -179,7 +179,7 @@ Layout Description <section> <description>Payload (21.375MB)</description> <eyeCatch>PAYLOAD</eyeCatch> - <physicalOffset>0x198D000</physicalOffset> + <physicalOffset>0x1AAD000</physicalOffset> <physicalRegionSize>0x1560000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -188,7 +188,7 @@ Layout Description <section> <description>Special PNOR Test Space (36K)</description> <eyeCatch>TEST</eyeCatch> - <physicalOffset>0x2EED000</physicalOffset> + <physicalOffset>0x300D000</physicalOffset> <physicalRegionSize>0x9000</physicalRegionSize> <testonly/> <side>sideless</side> @@ -199,7 +199,7 @@ Layout Description from skipping header. Signing is forced in build pnor phase --> <description>Special PNOR Test Space with Header (36K)</description> <eyeCatch>TESTRO</eyeCatch> - <physicalOffset>0x2EF6000</physicalOffset> + <physicalOffset>0x3016000</physicalOffset> <physicalRegionSize>0x9000</physicalRegionSize> <side>sideless</side> <testonly/> @@ -210,7 +210,7 @@ Layout Description <section> <description>Hostboot Bootloader (28K)</description> <eyeCatch>HBBL</eyeCatch> - <physicalOffset>0x2EFF000</physicalOffset> + <physicalOffset>0x301F000</physicalOffset> <!-- Physical Size includes Header rounded to ECC valid size --> <!-- Max size of actual HBBL content is 20K and 22.5K with ECC --> <physicalRegionSize>0x7000</physicalRegionSize> @@ -221,7 +221,7 @@ Layout Description <section> <description>Global Data (36K)</description> <eyeCatch>GLOBAL</eyeCatch> - <physicalOffset>0x2F06000</physicalOffset> + <physicalOffset>0x3026000</physicalOffset> <physicalRegionSize>0x9000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -229,7 +229,7 @@ Layout Description <section> <description>Ref Image Ring Overrides (20K)</description> <eyeCatch>RINGOVD</eyeCatch> - <physicalOffset>0x2F0F000</physicalOffset> + <physicalOffset>0x302F000</physicalOffset> <physicalRegionSize>0x5000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -237,7 +237,7 @@ Layout Description <section> <description>SecureBoot Key Transition Partition (16K)</description> <eyeCatch>SBKT</eyeCatch> - <physicalOffset>0x2F14000</physicalOffset> + <physicalOffset>0x3034000</physicalOffset> <physicalRegionSize>0x4000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -245,7 +245,7 @@ Layout Description <section> <description>OCC Lid (1.125M)</description> <eyeCatch>OCC</eyeCatch> - <physicalOffset>0x2F18000</physicalOffset> + <physicalOffset>0x3038000</physicalOffset> <physicalRegionSize>0x120000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -256,7 +256,7 @@ Layout Description <!-- We need 266KB per module sort, going to support 40 tables by default, plus ECC --> <eyeCatch>WOFDATA</eyeCatch> - <physicalOffset>0x3038000</physicalOffset> + <physicalOffset>0x3158000</physicalOffset> <physicalRegionSize>0xC00000</physicalRegionSize> <side>sideless</side> <sha512Version/> @@ -265,7 +265,7 @@ Layout Description <section> <description>FIRDATA (12K)</description> <eyeCatch>FIRDATA</eyeCatch> - <physicalOffset>0x3C38000</physicalOffset> + <physicalOffset>0x3D58000</physicalOffset> <physicalRegionSize>0x3000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -273,7 +273,7 @@ Layout Description <section> <description>Memory Data (128K)</description> <eyeCatch>MEMD</eyeCatch> - <physicalOffset>0x3C3B000</physicalOffset> + <physicalOffset>0x3D5B000</physicalOffset> <physicalRegionSize>0x20000</physicalRegionSize> <side>sideless</side> <sha512Version/> @@ -282,7 +282,7 @@ Layout Description <section> <description>Secureboot Test Load (12K)</description> <eyeCatch>TESTLOAD</eyeCatch> - <physicalOffset>0x3C5B000</physicalOffset> + <physicalOffset>0x3D7B000</physicalOffset> <physicalRegionSize>0x3000</physicalRegionSize> <side>sideless</side> <sha512Version/> @@ -291,7 +291,7 @@ Layout Description <section> <description>Centaur Hw Ref Image (12K)</description> <eyeCatch>CENHWIMG</eyeCatch> - <physicalOffset>0x3C5E000</physicalOffset> + <physicalOffset>0x3D7E000</physicalOffset> <physicalRegionSize>0x3000</physicalRegionSize> <sha512Version/> <side>sideless</side> @@ -300,7 +300,7 @@ Layout Description <section> <description>Secure Boot (144K)</description> <eyeCatch>SECBOOT</eyeCatch> - <physicalOffset>0x3C61000</physicalOffset> + <physicalOffset>0x3D81000</physicalOffset> <physicalRegionSize>0x24000</physicalRegionSize> <side>sideless</side> <ecc/> @@ -309,7 +309,7 @@ Layout Description <section> <description>Open CAPI Memory Buffer (OCMB) Firmware (300K)</description> <eyeCatch>OCMBFW</eyeCatch> - <physicalOffset>0x3C85000</physicalOffset> + <physicalOffset>0x3DA5000</physicalOffset> <physicalRegionSize>0x4B000</physicalRegionSize> <side>sideless</side> <sha512Version/> @@ -319,7 +319,7 @@ Layout Description <section> <description>HDAT Data (16K)</description> <eyeCatch>HDAT</eyeCatch> - <physicalOffset>0x3CD0000</physicalOffset> + <physicalOffset>0x3DF0000</physicalOffset> <physicalRegionSize>0x4000</physicalRegionSize> <side>sideless</side> <sha512Version/> |