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author | Bill Hoffa <wghoffa@us.ibm.com> | 2018-10-10 08:49:08 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-08 15:42:06 -0600 |
commit | e36e0019e0b97ee66e649fd32a708e2905b26623 (patch) | |
tree | bc8cb284194865a10d3c8f75f72a36bccf6d1643 /src/bootloader | |
parent | dc1efdb95ce7198d29797abd165d6ce2fd30f5ad (diff) | |
download | talos-hostboot-e36e0019e0b97ee66e649fd32a708e2905b26623.tar.gz talos-hostboot-e36e0019e0b97ee66e649fd32a708e2905b26623.zip |
HBBL LPC Error Checking
- To avoid IPL delays, the LPC status register should be
checked prior to loading the entire PNOR image
(done via LPC). If an error condition occurs, HBBL
should fail out.
Change-Id: I5d716213f468e28191db794bf3e5480af547b26e
CQ: SW446254
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68442
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/bootloader')
-rw-r--r-- | src/bootloader/bl_pnorAccess.C | 44 | ||||
-rw-r--r-- | src/bootloader/bootloader.C | 8 |
2 files changed, 41 insertions, 11 deletions
diff --git a/src/bootloader/bl_pnorAccess.C b/src/bootloader/bl_pnorAccess.C index 5a7076afd..89183754a 100644 --- a/src/bootloader/bl_pnorAccess.C +++ b/src/bootloader/bl_pnorAccess.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -190,9 +190,13 @@ void bl_pnorAccess::readTOC(uint8_t i_tocBuffer[PNOR::TOC_SIZE], } while(0); } -void bl_pnorAccess::findTOC(uint64_t i_pnorEnd, PNOR::SectionData_t * o_TOC, +void bl_pnorAccess::findTOC(uint64_t i_lpcBar, PNOR::SectionData_t * o_TOC, uint32_t& o_errCode, uint64_t& o_pnorStart) { + //pnorEnd is the end of flash, which is base of lpc, plus + //the offset of the FW space, plus the TOP memory address in FW space + uint64_t i_pnorEnd = i_lpcBar + LPC::LPCHC_FW_SPACE + PNOR::LPC_TOP_OF_FLASH_OFFSET; + uint8_t *l_tocBuffer = g_blScratchSpace; //The first TOC is 1 TOC size + 1 page back from the end of the flash (+ 1) @@ -204,6 +208,35 @@ void bl_pnorAccess::findTOC(uint64_t i_pnorEnd, PNOR::SectionData_t * o_TOC, //@TODO RTC:138268 Set up multiple side of PNOR for bootloader o_errCode = 0; + uint64_t l_mmioStatusAddr = LPC::LPCHC_ERR_SPACE + i_lpcBar; + + // First do a dummy LPC access (if an LPC error condition exists, + // an access can be necessary to get the error indicated in the + // status register. This read will force the error condition to + // properly be shown in the LPC error status reg + Bootloader::handleMMIO(l_mmioAddr, + reinterpret_cast<uint64_t>(l_tocBuffer), + Bootloader::WORDSIZE, + Bootloader::WORDSIZE); + + // Now Read OPB Master Status Reg offset (LPC Addr 0xC0010000) + Bootloader::handleMMIO(l_mmioStatusAddr, + reinterpret_cast<uint64_t>(l_tocBuffer), + Bootloader::WORDSIZE, + Bootloader::WORDSIZE); + + uint32_t *l_val = reinterpret_cast<uint32_t *>(l_tocBuffer); + + // Check Error Condition + if (*l_val & LPC::OPB_ERROR_MASK) + { + //PNOR error found + o_errCode = PNOR::LPC_ERR; + BOOTLOADER_TRACE(BTLDR_TRC_PA_FINDTOC_TOC1_LPC_ERR); + //@TODO RTC:203989 Add LPC Error/Status Reg as part of FFDC + terminateExecuteTI(); + } + //Copy Table of Contents from PNOR flash to a local buffer Bootloader::handleMMIO(l_mmioAddr, reinterpret_cast<uint64_t>(l_tocBuffer), @@ -273,7 +306,7 @@ void bl_pnorAccess::findTOC(uint64_t i_pnorEnd, PNOR::SectionData_t * o_TOC, /** * @brief Get the hostboot base image */ -void bl_pnorAccess::getHBBSection(uint64_t i_pnorEnd, +void bl_pnorAccess::getHBBSection(uint64_t i_lpcBar, PNOR::SectionData_t& o_hbbSection, uint32_t& o_errCode, uint64_t& o_pnorStart) @@ -281,9 +314,11 @@ void bl_pnorAccess::getHBBSection(uint64_t i_pnorEnd, BOOTLOADER_TRACE(BTLDR_TRC_PA_GETHBBSECTION_START); do { + + o_errCode = 0; PNOR::SectionData_t l_TOC[PNOR::NUM_SECTIONS+1]; - findTOC(i_pnorEnd, l_TOC, o_errCode, o_pnorStart); + findTOC(i_lpcBar, l_TOC, o_errCode, o_pnorStart); if(o_errCode != PNOR::NO_ERROR) { @@ -318,6 +353,5 @@ void bl_pnorAccess::getHBBSection(uint64_t i_pnorEnd, } } while(0); BOOTLOADER_TRACE(BTLDR_TRC_PA_GETHBBSECTION_FINDTOC_RTN); - } diff --git a/src/bootloader/bootloader.C b/src/bootloader/bootloader.C index 2b9217c98..6cb1642dd 100644 --- a/src/bootloader/bootloader.C +++ b/src/bootloader/bootloader.C @@ -431,11 +431,6 @@ namespace Bootloader{ ? l_blConfigData->lpcBAR : MMIO_GROUP0_CHIP0_LPC_BASE_ADDR; - //pnorEnd is the end of flash, which is base of lpc, plus - //the offset of the FW space, plus the TOP memory address in FW space - uint64_t l_pnorEnd = g_blData->blToHbData.lpcBAR + LPC::LPCHC_FW_SPACE - + PNOR::LPC_TOP_OF_FLASH_OFFSET; - //We dont know what the start of pnor is because we dont know the size uint64_t l_pnorStart = 0; @@ -444,10 +439,11 @@ namespace Bootloader{ // Get location of HB base code in PNOR from TOC // @TODO RTC:138268 Support multiple sides of PNOR in bootloader - bl_pnorAccess::getHBBSection(l_pnorEnd, + bl_pnorAccess::getHBBSection(g_blData->blToHbData.lpcBAR, g_blData->bl_hbbSection, l_errCode, l_pnorStart); + BOOTLOADER_TRACE(BTLDR_TRC_MAIN_GETHBBSECTION_RTN ); if(PNOR::NO_ERROR == l_errCode) |