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| author | Christian Geddes <crgeddes@us.ibm.com> | 2019-01-15 09:47:31 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-13 14:41:48 -0600 |
| commit | aa18e987116a8e03391473c488d0ddb1d5ea8eb5 (patch) | |
| tree | c03228ca69f31fcdf26a84f4cf15e1eb736b5164 /src/HBconfig | |
| parent | b9678e8f9164c44361614e50cf02b6e31c860303 (diff) | |
| download | talos-hostboot-aa18e987116a8e03391473c488d0ddb1d5ea8eb5.tar.gz talos-hostboot-aa18e987116a8e03391473c488d0ddb1d5ea8eb5.zip | |
Add EEPROM caching device op
This commit introduces a new EEPROM_CACHE deviceOp and registers
the OCMB_CHIP, PROC, and DIMM targets to it. This is part of the
larger effort to transition for a "VPD" cache to an "EEPROM" cache
in pnor. The deviceOp is currently called in hwasPlat's
platPresenceDetect if the target in question has a
ATTR_EEPROM_VPD_PRIMARY_INFO associated with it. The layout for the
new EECACHE section in pnor is defined in eepromCache_const.H.
Essentially it is a header that contains an array of record headers
that tell where in the EECACHE pnor section a given cached EEPROM
can be found. All EEPROM targets will be allocated space in the
EECACHE section but only present targets will have their cache
filled in.
RTC: 196805
Change-Id: I49c341c9784be04ddf0259bd444f06c9baf8c6f1
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70520
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/HBconfig')
| -rw-r--r-- | src/HBconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/HBconfig b/src/HBconfig index 72a4c0a45..8b2c5e407 100644 --- a/src/HBconfig +++ b/src/HBconfig @@ -54,7 +54,14 @@ config SUPPORT_PARTIAL_CACHE Support chips that do not have full cache -- intended for early bringup of hardware + config AXONE_BRING_UP default n help Only enable for Axone bringup, will be removed eventually + +config SUPPORT_EEPROM_CACHING + default n + help + If enabled will read data off eeproms and cache in PNOR's + EECACHE section.
\ No newline at end of file |
