diff options
author | Dan Crowell <dcrowell@us.ibm.com> | 2014-12-16 15:12:06 -0600 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-12-18 09:26:29 -0600 |
commit | fcb898b6a85622e0285913a3e61c8d70814d9375 (patch) | |
tree | 935888d3737707d11682944179829e12bb039b5c | |
parent | 492738975921b5eeab19573cc47a5536e867cb02 (diff) | |
download | talos-hostboot-fcb898b6a85622e0285913a3e61c8d70814d9375.tar.gz talos-hostboot-fcb898b6a85622e0285913a3e61c8d70814d9375.zip |
Remove Centaur I2C Master setup from end of IPL
PHYP doesn't use the Centaur engines and Opal will set them up
themselves so HB doesn't need to do this. The immediate
motivation to remove this is to avoid a potential ibscom
collision between OCC and HB.
Change-Id: I7086e6e5105eb0d40f4727e695e49c5c5d486eb2
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14932
Tested-by: Jenkins Server
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
-rw-r--r-- | src/include/usr/i2c/i2cif.H | 2 | ||||
-rwxr-xr-x | src/usr/i2c/i2c.C | 97 |
2 files changed, 1 insertions, 98 deletions
diff --git a/src/include/usr/i2c/i2cif.H b/src/include/usr/i2c/i2cif.H index 2599124d6..b6e8ca819 100644 --- a/src/include/usr/i2c/i2cif.H +++ b/src/include/usr/i2c/i2cif.H @@ -30,7 +30,7 @@ namespace I2C /** * @brief This function will handle everything required to setup the master - * engines. + * engines on the processor. * Mainly, as of current code, this is being used to write the I2C Bus * Divisor values to the master engines to be used by Phyp. * diff --git a/src/usr/i2c/i2c.C b/src/usr/i2c/i2c.C index 0fbabed73..e9c0539df 100755 --- a/src/usr/i2c/i2c.C +++ b/src/usr/i2c/i2c.C @@ -2242,103 +2242,6 @@ errlHndl_t i2cSetupMasters ( void ) tS.getTopLevelTarget( sysTarget ); assert( sysTarget != NULL ); - // Get list of the Centaur Chips - TARGETING::TargetHandleList centList; - TARGETING::PredicateCTM predCent( TARGETING::CLASS_CHIP, - TARGETING::TYPE_MEMBUF ); - tS.getAssociated( centList, - sysTarget, - TARGETING::TargetService::CHILD, - TARGETING::TargetService::ALL, - &predCent ); - - if( 0 == centList.size() ) - { - TRACFCOMP( g_trac_i2c, - INFO_MRK"i2cSetupMasters: No Centaur chips found!" ); - } - - TRACUCOMP( g_trac_i2c, - INFO_MRK"I2C Master Centaurs: %d", - centList.size() ); - - // Setup each Membuf Master - for( uint32_t centaur = 0; centaur < centList.size(); centaur++ ) - { - if( !centList[centaur]->getAttr<TARGETING::ATTR_HWAS_STATE>().functional ) - { - // Non functional - TRACDCOMP( g_trac_i2c, - INFO_MRK"Centaur %d is non-functional", - centaur ); - continue; - } - - // Setup Host-based I2C - args.switches.useHostI2C = 1; - args.switches.useFsiI2C = 0; - - for( uint32_t engine = 0; - engine < CENTAUR_MASTER_ENGINES; - engine++ ) - { - args.engine = engine; - - // Write Mode Register: - mode.value = 0x0ull; - - // Hardcode to 400KHz for PHYP - err = i2cSetBusVariables ( centList[centaur], - I2C_BUS_SPEED_400KHZ, - args ); - - if( err ) - { - TRACFCOMP( g_trac_i2c, - ERR_MRK"i2cSetupMasters: Error Setting Bus " - "Speed Variables-Centaur, engine: %d", - engine ); - - // If we get error skip setting this target, but still need - // to continue to program the I2C Bus Divisor for the rest - errlCommit( err, - I2C_COMP_ID ); - continue; - } - - mode.bit_rate_div = args.bit_rate_divisor; - - err = i2cRegisterOp( DeviceFW::WRITE, - centList[centaur], - &mode.value, - I2C_REG_MODE, - args ); - - if( err ) - { - TRACFCOMP( g_trac_i2c, - ERR_MRK"i2cSetupMasters: Error reading from " - "Centaur, engine: %d", - engine ); - - // If we get errors on these reads, we still need to continue - // to program the I2C Bus Divisor for the rest - errlCommit( err, - I2C_COMP_ID ); - } - } - - if( err ) - { - break; - } - } - - if( err ) - { - break; - } - // Get list of Procs TARGETING::TargetHandleList procList; TARGETING::PredicateCTM predProc( TARGETING::CLASS_CHIP, |