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| author | Yue Du <daviddu@us.ibm.com> | 2016-11-15 13:20:38 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-12-05 18:37:23 -0500 |
| commit | f8578ea4bc4244b999d5114bc752c24306a19586 (patch) | |
| tree | 672b2f00c014315cedf22703508bea2d167e639b | |
| parent | 39e3956aba9ee7b7edf53aadcdec8f506429369b (diff) | |
| download | talos-hostboot-f8578ea4bc4244b999d5114bc752c24306a19586.tar.gz talos-hostboot-f8578ea4bc4244b999d5114bc752c24306a19586.zip | |
STOP: fix fuse core mode
Change-Id: If00c2c59e62d1a0905c49e37f6b17732971e8b7f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32674
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ADAM S. HALE <ashale@us.ibm.com>
Dev-Ready: ADAM S. HALE <ashale@us.ibm.com>
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33272
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H | 2 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 670028cbe..135309866 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -128,7 +128,7 @@ HCD_HDR_UINT64( magic_number, CPMR_MAGIC_NUMBER); // CPMR_1.0 HCD_HDR_UINT32( cpmrbuildDate, 0); HCD_HDR_UINT32( cpmrVersion, 0); HCD_HDR_UINT8_VEC (cpmrReserveFlags, 7, 0); -HCD_HDR_UINT8 ( fuseModeStatus, 0); +HCD_HDR_UINT8 ( fusedModeStatus, 0); HCD_HDR_UINT32( cmeImgOffset, 0); HCD_HDR_UINT32( cmeImgLength, 0); HCD_HDR_UINT32( cmeCommonRingOffset, 0); diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 48a929d56..40de12f95 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -616,11 +616,11 @@ extern "C" cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; //populate CPMR header - pCpmrHdr->fuseModeStatus = i_fusedState ? FUSED_MODE : NONFUSED_MODE; + pCpmrHdr->fusedModeStatus = i_fusedState ? FUSED_MODE : NONFUSED_MODE; pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(i_fusedState ? 1 : 0); FAPI_INF("CPMR SR"); - FAPI_INF(" Fuse Mode = 0x%08X CME Image Flag = 0x%08X", pCpmrHdr->fuseModeStatus, + FAPI_INF(" Fuse Mode = 0x%08X CME Image Flag = 0x%08X", pCpmrHdr->fusedModeStatus, SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); FAPI_DBG(" Offset = 0x%08X, Header value 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset) * 32, |
