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author | Brian Silver <bsilver@us.ibm.com> | 2016-04-06 11:42:58 -0500 |
---|---|---|
committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-04-22 15:39:21 -0400 |
commit | e429379831fc65df049855f443ec623dfbc9e746 (patch) | |
tree | 6a9f2c9cff84ce07510d4bddd50b6fcce8a3222e | |
parent | 33267ef530a0fb646157c705b8b9b545c06aad2e (diff) | |
download | talos-hostboot-e429379831fc65df049855f443ec623dfbc9e746.tar.gz talos-hostboot-e429379831fc65df049855f443ec623dfbc9e746.zip |
Add relative position functions
Fix mcbist/ccs port specifications for MC23
Change-Id: I6dbd88b24e10c449f21b4eec82acae8fe3e2ba69
Original-Change-Id: I7c8d72db40c2df6d5951dcb04a0ffc76133e61c6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22963
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23412
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
13 files changed, 110 insertions, 52 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.H index 69dbcb9a3..1242d2644 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.H @@ -32,7 +32,7 @@ #include <fapi2.H> -#include <mss_attribute_accessors.H> +#include <lib/mss_attribute_accessors.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index e6295daeb..6cb8a797d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -21,7 +21,7 @@ #define MSS_ATTR_ACCESS_H_ #include <fapi2.H> -#include <mss_utils.H> +#include <lib/mss_utils.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C index a3b13767f..1e2a5812d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/apb.C @@ -53,11 +53,11 @@ fapi2::ReturnCode apb<fapi2::TARGET_TYPE_MCA>::fir_check( FAPI_TRY( read_error_status0(i_target, l_data) ); FAPI_ASSERT( l_data.getBit<TT::INVALID_ADDRESS>() == false, - fapi2::MSS_APB_INVALID_ADDRESS().set_PORT_POSITION(mss::pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_APB_INVALID_ADDRESS().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), "APB interface is reporting an invalid address on %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::WRITE_PARITY_ERR>() == false, - fapi2::MSS_APB_WR_PAR_ERR().set_PORT_POSITION(mss::pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_APB_WR_PAR_ERR().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), "APB interface is reporting a read/write parity error on %s", mss::c_str(i_target) ); } @@ -67,35 +67,35 @@ fapi2::ReturnCode apb<fapi2::TARGET_TYPE_MCA>::fir_check( FAPI_TRY( read_fir_err0(i_target, l_data) ); FAPI_ASSERT( l_data.getBit<TT::FATAL_FSM>() == false, - fapi2::MSS_FATAL_FSM_PHYTOP().set_PORT_POSITION(mss::pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_FATAL_FSM_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), "APB interface is reporting a fatal FSM error in PHYTOP %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::FATAL_PARITY>() == false, - fapi2::MSS_FATAL_PARITY_PHYTOP().set_PORT_POSITION(mss::pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_FATAL_PARITY_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), "APB interface is reporting a fatal parity error in PHYTOP %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::FSM>() == false, - fapi2::MSS_FSM_PHYTOP().set_PORT_POSITION(mss::pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_FSM_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), "APB interface is reporting a recoverable FSM error in PHYTOP %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::PARITY>() == false, - fapi2::MSS_PARITY_PHYTOP().set_PORT_POSITION(mss::pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_PARITY_PHYTOP().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), "APB interface is reporting a recoverable parity error in PHYTOP %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::FATAL_ADR52_MASTER>() == false, - fapi2::MSS_FATAL_ADR52_MASTER().set_PORT_POSITION(mss::pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_FATAL_ADR52_MASTER().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), "APB interface is reporting a fatal register parity error in ADR52 master side logic %s", mss::c_str(i_target) ); FAPI_ASSERT( l_data.getBit<TT::FATAL_ADR52_SLAVE>() == false, - fapi2::MSS_FATAL_ADR52_SLAVE().set_PORT_POSITION(mss::pos(i_target)).set_TARGET_IN_ERROR(i_target), + fapi2::MSS_FATAL_ADR52_SLAVE().set_PORT_POSITION(mss::fapi_pos(i_target)).set_TARGET_IN_ERROR(i_target), "APB interface is reporting a fatal register parity error in ADR52 slave side logic %s", mss::c_str(i_target) ); l_data.extractToRight<TT::FSM_DP16, TT::FSM_DP16_LEN>(l_dp16); FAPI_ASSERT( l_dp16 == 0, fapi2::MSS_FSM_DP16() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_DP16_POSITION(l_dp16) .set_TARGET_IN_ERROR(i_target), "APB interface is reporting a recoverable FSM state checker error in DP16 %s 0x%x", diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 278fed255..9dfc4d727 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -553,7 +553,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC // out all the possible failures. FAPI_ASSERT( l_err_data == 0, fapi2::MSS_DRAMINIT_TRAINING_PHY_CONTROL_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_TARGET_IN_ERROR(i_target), "PHY reported a control error during initial calibration port: %s, pc_error_status0 err: 0x%016llx", mss::c_str(i_target), uint64_t(l_err_data) @@ -601,7 +601,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT(mss::bit_count(l_errors) == 1, fapi2::MSS_DRAMINIT_TRAINING_MULTIPLE_ERRORS() .set_FAILED_STEPS(uint64_t(l_err_data)) - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed multiple training steps. dimm: %s, cal err: 0x%016llx", @@ -610,7 +610,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT( ! l_err_data.getBit<TT::INIT_CAL_ERROR_WR_LEVEL>(), fapi2::MSS_DRAMINIT_TRAINING_WR_LVL_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed write leveling. dimm: %s, cal err: 0x%016llx", @@ -619,7 +619,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT( ! l_err_data.getBit<TT::INIT_CAL_ERROR_INITIAL_PAT_WRITE>(), fapi2::MSS_DRAMINIT_TRAINING_INITIAL_PAT_WRITE_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed initial pattern write. dimm: %s, cal err: 0x%016llx", @@ -628,7 +628,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT( ! l_err_data.getBit<TT::INIT_CAL_ERROR_DQS_ALIGN>(), fapi2::MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed DQS alignenment. dimm: %s, cal err: 0x%016llx", @@ -637,7 +637,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT( ! l_err_data.getBit<TT::INIT_CAL_ERROR_RDCLK_ALIGN>(), fapi2::MSS_DRAMINIT_TRAINING_RD_CLK_SYS_CLK_ALIGNMENT_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed read clk alignenment. dimm: %s, cal err: 0x%016llx", @@ -646,7 +646,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT( ! l_err_data.getBit<TT::INIT_CAL_ERROR_READ_CTR>(), fapi2::MSS_DRAMINIT_TRAINING_RD_CENTERING_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed read centering. dimm: %s, cal err: 0x%016llx", @@ -655,7 +655,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT( ! l_err_data.getBit<TT::INIT_CAL_ERROR_WRITE_CTR>(), fapi2::MSS_DRAMINIT_TRAINING_WR_CENTERING_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed write centering. dimm: %s, cal err: 0x%016llx", @@ -664,7 +664,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT( ! l_err_data.getBit<TT::INIT_CAL_ERROR_INITIAL_COARSE_WR>(), fapi2::MSS_DRAMINIT_TRAINING_INITIAL_COARSE_WR_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed initial coarse write. dimm: %s, cal err: 0x%016llx", @@ -673,7 +673,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT( ! l_err_data.getBit<TT::INIT_CAL_ERROR_COARSE_RD>(), fapi2::MSS_DRAMINIT_TRAINING_COARSE_RD_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed coarse read. dimm: %s, cal err: 0x%016llx", @@ -682,7 +682,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT( ! l_err_data.getBit<TT::INIT_CAL_ERROR_CUSTOM_RD>(), fapi2::MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_RD_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed custom read. dimm: %s, cal err: 0x%016llx", @@ -691,7 +691,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT( ! l_err_data.getBit<TT::INIT_CAL_ERROR_CUSTOM_WR>(), fapi2::MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_WR_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed custom write. dimm: %s, cal err: 0x%016llx", @@ -700,7 +700,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target<TARGET_TYPE_MC FAPI_ASSERT( ! l_err_data.getBit<TT::INIT_CAL_ERROR_DIGITAL_EYE>(), fapi2::MSS_DRAMINIT_TRAINING_DIGITAL_EYE_ERROR() - .set_PORT_POSITION(mss::pos(i_target)) + .set_PORT_POSITION(mss::fapi_pos(i_target)) .set_RANKGROUP_POSITION(l_rank_pairs) .set_TARGET_IN_ERROR(l_failed_dimm), "Initial CAL failed digital eye. dimm: %s, cal err: 0x%016llx", diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/port/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/port/port.H index 71b1ae6e2..953cfd4c2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/port/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/port/port.H @@ -33,6 +33,7 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> +#include <p9_mc_scom_addresses_fld.H> // I have a dream that port code can be shared among controllers. So, I drive the // engine from a set of traits. This might be folly. Allow me to dream. BRS @@ -79,19 +80,6 @@ class portTraits<fapi2::TARGET_TYPE_MCA> namespace mss { -/// -/// @brief Given a DIMM, return it's port number. -/// @param[in] i_target the DIMM in question -/// @return the port number it's attached to -/// -// Note: Make this a template and dispatch at runtime to determine if the parent of -// the DIMM is an MBA or an MCA BRS -// -inline uint64_t port( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target ) -{ - // Our port is the position of our MCA - return mss::pos( i_target.getParent<fapi2::TARGET_TYPE_MCA>() ); -} /// /// @brief Change the state of the port_fail_disable bit diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/pos.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/pos.H index e121ea870..970706ac3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/pos.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/pos.H @@ -31,6 +31,7 @@ #define _MSS_POS_H_ #include <fapi2.H> +#include <lib/shared/mss_const.H> namespace mss { @@ -48,6 +49,9 @@ class posTraits typedef uint8_t pos_type; }; +/// +/// @brief DIMM Trait class for the mss::pos functions +/// template<> class posTraits<fapi2::TARGET_TYPE_DIMM> { @@ -55,6 +59,9 @@ class posTraits<fapi2::TARGET_TYPE_DIMM> typedef uint32_t pos_type; }; +/// +/// @brief Processor Trait class for the mss::pos functions +/// template<> class posTraits<fapi2::TARGET_TYPE_PROC_CHIP> { @@ -65,8 +72,8 @@ class posTraits<fapi2::TARGET_TYPE_PROC_CHIP> /// /// @brief Return a target's position from a fapi2 target /// @tparam T the fapi2::TargetType -/// @param[in] i_target a DIMM target representing the DIMM in question -/// @return The position +/// @param[in] i_target a target representing the target in question +/// @return The position relative to the chip /// template< fapi2::TargetType T, typename TT = posTraits<T> > inline typename TT::pos_type pos(const fapi2::Target<T>& i_target) @@ -89,6 +96,11 @@ fapi_try_exit: return 0; } +/// +/// @brief Return a DIMM's position from a fapi2 target +/// @param[in] i_target a target representing the target in question +/// @return The position relative to the chip +/// template<> inline posTraits<fapi2::TARGET_TYPE_DIMM>::pos_type pos(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) { @@ -109,9 +121,14 @@ fapi_try_exit: } +/// +/// @brief Return a processor's position from a fapi2 target +/// @param[in] i_target a target representing the target in question +/// @return The position relative to the chip +/// template<> -inline posTraits<fapi2::TARGET_TYPE_PROC_CHIP>::pos_type pos(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& - i_target) +inline posTraits<fapi2::TARGET_TYPE_PROC_CHIP>::pos_type pos( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { posTraits<fapi2::TARGET_TYPE_PROC_CHIP>::pos_type i_pos = 0; @@ -129,5 +146,60 @@ fapi_try_exit: return 0; } + + +/// +/// @brief Return a target's relative position from a fapi2 target +/// @tparam T the fapi2::TargetType +/// @tparam R the fapi2::TargetType we want the position relative to +/// @param[in] i_target a target representing the target in question +/// @return The position relative to chiplet R +/// +template< fapi2::TargetType R, fapi2::TargetType T, typename TT = posTraits<T> > +inline typename TT::pos_type relative_pos(const fapi2::Target<T>& i_target); + +template<> +inline uint8_t relative_pos<fapi2::TARGET_TYPE_MCBIST>(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) +{ + return pos(i_target) % PORTS_PER_MCBIST; +} + + + +/// +/// @brief Return a target's fapi position from a fapi2 target +/// @tparam T the fapi2::TargetType +/// @param[in] i_target a target representing the target in question +/// @return The position relative to the system +/// +template< fapi2::TargetType T, typename TT = posTraits<T> > +inline uint32_t fapi_pos(const fapi2::Target<T>& i_target) +{ + +// Doesn't look like ATTR_FAPI_POS is supported in Cronus yet, so we'll +// use our chip-relative position for the time being. +#ifdef ATTR_FAPI_POS_SUPPORTED + uint32_t i_pos = 0; + + // Don't use FAPI_TRY as you'll mess up fapi2::current_err which + // lmits where this can be used. + if (FAPI_ATTR_GET(fapi2::ATTR_FAPI_POS, i_target, i_pos) != fapi2::FAPI2_RC_SUCCESS) + { + goto fapi_try_exit; + } + + return i_pos; + +fapi_try_exit: + // If we can't get our fapi position, we're in other trouble + FAPI_ERR("can't get our fapi position"); + fapi2::Assert(false); + return 0; +#else + return pos(i_target); +#endif +} + + } #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index ba2c6ef9c..8555d5f00 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -128,7 +128,7 @@ extern "C" // Uses address register set 0 mss::mcbist::subtest_t<TARGET_TYPE_MCBIST> l_fw_subtest = mss::mcbist::write_subtest<TARGET_TYPE_MCBIST>(); - l_fw_subtest.enable_port(mss::pos(p)); + l_fw_subtest.enable_port(mss::relative_pos<TARGET_TYPE_MCBIST>(p)); // Run in ECC mode @@ -142,7 +142,7 @@ extern "C" // Uses address register set 0 mss::mcbist::subtest_t<TARGET_TYPE_MCBIST> l_fr_subtest = mss::mcbist::read_subtest<TARGET_TYPE_MCBIST>(); - l_fr_subtest.enable_port(mss::pos(p)); + l_fr_subtest.enable_port(mss::relative_pos<TARGET_TYPE_MCBIST>(p)); // Run in ECC mode @@ -189,7 +189,7 @@ extern "C" // Just one port for now. Per Shelton we need to set this in maint adress mode // even tho we specify the port/dimm in the subtest. fapi2::buffer<uint8_t> l_port; - l_port.setBit(mss::pos(p)); + l_port.setBit(mss::relative_pos<TARGET_TYPE_MCBIST>(p)); l_program.select_ports(l_port >> 4); // Kick it off, wait for a result diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C index 81ea37d18..fc3abcfbd 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C @@ -40,7 +40,7 @@ #include <p9_mss_eff_grouping.H> #include <p9_fbc_utils.H> #include <map> -#include <memory_size.H> +#include <lib/eff_config/memory_size.H> ///---------------------------------------------------------------------------- /// Constant definitions diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.mk b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.mk index 9e44f2c09..2ab3121f2 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.mk +++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.mk @@ -19,6 +19,5 @@ PROCEDURE=p9_mss_eff_grouping OBJS+=p9_fbc_utils.o lib$(PROCEDURE)_DEPLIBS+=mss -$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/memory/lib/) -$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/memory/lib/eff_config/) +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/memory/) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C index 7bcd06413..60bbb8a88 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C @@ -37,7 +37,7 @@ #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> #include <map> -#include <memory_size.H> +#include <lib/eff_config/memory_size.H> ///---------------------------------------------------------------------------- /// Constant definitions diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.mk b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.mk index c733a9575..14f757e44 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.mk +++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.mk @@ -18,6 +18,5 @@ # IBM_PROLOG_END_TAG PROCEDURE=p9_mss_setup_bars lib$(PROCEDURE)_DEPLIBS+=mss -$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/memory/lib/) -$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/memory/lib/eff_config/) +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/memory/) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C index a5b2e7bff..a700ae65b 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C @@ -37,7 +37,7 @@ //------------------------------------------------------------------------------ #include <p9_throttle_sync.H> #include <fapi2.H> -#include <find.H> +#include <lib/utils/find.H> ///---------------------------------------------------------------------------- /// Constant definitions diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.mk b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.mk index b71a92e15..827fd2f58 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.mk +++ b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.mk @@ -18,5 +18,5 @@ # IBM_PROLOG_END_TAG PROCEDURE=p9_throttle_sync lib$(PROCEDURE)_DEPLIBS+=mss -$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/memory/lib/utils/) +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/memory/) $(call BUILD_PROCEDURE) |