diff options
| author | Stephen Glancy <sglancy@us.ibm.com> | 2018-01-12 09:42:10 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-01-13 14:15:15 -0500 |
| commit | e369ee31b0c5fbb6e5b65807938140002ea6c162 (patch) | |
| tree | 653ae973cabd1b84b0216e9a865905e2cc55006e | |
| parent | 6650adcec6acc4358ded7a9e2256d096123fde8b (diff) | |
| download | talos-hostboot-e369ee31b0c5fbb6e5b65807938140002ea6c162.tar.gz talos-hostboot-e369ee31b0c5fbb6e5b65807938140002ea6c162.zip | |
Updates custom RD CTR pattern
Change-Id: I7a23b502626df75f371957345f18d788a534ba87
CQ:SW413773
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51888
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H | 6 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 8 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index 783fd05aa..d24cbea29 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -9381,7 +9381,7 @@ fapi_try_exit: /// pattern read There can be two patterns used here. This attribute is before /// swizzling for endianness of the registers. CODE WILL SWIZZLE FOR THE SYSTEM The /// first 0-15 bits are for PATTERN0, bits 16-32 are for PATTERN1. If this attribute -/// is set to 0, using the default values of: 0x13EC for PATTERN0 0x02FD for +/// is set to 0, using the default values of: 0x8E8E for PATTERN0 0x2BC6 for /// PATTERN1 Set to default in /// eff_config /// @@ -9411,7 +9411,7 @@ fapi_try_exit: /// pattern read There can be two patterns used here. This attribute is before /// swizzling for endianness of the registers. CODE WILL SWIZZLE FOR THE SYSTEM The /// first 0-15 bits are for PATTERN0, bits 16-32 are for PATTERN1. If this attribute -/// is set to 0, using the default values of: 0x13EC for PATTERN0 0x02FD for +/// is set to 0, using the default values of: 0x8E8E for PATTERN0 0x2BC6 for /// PATTERN1 Set to default in /// eff_config /// @@ -9442,7 +9442,7 @@ fapi_try_exit: /// pattern read There can be two patterns used here. This attribute is before /// swizzling for endianness of the registers. CODE WILL SWIZZLE FOR THE SYSTEM The /// first 0-15 bits are for PATTERN0, bits 16-32 are for PATTERN1. If this attribute -/// is set to 0, using the default values of: 0x13EC for PATTERN0 0x02FD for +/// is set to 0, using the default values of: 0x8E8E for PATTERN0 0x2BC6 for /// PATTERN1 Set to default in /// eff_config /// diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index eb57d043f..a073b35fb 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -1981,13 +1981,13 @@ The first 0-15 bits are for PATTERN0, bits 16-32 are for PATTERN1. If this attribute is set to 0, using the default values of: - 0x13EC for PATTERN0 - 0x02FD for PATTERN1 + 0x8E8E for PATTERN0 + 0x2BC6 for PATTERN1 Set to default in eff_config </description> <valueType>uint32</valueType> <initToZero></initToZero> - <enum>DEFAULT_PATTERN0 = 0xEA0C, DEFAULT_PATTERN1 = 0xA6C9</enum> + <enum>DEFAULT_PATTERN0 = 0x8E8E, DEFAULT_PATTERN1 = 0x2BC6</enum> <writeable/> <array>2</array> <mssAccessorName>custom_training_adv_patterns</mssAccessorName> @@ -2013,7 +2013,7 @@ </description> <valueType>uint32</valueType> <initToZero></initToZero> - <enum>DEFAULT_PATTERN0 = 0x13EC, DEFAULT_PATTERN1 = 0x02FD</enum> + <enum>DEFAULT_PATTERN0 = 0xEA0C, DEFAULT_PATTERN1 = 0xA6C9</enum> <writeable/> <array>2</array> <mssAccessorName>custom_training_adv_backup_patterns</mssAccessorName> |
