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| author | Zane Shelley <zshelle@us.ibm.com> | 2018-07-27 09:40:13 -0500 |
|---|---|---|
| committer | Zane C. Shelley <zshelle@us.ibm.com> | 2018-07-27 21:29:50 -0500 |
| commit | df829c02d7d5ef1c76ac73c4ef3b18d3e7f58820 (patch) | |
| tree | e0092a79e695b6058d44b835eb0aaa8546f393ae | |
| parent | 10ccdde9f0637c7fb1c01c8f8ceaa9e7dcc44191 (diff) | |
| download | talos-hostboot-df829c02d7d5ef1c76ac73c4ef3b18d3e7f58820.tar.gz talos-hostboot-df829c02d7d5ef1c76ac73c4ef3b18d3e7f58820.zip | |
PRD: segfault in PLL domain code
Change-Id: Iaf3661c02edbe910cd38247e8817e80b5b62d1f1
CQ: SW439652
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63466
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63497
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
| -rw-r--r-- | src/usr/diag/prdf/common/plat/p9/prdfP9PllDomain.C | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/src/usr/diag/prdf/common/plat/p9/prdfP9PllDomain.C b/src/usr/diag/prdf/common/plat/p9/prdfP9PllDomain.C index 2d9c25752..514eb9152 100644 --- a/src/usr/diag/prdf/common/plat/p9/prdfP9PllDomain.C +++ b/src/usr/diag/prdf/common/plat/p9/prdfP9PllDomain.C @@ -130,18 +130,19 @@ int32_t PllDomain::Analyze(STEP_CODE_DATA_STRUCT & serviceData, ExtensibleChip * l_chip = LookUp(index); - // Check if this chip has a clock error - ExtensibleChipFunction * l_query = - l_chip->getExtensibleFunction("CheckErrorType"); - rc |= (*l_query)(l_chip, - PluginDef::bindParm<uint32_t &> (l_errType)); - if ( !PlatServices::isFunctional(l_chip->getTrgt()) ) { // The chip is now non-functional. nfchips.push_back( l_chip ); + continue; } + // Check if this chip has a clock error + ExtensibleChipFunction * l_query = + l_chip->getExtensibleFunction("CheckErrorType"); + rc |= (*l_query)(l_chip, + PluginDef::bindParm<uint32_t &> (l_errType)); + // Continue if no clock errors reported on this chip if ( 0 == l_errType ) continue; @@ -173,8 +174,8 @@ int32_t PllDomain::Analyze(STEP_CODE_DATA_STRUCT & serviceData, // Update error lists if (l_errType & SYS_PLL_UNLOCK ) sysRefList.push_back( l_chip ); if (l_errType & PCI_PLL_UNLOCK ) pciList.push_back( l_chip ); - if (l_errType & SYS_OSC_FAILOVER) mfFoList.push_back( l_chip ); - if (l_errType & PCI_OSC_FAILOVER) sysRefFoList.push_back( l_chip ); + if (l_errType & PCI_OSC_FAILOVER) mfFoList.push_back( l_chip ); + if (l_errType & SYS_OSC_FAILOVER) sysRefFoList.push_back( l_chip ); } // end for each chip in domain @@ -302,7 +303,7 @@ int32_t PllDomain::Analyze(STEP_CODE_DATA_STRUCT & serviceData, // Set Signature serviceData.service_data->GetErrorSignature()-> - setChipId(pciList[0]->getHuid()); + setChipId(mfFoList[0]->getHuid()); serviceData.service_data->SetErrorSig( PRDFSIG_MF_REF_FAILOVER ); } if (sysRefFoList.size() > 0) @@ -311,7 +312,7 @@ int32_t PllDomain::Analyze(STEP_CODE_DATA_STRUCT & serviceData, // Set Signature serviceData.service_data->GetErrorSignature()-> - setChipId(pciList[0]->getHuid()); + setChipId(sysRefFoList[0]->getHuid()); serviceData.service_data->SetErrorSig( PRDFSIG_SYS_REF_FAILOVER ); } |
