INITPROC: Hostboot SW250073 Mfg threshold changes

Change-Id: I2a1759069f8ba3870ab3b826a77092a0e86780c8
CQ:SW250073
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9568
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 61 insertions, 4 deletions

diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile
index e5046ecd8..e2bbd4370 100644
--- a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile
@@ -1,8 +1,9 @@
-#-- $Id: cen.dmi.custom.scom.initfile,v 1.20 2014/02/14 15:57:01 jgrell Exp $
+#-- $Id: cen.dmi.custom.scom.initfile,v 1.21 2014/02/20 15:19:02 garyp Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.21|garyp   |02/19/14|Added rx_min_eye_width and rx_min_eye_height for manufacturing and lab thresholding
 #--     1.20|jgrell  |02/14/14|Corrected FIR_ACTION1 and FIR_MASK settings for SW245013
 #--     1.19|jgrell  |02/12/14|Added FIR_ACTION1 setting and changed FIR_MASK setting for SW245013
 #--                           |Added rx_wt_lane_disabled=1 on lane 17 for SW244284
@@ -64,6 +65,18 @@ define def_IS_VBU = (SYS.ATTR_IS_SIMULATION == 1);
 
 define def_all_lanes=11111;
 
+#--*****************
+#-- set rx_min_eye_width and rx_min_eye_height if in manufacturing mode
+#--*****************
+scom 0x800.0b(rx_result_chk_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+        bits,                         	scom_data, 	expr;
+    rx_min_eye_width, SYS.ATTR_MNFG_DMI_MIN_EYE_WIDTH,              ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
+    rx_min_eye_height, SYS.ATTR_MNFG_DMI_MIN_EYE_HEIGHT,            ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
+}
+
+
+
+
 #--***********************************************************************************
 #-------------------------------------------------------------------------------------
 #     __                        ____                             __  __
diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
index f63380a2c..800df287c 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
@@ -1,8 +1,9 @@
-#-- $Id: p8.abus.custom.scom.initfile,v 1.13 2014/02/12 20:04:14 jgrell Exp $
+#-- $Id: p8.abus.custom.scom.initfile,v 1.14 2014/02/20 15:28:36 garyp Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.14|garyp   |02/19/14| Added rx_min_eye_width and rx_min_eye_height for manufacturing and lab thresholding
 #--     1.13|jgrell  |02/12/14| Added rx_wt_lane_disabled=1 on lane 17 (SW244284)
 #--     1.12|jgrell  |12/03/13| Set rx_eo_ddc_timeout_sel to 110 for DD2
 #--     1.11|jgrell  |10/29/13| Changed rx_ds_timeout_sel setting to 111
@@ -46,6 +47,16 @@ include edi.io.define
 
 define def_all_lanes=11111;
 
+#--*****************
+#-- set rx_min_eye_width and rx_min_eye_height if in manufacturing mode
+#--*****************
+scom 0x800.0b(rx_result_chk_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) {
+    bits,                         	scom_data, 	expr;
+    rx_min_eye_width, SYS.ATTR_MNFG_ABUS_MIN_EYE_WIDTH,             ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
+    rx_min_eye_height, SYS.ATTR_MNFG_ABUS_MIN_EYE_HEIGHT,           ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
+}
+
+
 
 #--******************************************************************************
 #--------------------------------------------------------------------------------
diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile
index a45893c13..5d3e10797 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile
@@ -1,8 +1,9 @@
-#-- $Id: p8.dmi.custom.scom.initfile,v 1.20 2013/12/04 17:25:28 jgrell Exp $
+#-- $Id: p8.dmi.custom.scom.initfile,v 1.21 2014/02/20 15:28:48 garyp Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.21|garyp   |02/19/14|Added rx_min_eye_width and rx_min_eye_height for manufacturing and lab thresholding
 #--     1.20|jgrell  |12/03/13|Set rx_eo_ddc_timeout_sel to 110 for DD2
 #--     1.19|jgrell  |10/29/13|Changed rx_ds_timeout_sel setting to 111
 #--     1.18|jgrell  |10/28/13|Re-enabled recal bits for DD2+ hw
@@ -67,6 +68,16 @@ define def_all_lanes=11111;
 #-------------------------------------------------------------------------------------
 #--***********************************************************************************
 
+#--*****************
+#-- set rx_min_eye_width and rx_min_eye_height if in manufacturing mode
+#--*****************
+scom 0x800.0b(rx_result_chk_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) {
+    bits,                         	scom_data, 	expr;
+    rx_min_eye_width, SYS.ATTR_MNFG_DMI_MIN_EYE_WIDTH,              ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
+    rx_min_eye_height, SYS.ATTR_MNFG_DMI_MIN_EYE_HEIGHT,            ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
+}
+
+
 #--***********************************************************************************
 #-------------------------------------------------------------------------------------
 #     __                        ____                             __  __
diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
index a8efed802..d76204a88 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
@@ -1,8 +1,9 @@
-#-- $Id: p8.xbus.custom.scom.initfile,v 1.7 2013/12/04 17:25:29 jgrell Exp $
+#-- $Id: p8.xbus.custom.scom.initfile,v 1.8 2014/02/20 15:29:11 garyp Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.8 |garyp   |02/19/14|Added rx_min_eye_width for manufacturing and lab thresholding
 #--     1.7 |jgrell  |12/03/13|Set rx_sls_extend_sel to 001 for DD2
 #--     1.5 |jgrell  |09/17/13|Added DD2 specific inits
 #--     1.3 |jgrell  |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab.
@@ -55,6 +56,27 @@ define def_all_lanes=11111;
 #-------------------------------------------------------------------------------------
 #--***********************************************************************************
 
+#--*****************
+#-- set rx_min_eye_width if in manufacturing mode
+#--*****************
+scom 0x800.0b(rx_result_chk_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) {
+    bits,                         	scom_data, 	expr;
+    rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH,               ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
+}
+scom 0x800.0b(rx_result_chk_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) {
+        bits,                         	scom_data, 	expr;
+    rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH,               ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
+}
+scom 0x800.0b(rx_result_chk_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) {
+        bits,                         	scom_data, 	expr;
+    rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH,               ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
+}
+scom 0x800.0b(rx_result_chk_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) {
+        bits,                         	scom_data, 	expr;
+    rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH,               ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0);
+}
+
+
 #--***********************************************************************************
 #-------------------------------------------------------------------------------------
 #     __                        ____                             __  __