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| author | Devon Baughen <devon.baughen1@ibm.com> | 2019-04-29 11:11:33 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-08 14:54:11 -0500 |
| commit | c5e2251b0c17916310b54cbf96540ffca1f4b1f7 (patch) | |
| tree | ceace48614514bca6e9dc29de9a04b9a10bd36a0 | |
| parent | bb8ed31934624fb652235a327dbb89b7df05606b (diff) | |
| download | talos-hostboot-c5e2251b0c17916310b54cbf96540ffca1f4b1f7.tar.gz talos-hostboot-c5e2251b0c17916310b54cbf96540ffca1f4b1f7.zip | |
add MR0 shadow regs override to fix wr_vref shmoo
Change-Id: I7729e08564c4cf11b6b434780133d4aa2565006e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76663
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76870
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rwxr-xr-x | src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C index 34aef9a4f..b33f4dad9 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -57,6 +57,7 @@ extern "C" fapi2::ReturnCode p9c_mss_mrs6_DDR4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target) { uint32_t l_ccs_inst_cnt = 0; + fapi2::buffer<uint64_t> l_shadow_data; for (uint8_t l_port_number = 0; l_port_number < 2; ++l_port_number) { @@ -65,6 +66,9 @@ extern "C" FAPI_TRY(mss_mr6_loader(i_target, l_port_number, l_ccs_inst_cnt), " mrs_load Failed"); } + // Get MR0 Shadow reg + FAPI_TRY(fapi2::getScom(i_target, 0x8000c01c0301143f, l_shadow_data)); + // Execute the contents of CCS array if (l_ccs_inst_cnt > 0) { @@ -74,6 +78,17 @@ extern "C" l_ccs_inst_cnt = 0; } + // Put MR0 Shadow Reg + FAPI_INF("Resetting MR0 Shadow registers to %016x", l_shadow_data); + FAPI_TRY(fapi2::putScom(i_target, 0x8001c01c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8000c01c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8001c11c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8000c11c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8001c21c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8000c21c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8001c31c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8000c31c0301143f, l_shadow_data)); + fapi_try_exit: return fapi2::current_err; } |
