Select boot seeprom for slave processors

Add a function to set the boot SEEPROM for the target processor based off
the setting for the master processor.

Change-Id: Ie39ca011952ea5cf10a8b752268116265cc4fabd
RTC:162326
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34022
Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

4 files changed, 144 insertions, 5 deletions

diff --git a/src/include/usr/sbe/sbeif.H b/src/include/usr/sbe/sbeif.H
index 780399005..12324d949 100644
--- a/src/include/usr/sbe/sbeif.H
+++ b/src/include/usr/sbe/sbeif.H
@@ -148,6 +148,18 @@ namespace SBE
     */
     void setNestFreqAttributes( uint32_t i_nestFreq );
 
+    /**
+     * @brief Updates which Seeprom was used to boot the SBE
+     *
+     * @param[in] i_target      Target processor to update
+     *
+     * @param[in] i_masterProc  Master processor target
+     *
+     * @return errlHndl_t       Error log handle on failure.
+     */
+    errlHndl_t updateSbeBootSeeprom(TARGETING::Target* i_target,
+                                    TARGETING::Target* i_masterProc);
+
 } //end namespace SBE
 
 #endif /* _SBEIF_H */
diff --git a/src/usr/isteps/istep08/call_host_slave_sbe_config.C b/src/usr/isteps/istep08/call_host_slave_sbe_config.C
index b71016605..dea506959 100644
--- a/src/usr/isteps/istep08/call_host_slave_sbe_config.C
+++ b/src/usr/isteps/istep08/call_host_slave_sbe_config.C
@@ -146,6 +146,26 @@ void* call_host_slave_sbe_config(void *io_pArgs)
                 // Commit Error
                 errlCommit( l_errl, ISTEP_COMP_ID );
             }
+
+            l_errl = SBE::updateSbeBootSeeprom(l_cpu_target,
+                                               l_pMasterProcTarget);
+
+            if( l_errl )
+            {
+                ErrlUserDetailsTarget(l_cpu_target).addToLog( l_errl );
+
+                // Create IStep error log and cross ref error that occurred
+                l_stepError.addErrorDetails( l_errl );
+
+                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                           "ERROR : updateSbeBootSeeprom target %.8X, "
+                           "PLID=0x%x",
+                           TARGETING::get_huid(l_cpu_target),
+                           l_errl->plid() );
+
+                // Commit Error
+                errlCommit( l_errl, ISTEP_COMP_ID );
+            }
         }
     } // end of cycling through all processor chips
 
diff --git a/src/usr/sbe/sbe_update.C b/src/usr/sbe/sbe_update.C
index ca4128309..0c2cab141 100644
--- a/src/usr/sbe/sbe_update.C
+++ b/src/usr/sbe/sbe_update.C
@@ -58,6 +58,7 @@
 #include    <fapi2.H>
 #include    <fapi2/plat_hwp_invoker.H>
 #include    <fapi2/hwp_executor.H>
+#include    <fapi2/hw_access.H>
 
 //Procedures
 #include <p9_xip_customize.H>
@@ -1667,6 +1668,111 @@ namespace SBE
     }
 
 /////////////////////////////////////////////////////////////////////
+    errlHndl_t updateSbeBootSeeprom(TARGETING::Target* i_target,
+                                    TARGETING::Target* i_masterProc)
+    {
+        TRACFCOMP( g_trac_sbe, ENTER_MRK"updateSbeBootSeeprom()" );
+
+        errlHndl_t err = NULL;
+        fapi2::ReturnCode l_fapi_rc;
+        sbeSeepromSide_t l_masterBootSide = SBE_SEEPROM_INVALID;
+        fapi2::buffer<uint32_t> l_read_reg;
+        const uint32_t l_sbeBootSelectMask = SBE_BOOT_SELECT_MASK >> 32;
+
+        // cast OUR type of target to a FAPI type of target.
+        const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>l_fapiTarg(i_target);
+
+        do{
+            // Grab the SBE boot side for the master proc
+            err = getSbeBootSeeprom(i_masterProc,
+                                    l_masterBootSide);
+
+
+            if( err )
+            {
+                TRACFCOMP( g_trac_sbe,
+                           ERR_MRK"updateSbeBootSeeprom(): getSbeBootSeeprom, "
+                           "RC=0x%X, PLID=0x%lX",
+                           ERRL_GETRC_SAFE(err),
+                           ERRL_GETPLID_SAFE(err));
+                break;
+            }
+
+            // Read PERV_SB_CS_FSI 0x2808 for target proc
+            l_fapi_rc = fapi2::getCfamRegister(l_fapiTarg,
+                                               PERV_SB_CS_FSI,
+                                               l_read_reg);
+
+            if(!l_fapi_rc.isRC(0))
+            {
+                err = fapi2::rcToErrl(l_fapi_rc);
+                err->collectTrace(FAPI_IMP_TRACE_NAME,256);
+                err->collectTrace(FAPI_TRACE_NAME,384);
+
+                TRACFCOMP( g_trac_sbe,
+                           ERR_MRK"updateSbeBootSeeprom(): getCfamRegister, "
+                           "PERV_SB_CS_FSI (0x%.4X), proc target = %.8X, "
+                           "RC=0x%X, PLID=0x%lX",
+                           PERV_SB_CS_FSI, // 0x2808
+                           TARGETING::get_huid(i_target),
+                           ERRL_GETRC_SAFE(err),
+                           ERRL_GETPLID_SAFE(err));
+                break;
+            }
+
+            // Master boot side is 0
+            if(SBE_SEEPROM0 == l_masterBootSide)
+            {
+                // Clear bit for side 1
+                l_read_reg &= ~l_sbeBootSelectMask;
+
+                TRACFCOMP( g_trac_sbe,
+                           INFO_MRK"updateSbeBootSeeprom(): l_read_reg=0x%.8X "
+                           "set SBE boot side 0 for proc=%.8X",
+                           l_read_reg,
+                           TARGETING::get_huid(i_target) );
+            }
+            // Master boot side is 1
+            else if(SBE_SEEPROM1 == l_masterBootSide)
+            {
+                // Set bit for side 1
+                l_read_reg |= l_sbeBootSelectMask;
+
+                TRACFCOMP( g_trac_sbe,
+                           INFO_MRK"updateSbeBootSeeprom(): l_read_reg=0x%.8X "
+                           "set SBE boot side 1 for proc=%.8X",
+                           l_read_reg,
+                           TARGETING::get_huid(i_target) );
+            }
+
+            l_fapi_rc = fapi2::putCfamRegister(l_fapiTarg,
+                                               PERV_SB_CS_FSI,
+                                               l_read_reg);
+
+            if(!l_fapi_rc.isRC(0))
+            {
+                err = fapi2::rcToErrl(l_fapi_rc);
+                err->collectTrace(FAPI_IMP_TRACE_NAME,256);
+                err->collectTrace(FAPI_TRACE_NAME,384);
+
+                TRACFCOMP( g_trac_sbe,
+                           ERR_MRK"updateSbeBootSeeprom(): putCfamRegister, "
+                           "PERV_SB_CS_FSI (0x%.4X), proc target = %.8X, "
+                           "RC=0x%X, PLID=0x%lX",
+                           PERV_SB_CS_FSI, // 0x2808
+                           TARGETING::get_huid(i_target),
+                           ERRL_GETRC_SAFE(err),
+                           ERRL_GETPLID_SAFE(err));
+                break;
+            }
+        }while(0);
+
+        TRACFCOMP( g_trac_sbe, EXIT_MRK"updateSbeBootSeeprom()" );
+
+        return err;
+    }
+
+/////////////////////////////////////////////////////////////////////
     errlHndl_t getSbeInfoState(sbeTargetState_t& io_sbeState,
                                sbeUpdateCheckType& i_check_type)
     {
@@ -2286,7 +2392,7 @@ namespace SBE
                      * @userdata2[0:31]     Size - No Ecc
                      * @userdata2[32:63]    Size - ECC
                      * @devdesc      ECC or Data Miscompare Fail Reading Back
-                     *               SBE Verion Information
+                     *               SBE Version Information
                      */
                     err = new ErrlEntry(ERRL_SEV_PREDICTIVE,
                                         SBE_UPDATE_SEEPROMS,
@@ -3541,7 +3647,7 @@ namespace SBE
              * @userdata2[0:31]   Original SEEPROM 0 CRC
              * @userdata2[32:63]  Original SEEPROM 1 CRC
              * @devdesc      Successful Update of SBE SEEPROM
-             *               SBE Verion Information
+             *               SBE Version Information
              */
             err_info = new ErrlEntry(ERRL_SEV_INFORMATIONAL,
                                      SBE_PERFORM_UPDATE_ACTIONS,
@@ -4195,7 +4301,7 @@ namespace SBE
                          * @reasoncode   SBE_MASTER_VERSION_DOWNLEVEL
                          * @userdata1    Master Target HUID
                          * @userdata2    Master Target Loop Index
-                         * @devdesc      SBE Image Verion Miscompare with
+                         * @devdesc      SBE Image Version Miscompare with
                          *               Master Target
                          */
                         err = new ErrlEntry(ERRL_SEV_PREDICTIVE,
@@ -4353,7 +4459,7 @@ namespace SBE
                      * @reasoncode   SBE_MISCOMPARE_WITH_MASTER_VERSION
                      * @userdata1    Master Target HUID
                      * @userdata2    Comparison Target HUID
-                     * @devdesc      SBE Verion Miscompare with Master Target
+                     * @devdesc      SBE Version Miscompare with Master Target
                      */
                     err = new ErrlEntry(ERRL_SEV_UNRECOVERABLE,
                                         SBE_MASTER_VERSION_COMPARE,
diff --git a/src/usr/sbe/sbe_update.H b/src/usr/sbe/sbe_update.H
index 1f960a3b1..a95c4bdef 100644
--- a/src/usr/sbe/sbe_update.H
+++ b/src/usr/sbe/sbe_update.H
@@ -85,7 +85,8 @@ namespace SBE
                                                 - SBE_SEEPROM_ECC_PAD
                                                 - SBE_VERSION_SPACE_WITH_ECC;
 
-    // Used to read SBE Boot Side from processor (PERV_SB_CS_SCOM 0x00050008)
+    // Used to read SBE Boot Side from processor
+    // (PERV_SB_CS_SCOM 0x00050008 or PERV_SB_CS_FSI 0x2808)
     const uint64_t SBE_BOOT_SELECT_MASK = 0x0000400000000000;
 
     // PNOR SBE and SBEC Partition constants