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| author | Stephen Glancy <sglancy@us.ibm.com> | 2016-10-20 21:49:53 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2016-10-25 18:10:46 -0400 |
| commit | c3ac859496b0ff61be4b3667cbc17921a2a1bdaa (patch) | |
| tree | d2220e1e3bc34715c71343ddfc6df86528ef2ad2 | |
| parent | 244cda98f3c221e9b09e791957646b9177c307be (diff) | |
| download | talos-hostboot-c3ac859496b0ff61be4b3667cbc17921a2a1bdaa.tar.gz talos-hostboot-c3ac859496b0ff61be4b3667cbc17921a2a1bdaa.zip | |
Fixed 1R WR DQS update issue
A known problem with the WR DQS is that it will not update if the
ping pong is not disabled for a one rank pair dimm.
Change-Id: I56b82e05f2a2c598a9dcb99ecddfef4301ab6663
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31596
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31675
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H index bd289c020..b243e3bc4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H @@ -178,6 +178,7 @@ class dp16Traits<fapi2::TARGET_TYPE_MCA> INIT_IO = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_INIT_IO, ADV_PP = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_ADVANCE_PING_PONG, DELAY_PP_HALF = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_DELAY_PING_PONG_HALF, + DISABLE_PING_PONG = MCA_DDRPHY_DP16_DATA_BIT_DIR1_P0_0_01_DISABLE_PING_PONG, TSYS_DATA = MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS, TSYS_DATA_LEN = MCA_DDRPHY_DP16_WRCLK_PR_P0_0_01_TSYS_LEN, @@ -718,7 +719,7 @@ inline void set_output_flush( fapi2::buffer<uint64_t>& o_data, const states i_st } /// -/// @brief Set the init io state +/// @brief Set the init IO state /// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA /// @tparam TT traits type defaults to dp16Traits<T> /// @param[out] o_data the value of the register @@ -759,7 +760,32 @@ inline void set_delay_pp_half( fapi2::buffer<uint64_t>& o_data, const states i_s o_data.writeBit<TT::DELAY_PP_HALF>(i_state); } +/// +/// @brief Set the ping pong disable IO state +/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to dp16Traits<T> +/// @param[in,out] io_data the value of the register +/// @param[in] i_state mss::LOW or mss::HIGH representing the state of the bit +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> > +inline void set_disable_ping_pong( fapi2::buffer<uint64_t>& io_data, const states i_state ) +{ + FAPI_INF("set_init_io %s", (i_state == mss::LOW ? "low" : "high")); + io_data.writeBit<TT::DISABLE_PING_PONG>(i_state); +} +/// +/// @brief Get the ping pong disable IO state +/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to dp16Traits<T> +/// @param[in] i_data the value of the register +/// @return value of the ping pong disable bit +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = dp16Traits<T> > +inline bool get_disable_ping_pong( const fapi2::buffer<uint64_t>& i_data ) +{ + return i_data.getBit<TT::DISABLE_PING_PONG>(); +} /// /// @brief Configure the DP16 sysclk |
