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| author | Brian Silver <bsilver@us.ibm.com> | 2016-10-25 12:19:22 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-10-30 21:46:53 -0400 |
| commit | af4d4d1e34b760404fe078ae9d3f762ca64b612a (patch) | |
| tree | 8fe97e33fff6d3563358985abf9ef2c8f2b3756a | |
| parent | eb8d7a7032f18aef350efac9e70f90d6394ec06a (diff) | |
| download | talos-hostboot-af4d4d1e34b760404fe078ae9d3f762ca64b612a.tar.gz talos-hostboot-af4d4d1e34b760404fe078ae9d3f762ca64b612a.zip | |
Change ADR output registers for init during reset
Change-Id: Ia9d3edf57d12130d9c73279d17a47171cd5f022d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31799
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: JACOB L. HARVEY <jlharvey@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31805
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C index 2a6572a4c..5a51eb329 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C @@ -54,8 +54,8 @@ const std::vector<uint64_t> adr32sTraits<fapi2::TARGET_TYPE_MCA>::DLL_CNFG_REG = // Definition of the ADR32S output driver registers const std::vector<uint64_t> adr32sTraits<fapi2::TARGET_TYPE_MCA>::OUTPUT_DRIVER_REG = { - MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S0, - MCA_DDRPHY_ADR_OUTPUT_DRIVER_FORCE_VALUE0_P0_ADR32S1 + MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0, + MCA_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S1, }; // Definition of the ADR32S duty cycle distortion registers |
