Change VPD for power on and VBU

  Create directory for ZZ, vbu and templates
  Add ZZ vpd, vbu vpd, dq map and cke map templates
  Update hb_temp_defaults.xml with new attributes in MR
  Update the accessor generator to handle non-array attrs
  Update the vpd decoder generator to handle MCS attrs only
  Add comment describing nibble/rank mapping for VPD
  Add support for signed attributes

Change-Id: Ib37b21b72a9885e0a104d63e37005935a4c2d8b9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28961
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28994
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

11 files changed, 813 insertions, 396 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
index 7aa8c264b..aeab68657 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C
@@ -2861,21 +2861,16 @@ fapi2::ReturnCode eff_config::geardown_mode(const fapi2::Target<TARGET_TYPE_DIMM
     // Attribute storage
     uint8_t l_2n_autoset = 0;
     uint8_t l_2n_mrw_mode = 0;
-    FAPI_TRY( mss::vpd_mr_mc_2n_mode_autoset(i_target, l_2n_autoset) );
+    FAPI_TRY( mss::vpd_mr_mc_2n_mode_autoset(l_mcs, l_2n_autoset) );
     FAPI_TRY( mss::mrw_dram_2n_mode(l_2n_mrw_mode) );
 
     // Geardown maps directly to autoset = 0 gets 1/2 rate, 1 get 1/4 rate.
     FAPI_TRY( eff_geardown_mode(l_mcs, l_attrs_geardown_mode.data()) );
 
     // If the MRW states 'auto' we use what's in VPD, otherwise we use what's in the MRW.
-    // (Errr ... does this make sense? The MRW is really just another form of VPD ...)
-    if (l_2n_mrw_mode != fapi2::ENUM_ATTR_MSS_MRW_DRAM_2N_MODE_AUTO)
-    {
-        // MRW values are 1 and 2 (to make room for 0 being the default.) So we subtract one.
-        l_2n_autoset = l_2n_mrw_mode - 1;
-    }
-
-    l_attrs_geardown_mode[l_port_num] = l_2n_autoset;
+    // We remove 1 from the value as that matches the expectations in the MR perfectly.
+    l_attrs_geardown_mode[l_port_num] = (l_2n_mrw_mode != fapi2::ENUM_ATTR_MSS_MRW_DRAM_2N_MODE_AUTO) ?
+                                        l_2n_mrw_mode - 1 : l_2n_autoset - 1;
 
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_GEARDOWN_MODE,
                             l_mcs,
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index f349d19b4..b3a7cdb02 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -35,9 +35,9 @@ namespace mss
 {
 ///
 /// @brief ATTR_MSS_VOLT_VDDR getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCBIST>
+/// @param[in] const ref to the TARGET_TYPE_MCBIST
 /// @param[out] uint32_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (MCBIST A)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt
 /// C code - in millivolts creator: mss_volt consumer: mss_eff_cnfg, others firmware
@@ -58,9 +58,9 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_VOLT_VPP getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCBIST>
+/// @param[in] const ref to the TARGET_TYPE_MCBIST
 /// @param[out] uint32_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (MCBIST A)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  DRAM VPP Voltage, each voltage rail would need to have a value. Computed in
 /// mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4 creator: mss_volt
@@ -81,9 +81,9 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_FREQ_OVERRIDE getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCBIST>
+/// @param[in] const ref to the TARGET_TYPE_MCBIST
 /// @param[out] uint64_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (MCBIST A)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  FOR LAB USE ONLY: Frequency override of this memory channel in MT/s comprising
 /// of up to three DIMMs. Set by config file or an attribute writing program.
@@ -106,9 +106,9 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_FREQ getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCBIST>
+/// @param[in] const ref to the TARGET_TYPE_MCBIST
 /// @param[out] uint64_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (MCBIST A)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Frequency of this memory channel in MT/s (Mega Transfers per second), comprising
 /// of three DIMMs. Computed in mss_freq creator: mss_freq consumer: mss_eff_cnfg,
@@ -129,9 +129,9 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_FREQ_BIAS_PERCENTAGE getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCBIST>
+/// @param[in] const ref to the TARGET_TYPE_MCBIST
 /// @param[out] uint32_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (MCBIST A)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Percentage to increase/decrease MEM frequency - two's complement number.
 /// Measured in 100's. So the value of 100 is one percent increase. This frequency
@@ -10591,9 +10591,9 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_NEST_CAPABLE_FREQUENCIES getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCBIST>
+/// @param[in] const ref to the TARGET_TYPE_MCBIST
 /// @param[out] uint64_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (MCBIST A)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  The NEST frequencies the memory chip can run at computed by the mss_freq. The
 /// possibilities are ORed together. The platform uses these value and the MRW to
@@ -10616,9 +10616,9 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_VOLT_OVERRIDE getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCBIST>
+/// @param[in] const ref to the TARGET_TYPE_MCBIST
 /// @param[out] uint8_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (MCBIST A)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Possible DRAM voltage override. Firmware notes: Default should be NONE
 /// (0x00).
@@ -19864,63 +19864,296 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_VPD_MR_0_VERSION_LAYOUT getter
+/// @param[in] const ref to the TARGET_TYPE_MCS
 /// @param[out] uint8_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  MR Keyword Layout Version Number. Increases when attributes are added, removed,
 /// or redefined. Does not
 /// reset.
 ///
-inline fapi2::ReturnCode vpd_mr_0_version_layout(uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mr_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        uint8_t& o_value)
 {
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_0_VERSION_LAYOUT, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_0_VERSION_LAYOUT, i_target, o_value) );
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_0_VERSION_LAYOUT: 0x%lx (system target)",
-             uint64_t(fapi2::current_err));
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_0_VERSION_LAYOUT: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
 /// @brief ATTR_MSS_VPD_MR_1_VERSION_DATA getter
+/// @param[in] const ref to the TARGET_TYPE_MCS
 /// @param[out] uint8_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  MR Keyword Data Version Number. Increases when data changes with the above
 /// layout version. Resets when layout version number
 /// increments.
 ///
-inline fapi2::ReturnCode vpd_mr_1_version_data(uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mr_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t& o_value)
 {
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_1_VERSION_DATA, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_1_VERSION_DATA, i_target, o_value) );
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_1_VERSION_DATA: 0x%lx (system target)",
-             uint64_t(fapi2::current_err));
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_1_VERSION_DATA: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
 /// @brief ATTR_MSS_VPD_MR_2_SIGNATURE_HASH getter
+/// @param[in] const ref to the TARGET_TYPE_MCS
 /// @param[out] uint32_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of
 /// data.
 ///
-inline fapi2::ReturnCode vpd_mr_2_signature_hash(uint32_t& o_value)
+inline fapi2::ReturnCode vpd_mr_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        uint32_t& o_value)
 {
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_2_SIGNATURE_HASH, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_2_SIGNATURE_HASH, i_target, o_value) );
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_2_SIGNATURE_HASH: 0x%lx (system target)",
-             uint64_t(fapi2::current_err));
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_2_SIGNATURE_HASH: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_DPHY_GPO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Global phy offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_GPO, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(i_target)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_GPO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_DPHY_GPO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D.1)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Global phy offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_GPO, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(l_mca)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_GPO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_DPHY_GPO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (E)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Global phy offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_GPO, i_target, l_value) );
+    memcpy(o_array, &l_value, 2);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_GPO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_DPHY_RLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Read latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_RLO, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(i_target)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_RLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_DPHY_RLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D.1)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Read latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_RLO, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(l_mca)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_RLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_DPHY_RLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (E)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Read latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_RLO, i_target, l_value) );
+    memcpy(o_array, &l_value, 2);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_RLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_DPHY_WLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Write latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(i_target)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_WLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_DPHY_WLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
+/// @param[out] ref to the value uint8_t
+/// @note Generated by gen_accessors.pl generateParameters (D.1)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Write latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
+{
+    uint8_t l_value[2];
+    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
+    o_value = l_value[mss::index(l_mca)];
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_WLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_DPHY_WLO getter
+/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[out] uint8_t* memory to store the value
+/// @note Generated by gen_accessors.pl generateParameters (E)
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
+/// @note  Write latency offset in number of
+/// clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
+{
+    if (o_array == nullptr)
+    {
+        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
+        return fapi2::FAPI2_RC_INVALID_PARAMETER;
+    }
+
+    uint8_t l_value[2];
+
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, i_target, l_value) );
+    memcpy(o_array, &l_value, 2);
+    return fapi2::current_err;
+
+fapi_try_exit:
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_WLO: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
@@ -23538,21 +23771,18 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
-/// @param[out] ref to the value uint8_t
-/// @note Generated by gen_accessors.pl generateParameters (D)
+/// @param[in] const ref to the TARGET_TYPE_MCS
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Default value for 2N Mode from Signal
-/// Integrity.
+/// @note  Default value for 2N Mode from Signal Integrity. 0x01 = 1N Mode , 0x02 = 2N
+/// Mode
 ///
-inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target,
+inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         uint8_t& o_value)
 {
-    uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, i_target.getParent<fapi2::TARGET_TYPE_MCS>(),
-                            l_value) );
-    o_value = l_value[mss::index(i_target)];
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, i_target, o_value) );
     return fapi2::current_err;
 
 fapi_try_exit:
@@ -23562,57 +23792,49 @@ fapi_try_exit:
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
-/// @param[out] ref to the value uint8_t
-/// @note Generated by gen_accessors.pl generateParameters (D.1)
+/// @brief ATTR_MSS_VPD_MR_TSYS_ADR getter
+/// @param[in] const ref to the TARGET_TYPE_MCS
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Default value for 2N Mode from Signal
-/// Integrity.
+/// @note  ADR WRClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of
+/// clock. Phase Rotator Static Offset value used to determine the Phase of the
+/// WrClk with respect to SysClk. For zero delay simulations, or simulations where
+/// the delay of the SysClk tree and the WrClk tree are equal, Set this field to
+/// 60h
 ///
-inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
-        uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mr_tsys_adr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t& o_value)
 {
-    uint8_t l_value[2];
-    auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(),
-                            l_value) );
-    o_value = l_value[mss::index(l_mca)];
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_TSYS_ADR, i_target, o_value) );
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_TSYS_ADR: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
-/// @brief ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET getter
-/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
-/// @param[out] uint8_t* memory to store the value
-/// @note Generated by gen_accessors.pl generateParameters (E)
+/// @brief ATTR_MSS_VPD_MR_TSYS_DATA getter
+/// @param[in] const ref to the TARGET_TYPE_MCS
+/// @param[out] uint8_t& reference to store the value
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Default value for 2N Mode from Signal
-/// Integrity.
+/// @note  DP16 WrClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of
+/// clock. Phase Rotator Static Offset value used to determine the Phase of the
+/// WrClk with respect to SysClk. For zero delay simulations, or simulations where
+/// the delay of the SysClk tree and the WrClk tree are equal, Set this field to
+/// 60h
 ///
-inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
-        uint8_t* o_array)
+inline fapi2::ReturnCode vpd_mr_tsys_data(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t& o_value)
 {
-    if (o_array == nullptr)
-    {
-        FAPI_ERR("nullptr passed to attribute accessor %s", __func__);
-        return fapi2::FAPI2_RC_INVALID_PARAMETER;
-    }
-
-    uint8_t l_value[2];
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, i_target, l_value) );
-    memcpy(o_array, &l_value, 2);
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_TSYS_DATA, i_target, o_value) );
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET: 0x%lx (target: %s)",
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_TSYS_DATA: 0x%lx (target: %s)",
              uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
@@ -23620,63 +23842,68 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_VPD_MT_0_VERSION_LAYOUT getter
+/// @param[in] const ref to the TARGET_TYPE_MCS
 /// @param[out] uint8_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  MT Keyword Layout Version Number. Increases when attributes are added, removed,
 /// or redefined. Does not
 /// reset.
 ///
-inline fapi2::ReturnCode vpd_mt_0_version_layout(uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mt_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        uint8_t& o_value)
 {
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_0_VERSION_LAYOUT, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_0_VERSION_LAYOUT, i_target, o_value) );
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_0_VERSION_LAYOUT: 0x%lx (system target)",
-             uint64_t(fapi2::current_err));
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_0_VERSION_LAYOUT: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
 /// @brief ATTR_MSS_VPD_MT_1_VERSION_DATA getter
+/// @param[in] const ref to the TARGET_TYPE_MCS
 /// @param[out] uint8_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  MT Keyword Data Version Number. Increases when data changes with the above
 /// layout version. Resets when layout version number
 /// increments.
 ///
-inline fapi2::ReturnCode vpd_mt_1_version_data(uint8_t& o_value)
+inline fapi2::ReturnCode vpd_mt_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t& o_value)
 {
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_1_VERSION_DATA, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_1_VERSION_DATA, i_target, o_value) );
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_1_VERSION_DATA: 0x%lx (system target)",
-             uint64_t(fapi2::current_err));
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_1_VERSION_DATA: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
 ///
 /// @brief ATTR_MSS_VPD_MT_2_SIGNATURE_HASH getter
+/// @param[in] const ref to the TARGET_TYPE_MCS
 /// @param[out] uint32_t& reference to store the value
-/// @note Generated by gen_accessors.pl generateParameters (SYSTEM)
+/// @note Generated by gen_accessors.pl generateParameters (NODIM A)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of
 /// data.
 ///
-inline fapi2::ReturnCode vpd_mt_2_signature_hash(uint32_t& o_value)
+inline fapi2::ReturnCode vpd_mt_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
+        uint32_t& o_value)
 {
 
-    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_2_SIGNATURE_HASH, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), o_value) );
+    FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_2_SIGNATURE_HASH, i_target, o_value) );
     return fapi2::current_err;
 
 fapi_try_exit:
-    FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_2_SIGNATURE_HASH: 0x%lx (system target)",
-             uint64_t(fapi2::current_err));
+    FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_2_SIGNATURE_HASH: 0x%lx (target: %s)",
+             uint64_t(fapi2::current_err), mss::c_str(i_target));
     return fapi2::current_err;
 }
 
@@ -25585,9 +25812,11 @@ fapi_try_exit:
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Number of clocks used for preamble. Calibration only uses 1 nCK preamble
-/// (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble
-/// option.
+/// @note  Number of clocks used for read/write preamble. Calibration only uses 1 nCK
+/// preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. "0" means
+/// 1 nCK preamble, "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for
+/// WRITE preamble. E.g. 0b
+/// 00010001
 ///
 inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint8_t& o_value)
 {
@@ -25609,9 +25838,11 @@ fapi_try_exit:
 /// @param[out] ref to the value uint8_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Number of clocks used for preamble. Calibration only uses 1 nCK preamble
-/// (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble
-/// option.
+/// @note  Number of clocks used for read/write preamble. Calibration only uses 1 nCK
+/// preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. "0" means
+/// 1 nCK preamble, "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for
+/// WRITE preamble. E.g. 0b
+/// 00010001
 ///
 inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value)
 {
@@ -25634,9 +25865,11 @@ fapi_try_exit:
 /// @param[out] uint8_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
-/// @note  Number of clocks used for preamble. Calibration only uses 1 nCK preamble
-/// (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble
-/// option.
+/// @note  Number of clocks used for read/write preamble. Calibration only uses 1 nCK
+/// preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. "0" means
+/// 1 nCK preamble, "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for
+/// WRITE preamble. E.g. 0b
+/// 00010001
 ///
 inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint8_t* o_array)
 {
@@ -25819,18 +26052,17 @@ fapi_try_exit:
 ///
 /// @brief ATTR_MSS_VPD_MT_WINDAGE_RD_CTR getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA>
-/// @param[out] ref to the value uint16_t
+/// @param[out] ref to the value int16_t
 /// @note Generated by gen_accessors.pl generateParameters (D)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Derived from calibration/characterization of read centering. Number of windage
-/// offset in units of pico-seconds[ps] with sign bit0 (0b0=positive, 0b1=negative)
-/// and value in bits1..31, so 0x8023 for example would mean "-35ps". If this is
-/// enabled, disable periodic rd_ctr in draminit_mc.
-/// Default
+/// offset in units of pico-seconds[ps]. If this is enabled, disable periodic rd_ctr
+/// in draminit_mc. Default is
+/// 0
 ///
-inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint16_t& o_value)
+inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, int16_t& o_value)
 {
-    uint16_t l_value[2];
+    int16_t l_value[2];
 
     FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_WINDAGE_RD_CTR, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
     o_value = l_value[mss::index(i_target)];
@@ -25845,19 +26077,17 @@ fapi_try_exit:
 ///
 /// @brief ATTR_MSS_VPD_MT_WINDAGE_RD_CTR getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_DIMM>
-/// @param[out] ref to the value uint16_t
+/// @param[out] ref to the value int16_t
 /// @note Generated by gen_accessors.pl generateParameters (D.1)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Derived from calibration/characterization of read centering. Number of windage
-/// offset in units of pico-seconds[ps] with sign bit0 (0b0=positive, 0b1=negative)
-/// and value in bits1..31, so 0x8023 for example would mean "-35ps". If this is
-/// enabled, disable periodic rd_ctr in draminit_mc.
-/// Default
+/// offset in units of pico-seconds[ps]. If this is enabled, disable periodic rd_ctr
+/// in draminit_mc. Default is
+/// 0
 ///
-inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
-        uint16_t& o_value)
+inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, int16_t& o_value)
 {
-    uint16_t l_value[2];
+    int16_t l_value[2];
     auto l_mca = i_target.getParent<fapi2::TARGET_TYPE_MCA>();
 
     FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_WINDAGE_RD_CTR, l_mca.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) );
@@ -25873,16 +26103,15 @@ fapi_try_exit:
 ///
 /// @brief ATTR_MSS_VPD_MT_WINDAGE_RD_CTR getter
 /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCS>
-/// @param[out] uint16_t* memory to store the value
+/// @param[out] int16_t* memory to store the value
 /// @note Generated by gen_accessors.pl generateParameters (E)
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK
 /// @note  Derived from calibration/characterization of read centering. Number of windage
-/// offset in units of pico-seconds[ps] with sign bit0 (0b0=positive, 0b1=negative)
-/// and value in bits1..31, so 0x8023 for example would mean "-35ps". If this is
-/// enabled, disable periodic rd_ctr in draminit_mc.
-/// Default
+/// offset in units of pico-seconds[ps]. If this is enabled, disable periodic rd_ctr
+/// in draminit_mc. Default is
+/// 0
 ///
-inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, uint16_t* o_array)
+inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, int16_t* o_array)
 {
     if (o_array == nullptr)
     {
@@ -25890,7 +26119,7 @@ inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET
         return fapi2::FAPI2_RC_INVALID_PARAMETER;
     }
 
-    uint16_t l_value[2];
+    int16_t l_value[2];
 
     FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_WINDAGE_RD_CTR, i_target, l_value) );
     memcpy(o_array, &l_value, 4);
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H
index 33afc8692..a59560f7f 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H
@@ -39,12 +39,12 @@ namespace decoder
 // VPD Keyword Version Byte: 00
 ///
 /// @brief ATTR_MSS_VPD_MT_0_VERSION_LAYOUT decode and set
-/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  MT Keyword Layout Version Number.  Increases when attributes are added, removed, or redefined.  Does not reset.
 ///
-inline fapi2::ReturnCode vpd_mt_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mt_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const std::vector<uint8_t*>& i_blobs)
 {
     uint8_t l_value;
@@ -59,12 +59,12 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_VPD_MT_1_VERSION_DATA decode and set
-/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  MT Keyword Data Version Number.  Increases when data changes with the above layout version.  Resets when layout version number increments.
 ///
-inline fapi2::ReturnCode vpd_mt_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mt_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const std::vector<uint8_t*>& i_blobs)
 {
     uint8_t l_value;
@@ -79,12 +79,12 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_VPD_MT_2_SIGNATURE_HASH decode and set
-/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of data.
 ///
-inline fapi2::ReturnCode vpd_mt_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mt_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const std::vector<uint8_t*>& i_blobs)
 {
     uint32_t l_value;
@@ -783,7 +783,8 @@ fapi_try_exit:
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Number of clocks used for preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option.
+/// @note  Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option.
+/// "0" means 1 nCK preamble, "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble. E.g. 0b 00010001
 ///
 inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const std::vector<uint8_t*>& i_blobs)
@@ -875,12 +876,12 @@ fapi_try_exit:
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blobs a std::vector of pointers to VPD blobs for this MCS's MCAs
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
-/// @note  Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps] with sign bit0 (0b0=positive, 0b1=negative) and value in bits1..31, so 0x8023 for example would mean "-35ps". If this is enabled, disable periodic rd_ctr in draminit_mc. Default
+/// @note  Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps]. If this is enabled, disable periodic rd_ctr in draminit_mc. Default is 0
 ///
 inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const std::vector<uint8_t*>& i_blobs)
 {
-    uint16_t l_value[2];
+    int16_t l_value[2];
     const auto& l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target);
     const uint64_t l_length = 4 / l_mcas.size();
 
@@ -908,12 +909,12 @@ fapi_try_exit:
 // VPD Keyword Version Byte: 00
 ///
 /// @brief ATTR_MSS_VPD_MR_0_VERSION_LAYOUT decode and set
-/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  MR Keyword Layout Version Number.  Increases when attributes are added, removed, or redefined.  Does not reset.
 ///
-inline fapi2::ReturnCode vpd_mr_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mr_0_version_layout(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value;
@@ -928,12 +929,12 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_VPD_MR_1_VERSION_DATA decode and set
-/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  MR Keyword Data Version Number.  Increases when data changes with the above layout version.  Resets when layout version number increments.
 ///
-inline fapi2::ReturnCode vpd_mr_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mr_1_version_data(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint8_t l_value;
@@ -948,12 +949,12 @@ fapi_try_exit:
 
 ///
 /// @brief ATTR_MSS_VPD_MR_2_SIGNATURE_HASH decode and set
-/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of data.
 ///
-inline fapi2::ReturnCode vpd_mr_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target,
+inline fapi2::ReturnCode vpd_mr_2_signature_hash(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
     uint32_t l_value;
@@ -968,6 +969,63 @@ fapi_try_exit:
 }
 
 ///
+/// @brief ATTR_MSS_VPD_MR_DPHY_GPO decode and set
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[in] i_blob the VPD blob for this MCS
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
+/// @note  Global phy offset in number of clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
+{
+    uint8_t l_value[2];
+
+    memcpy(&l_value, i_blob + 6, 2);
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_DPHY_GPO, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_DPHY_GPO start: 6, len: 2");
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_DPHY_RLO decode and set
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[in] i_blob the VPD blob for this MCS
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
+/// @note  Read latency offset in number of clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
+{
+    uint8_t l_value[2];
+
+    memcpy(&l_value, i_blob + 8, 2);
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_DPHY_RLO, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_DPHY_RLO start: 8, len: 2");
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_DPHY_WLO decode and set
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[in] i_blob the VPD blob for this MCS
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
+/// @note  Write latency offset in number of clocks
+///
+inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
+{
+    uint8_t l_value[2];
+
+    memcpy(&l_value, i_blob + 10, 2);
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_DPHY_WLO start: 10, len: 2");
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
 /// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 decode and set
 /// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
 /// @param[in] i_blob the VPD blob for this MCS
@@ -979,9 +1037,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 6, 2);
+    memcpy(&l_value, i_blob + 12, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 start: 6, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 start: 12, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -999,9 +1057,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 8, 2);
+    memcpy(&l_value, i_blob + 14, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01 start: 8, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01 start: 14, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1019,9 +1077,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 10, 2);
+    memcpy(&l_value, i_blob + 16, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02 start: 10, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02 start: 16, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1039,9 +1097,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 12, 2);
+    memcpy(&l_value, i_blob + 18, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03 start: 12, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03 start: 18, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1059,9 +1117,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 14, 2);
+    memcpy(&l_value, i_blob + 20, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04 start: 14, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04 start: 20, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1079,9 +1137,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 16, 2);
+    memcpy(&l_value, i_blob + 22, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05 start: 16, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05 start: 22, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1099,9 +1157,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 18, 2);
+    memcpy(&l_value, i_blob + 24, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06 start: 18, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06 start: 24, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1119,9 +1177,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 20, 2);
+    memcpy(&l_value, i_blob + 26, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07 start: 20, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07 start: 26, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1139,9 +1197,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 22, 2);
+    memcpy(&l_value, i_blob + 28, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08 start: 22, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08 start: 28, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1159,9 +1217,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 24, 2);
+    memcpy(&l_value, i_blob + 30, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09 start: 24, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09 start: 30, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1179,9 +1237,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 26, 2);
+    memcpy(&l_value, i_blob + 32, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10 start: 26, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10 start: 32, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1199,9 +1257,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 28, 2);
+    memcpy(&l_value, i_blob + 34, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11 start: 28, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11 start: 34, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1219,9 +1277,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 30, 2);
+    memcpy(&l_value, i_blob + 36, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12 start: 30, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12 start: 36, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1239,9 +1297,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 32, 2);
+    memcpy(&l_value, i_blob + 38, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13 start: 32, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13 start: 38, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1259,9 +1317,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 34, 2);
+    memcpy(&l_value, i_blob + 40, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17 start: 34, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17 start: 40, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1279,9 +1337,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 36, 2);
+    memcpy(&l_value, i_blob + 42, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0 start: 36, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0 start: 42, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1299,9 +1357,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 38, 2);
+    memcpy(&l_value, i_blob + 44, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1 start: 38, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1 start: 44, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1319,9 +1377,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 40, 2);
+    memcpy(&l_value, i_blob + 46, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0 start: 40, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0 start: 46, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1339,9 +1397,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 42, 2);
+    memcpy(&l_value, i_blob + 48, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1 start: 42, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1 start: 48, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1359,9 +1417,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target<fapi2::
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 44, 2);
+    memcpy(&l_value, i_blob + 50, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0 start: 44, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0 start: 50, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1379,9 +1437,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target<fapi2::
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 46, 2);
+    memcpy(&l_value, i_blob + 52, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1 start: 46, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1 start: 52, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1399,9 +1457,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target<fapi2::
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 48, 2);
+    memcpy(&l_value, i_blob + 54, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2 start: 48, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2 start: 54, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1419,9 +1477,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target<fapi2::
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 50, 2);
+    memcpy(&l_value, i_blob + 56, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP start: 50, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP start: 56, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1439,9 +1497,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target<fapi2::
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 52, 2);
+    memcpy(&l_value, i_blob + 58, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN start: 52, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN start: 58, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1459,9 +1517,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target<fapi2::
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 54, 2);
+    memcpy(&l_value, i_blob + 60, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP start: 54, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP start: 60, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1479,9 +1537,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target<fapi2::
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 56, 2);
+    memcpy(&l_value, i_blob + 62, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN start: 56, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN start: 62, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1499,9 +1557,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target<fapi2:
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 58, 2);
+    memcpy(&l_value, i_blob + 64, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN start: 58, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN start: 64, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1519,9 +1577,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Targ
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 60, 2);
+    memcpy(&l_value, i_blob + 66, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 start: 60, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 start: 66, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1539,9 +1597,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Targ
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 62, 2);
+    memcpy(&l_value, i_blob + 68, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 start: 62, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 start: 68, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1559,9 +1617,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Targe
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 64, 2);
+    memcpy(&l_value, i_blob + 70, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 start: 64, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 start: 70, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1579,9 +1637,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target<fapi2::
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 66, 2);
+    memcpy(&l_value, i_blob + 72, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR start: 66, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR start: 72, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1599,9 +1657,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 68, 2);
+    memcpy(&l_value, i_blob + 74, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 start: 68, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 start: 74, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1619,9 +1677,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 70, 2);
+    memcpy(&l_value, i_blob + 76, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 start: 70, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 start: 76, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1639,9 +1697,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 72, 2);
+    memcpy(&l_value, i_blob + 78, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0 start: 72, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0 start: 78, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1659,9 +1717,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 74, 2);
+    memcpy(&l_value, i_blob + 80, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1 start: 74, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1 start: 80, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1679,9 +1737,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 76, 2);
+    memcpy(&l_value, i_blob + 82, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 start: 76, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 start: 82, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1699,9 +1757,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 78, 2);
+    memcpy(&l_value, i_blob + 84, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 start: 78, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 start: 84, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1719,9 +1777,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 80, 2);
+    memcpy(&l_value, i_blob + 86, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 start: 80, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 start: 86, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1739,9 +1797,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 82, 2);
+    memcpy(&l_value, i_blob + 88, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 start: 82, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 start: 88, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1759,9 +1817,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 84, 2);
+    memcpy(&l_value, i_blob + 90, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 start: 84, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 start: 90, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1779,9 +1837,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 86, 2);
+    memcpy(&l_value, i_blob + 92, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 start: 86, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 start: 92, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1799,9 +1857,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 88, 2);
+    memcpy(&l_value, i_blob + 94, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 start: 88, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 start: 94, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1819,9 +1877,9 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target<fa
 {
     uint8_t l_value[2];
 
-    memcpy(&l_value, i_blob + 90, 2);
+    memcpy(&l_value, i_blob + 96, 2);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 start: 90, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 start: 96, len: 2");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1833,15 +1891,60 @@ fapi_try_exit:
 /// @param[in] i_blob the VPD blob for this MCS
 /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
 /// @note  Default value for 2N Mode from Signal Integrity.
+/// 0x01 = 1N Mode , 0x02 = 2N Mode
 ///
 inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
         const uint8_t* i_blob)
 {
-    uint8_t l_value[2];
+    uint8_t l_value;
 
-    memcpy(&l_value, i_blob + 92, 2);
+    memcpy(&l_value, i_blob + 98, 1);
     FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, i_target, l_value),
-              "Unable to decode and set ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET start: 92, len: 2");
+              "Unable to decode and set ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET start: 98, len: 1");
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_TSYS_ADR decode and set
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[in] i_blob the VPD blob for this MCS
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
+/// @note  ADR WRClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of clock.
+/// Phase Rotator Static Offset value used to determine the Phase of the WrClk with respect to SysClk.
+/// For zero delay simulations, or simulations where the delay of the SysClk tree and the WrClk tree are equal,
+/// Set this field to 60h
+///
+inline fapi2::ReturnCode vpd_mr_tsys_adr(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
+{
+    uint8_t l_value;
+
+    memcpy(&l_value, i_blob + 99, 1);
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_TSYS_ADR, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_TSYS_ADR start: 99, len: 1");
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+///
+/// @brief ATTR_MSS_VPD_MR_TSYS_DATA decode and set
+/// @param[in] i_target fapi2::Target<fapi2::TARGET_TYPE_MCS>
+/// @param[in] i_blob the VPD blob for this MCS
+/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK
+/// @note  DP16 WrClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of clock.
+/// Phase Rotator Static Offset value used to determine the Phase of the WrClk with respect to SysClk.
+/// For zero delay simulations, or simulations where the delay of the SysClk tree and the WrClk tree are equal,
+/// Set this field to 60h
+///
+inline fapi2::ReturnCode vpd_mr_tsys_data(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, const uint8_t* i_blob)
+{
+    uint8_t l_value;
+
+    memcpy(&l_value, i_blob + 100, 1);
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_VPD_MR_TSYS_DATA, i_target, l_value),
+              "Unable to decode and set ATTR_MSS_VPD_MR_TSYS_DATA start: 100, len: 1");
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -1860,9 +1963,9 @@ fapi_try_exit:
 inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target,
                                     const std::vector<uint8_t*>& i_mt_blob, const uint8_t* i_mr_blob)
 {
-    FAPI_TRY (decoder::vpd_mt_0_version_layout(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) );
-    FAPI_TRY (decoder::vpd_mt_1_version_data(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) );
-    FAPI_TRY (decoder::vpd_mt_2_signature_hash(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_0_version_layout(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_1_version_data(i_target, i_mt_blob) );
+    FAPI_TRY (decoder::vpd_mt_2_signature_hash(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_dimm_rcd_ibt_ca(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_dimm_rcd_ibt_cke(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_dimm_rcd_ibt_cs(i_target, i_mt_blob) );
@@ -1888,9 +1991,12 @@ inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>&
     FAPI_TRY (decoder::vpd_mt_vref_dram_wr(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_vref_mc_rd(i_target, i_mt_blob) );
     FAPI_TRY (decoder::vpd_mt_windage_rd_ctr(i_target, i_mt_blob) );
-    FAPI_TRY (decoder::vpd_mr_0_version_layout(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mr_blob) );
-    FAPI_TRY (decoder::vpd_mr_1_version_data(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mr_blob) );
-    FAPI_TRY (decoder::vpd_mr_2_signature_hash(fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_0_version_layout(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_1_version_data(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_2_signature_hash(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_dphy_gpo(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_dphy_rlo(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_dphy_wlo(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a00(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a01(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_addr_a02(i_target, i_mr_blob) );
@@ -1935,6 +2041,8 @@ inline fapi2::ReturnCode eff_decode(const fapi2::Target<fapi2::TARGET_TYPE_MCS>&
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_odt0(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_phase_rot_cntl_d1_odt1(i_target, i_mr_blob) );
     FAPI_TRY (decoder::vpd_mr_mc_2n_mode_autoset(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_tsys_adr(i_target, i_mr_blob) );
+    FAPI_TRY (decoder::vpd_mr_tsys_data(i_target, i_mr_blob) );
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
index bd607b2f0..a7192efda 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C
@@ -280,8 +280,8 @@ fapi2::ReturnCode rd_vref_bitfield_helper( const fapi2::Target<T>& i_target,
                      .set_TARGET(i_target),
                      "Target %s VPD_MT_VREF_MC_RD percentage out of bounds (%d - %d): %d",
                      c_str(i_target),
-                     TT::MAX_RD_VREF,
-                     TT::MIN_RD_VREF,
+                     l_max,
+                     l_min,
                      i_vref );
     }
     else
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
index d340b760a..d60d4dde8 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/fake_vpd.C
@@ -57,7 +57,7 @@ static constexpr uint8_t raw_mt[raw_mt_size] =
     0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x16, 0x00, 0x01,
-    0x31, 0xfd, 0x00, 0x01, 0x31, 0xfd, 0x80, 0x23, 0x80, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x31, 0xfd, 0x00, 0x01, 0x31, 0xfd, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 };
@@ -65,13 +65,13 @@ static constexpr uint8_t raw_mt[raw_mt_size] =
 constexpr auto raw_mr_size = 255;
 static constexpr uint8_t raw_mr[raw_mr_size] =
 {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x08, 0x03, 0x06, 0x03, 0x09, 0x04, 0x04, 0x00, 0x01,
-    0x01, 0x00, 0x04, 0x02, 0x03, 0x00, 0x06, 0x0a, 0x02, 0x01, 0x09, 0x09, 0x03, 0x01, 0x05, 0x07,
-    0x03, 0x05, 0x03, 0x03, 0x0a, 0x06, 0x08, 0x05, 0x09, 0x08, 0x09, 0x07, 0x0f, 0x0f, 0x0f, 0x0f,
-    0x0f, 0x0f, 0x67, 0x64, 0x66, 0x6b, 0x66, 0x66, 0x68, 0x6b, 0x0b, 0x03, 0x0b, 0x0a, 0x09, 0x0d,
-    0x0a, 0x0b, 0x09, 0x04, 0x15, 0x14, 0x00, 0x00, 0x25, 0x22, 0x00, 0x00, 0x1b, 0x14, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x00, 0x00, 0x14, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05, 0x02, 0x02, 0x01, 0x01, 0x03, 0x08, 0x03, 0x06,
+    0x03, 0x09, 0x04, 0x04, 0x00, 0x01, 0x01, 0x00, 0x04, 0x02, 0x03, 0x00, 0x06, 0x0a, 0x02, 0x01,
+    0x09, 0x09, 0x03, 0x01, 0x05, 0x07, 0x03, 0x05, 0x03, 0x03, 0x0a, 0x06, 0x08, 0x05, 0x09, 0x08,
+    0x09, 0x07, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x67, 0x64, 0x66, 0x6b, 0x66, 0x66, 0x68, 0x6b,
+    0x0b, 0x03, 0x0b, 0x0a, 0x09, 0x0d, 0x0a, 0x0b, 0x09, 0x04, 0x15, 0x14, 0x00, 0x00, 0x25, 0x22,
+    0x00, 0x00, 0x1b, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x00, 0x00, 0x14, 0x0e,
+    0x00, 0x00, 0x01, 0x21, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
index 119f39f8a..41d193069 100644
--- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
+++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C
@@ -198,12 +198,8 @@ fapi2::ReturnCode p9_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MCS>
         FAPI_TRY( l_eff_config.write_dbi(l_dimm) );
         FAPI_TRY( l_eff_config.additive_latency(l_dimm) );
         FAPI_TRY( l_eff_config.data_mask(l_dimm) );
-        // Hard-coded RIT protect attribute set (currently not taken account in eff_config)
-        {
-            uint16_t l_mss_vpd_mt_windage_rd_ctr[mss::PORTS_PER_MCS] = {0xDEAD, 0xBEEF};
-            FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_MSS_VPD_MT_WINDAGE_RD_CTR, i_target, l_mss_vpd_mt_windage_rd_ctr) );
-        }
 
+        // Hard-coded RIT protect attribute set (currently not taken account in eff_config)
         {
             uint8_t l_vpd_rlo[mss::PORTS_PER_MCS] = {0x01, 0x01};
             FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_VPD_RLO, i_target, l_vpd_rlo ) );
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
index 33cbaae1d..ff39283f8 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mr_attributes.xml
@@ -25,7 +25,7 @@
 <attributes>
     <attribute>
         <id>ATTR_MSS_VPD_MR_0_VERSION_LAYOUT</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
+        <targetType>TARGET_TYPE_MCS</targetType>
         <description>
             MR Keyword Layout Version Number.  Increases when attributes are added, removed, or redefined.  Does not reset.
         </description>
@@ -40,7 +40,7 @@
 
     <attribute>
         <id>ATTR_MSS_VPD_MR_1_VERSION_DATA</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
+        <targetType>TARGET_TYPE_MCS</targetType>
         <description>
             MR Keyword Data Version Number.  Increases when data changes with the above layout version.  Resets when layout version number increments.
         </description>
@@ -55,7 +55,7 @@
 
     <attribute>
         <id>ATTR_MSS_VPD_MR_2_SIGNATURE_HASH</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
+        <targetType>TARGET_TYPE_MCS</targetType>
         <description>
             Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of data.
         </description>
@@ -69,6 +69,54 @@
     </attribute>
 
     <attribute>
+        <id>ATTR_MSS_VPD_MR_DPHY_GPO</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            Global phy offset in number of clocks
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <mssUnits>nCK</mssUnits>
+        <mssBlobStart>6</mssBlobStart>
+        <mssBlobLength>2</mssBlobLength>
+        <mssAccessorName>vpd_mr_dphy_gpo</mssAccessorName>
+        <array>2</array>
+    </attribute>
+
+    <attribute>
+        <id>ATTR_MSS_VPD_MR_DPHY_RLO</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            Read latency offset in number of clocks
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <mssUnits>nCK</mssUnits>
+        <mssBlobStart>8</mssBlobStart>
+        <mssBlobLength>2</mssBlobLength>
+        <mssAccessorName>vpd_mr_dphy_rlo</mssAccessorName>
+        <array>2</array>
+    </attribute>
+
+    <attribute>
+        <id>ATTR_MSS_VPD_MR_DPHY_WLO</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            Write latency offset in number of clocks
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <mssUnits>nCK</mssUnits>
+        <mssBlobStart>10</mssBlobStart>
+        <mssBlobLength>2</mssBlobLength>
+        <mssAccessorName>vpd_mr_dphy_wlo</mssAccessorName>
+        <array>2</array>
+    </attribute>
+
+    <attribute>
         <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
@@ -78,7 +126,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>6</mssBlobStart>
+        <mssBlobStart>12</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a00</mssAccessorName>
         <array>2</array>
@@ -94,7 +142,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>8</mssBlobStart>
+        <mssBlobStart>14</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a01</mssAccessorName>
         <array>2</array>
@@ -110,7 +158,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>10</mssBlobStart>
+        <mssBlobStart>16</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a02</mssAccessorName>
         <array>2</array>
@@ -126,7 +174,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>12</mssBlobStart>
+        <mssBlobStart>18</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a03</mssAccessorName>
         <array>2</array>
@@ -142,7 +190,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>14</mssBlobStart>
+        <mssBlobStart>20</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a04</mssAccessorName>
         <array>2</array>
@@ -158,7 +206,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>16</mssBlobStart>
+        <mssBlobStart>22</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a05</mssAccessorName>
         <array>2</array>
@@ -174,7 +222,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>18</mssBlobStart>
+        <mssBlobStart>24</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a06</mssAccessorName>
         <array>2</array>
@@ -190,7 +238,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>20</mssBlobStart>
+        <mssBlobStart>26</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a07</mssAccessorName>
         <array>2</array>
@@ -206,7 +254,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>22</mssBlobStart>
+        <mssBlobStart>28</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a08</mssAccessorName>
         <array>2</array>
@@ -222,7 +270,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>24</mssBlobStart>
+        <mssBlobStart>30</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a09</mssAccessorName>
         <array>2</array>
@@ -238,7 +286,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>26</mssBlobStart>
+        <mssBlobStart>32</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a10</mssAccessorName>
         <array>2</array>
@@ -254,7 +302,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>28</mssBlobStart>
+        <mssBlobStart>34</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a11</mssAccessorName>
         <array>2</array>
@@ -270,7 +318,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>30</mssBlobStart>
+        <mssBlobStart>36</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a12</mssAccessorName>
         <array>2</array>
@@ -286,7 +334,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>32</mssBlobStart>
+        <mssBlobStart>38</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a13</mssAccessorName>
         <array>2</array>
@@ -302,7 +350,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>34</mssBlobStart>
+        <mssBlobStart>40</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_a17</mssAccessorName>
         <array>2</array>
@@ -318,7 +366,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>36</mssBlobStart>
+        <mssBlobStart>42</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_ba0</mssAccessorName>
         <array>2</array>
@@ -334,7 +382,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>38</mssBlobStart>
+        <mssBlobStart>44</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_ba1</mssAccessorName>
         <array>2</array>
@@ -350,7 +398,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>40</mssBlobStart>
+        <mssBlobStart>46</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_bg0</mssAccessorName>
         <array>2</array>
@@ -366,7 +414,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>42</mssBlobStart>
+        <mssBlobStart>48</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_bg1</mssAccessorName>
         <array>2</array>
@@ -382,7 +430,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>44</mssBlobStart>
+        <mssBlobStart>50</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_c0</mssAccessorName>
         <array>2</array>
@@ -398,7 +446,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>46</mssBlobStart>
+        <mssBlobStart>52</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_c1</mssAccessorName>
         <array>2</array>
@@ -414,7 +462,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>48</mssBlobStart>
+        <mssBlobStart>54</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_addr_c2</mssAccessorName>
         <array>2</array>
@@ -430,7 +478,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>50</mssBlobStart>
+        <mssBlobStart>56</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkp</mssAccessorName>
         <array>2</array>
@@ -446,7 +494,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>52</mssBlobStart>
+        <mssBlobStart>58</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_d0_clkn</mssAccessorName>
         <array>2</array>
@@ -462,7 +510,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>54</mssBlobStart>
+        <mssBlobStart>60</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkp</mssAccessorName>
         <array>2</array>
@@ -478,7 +526,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>56</mssBlobStart>
+        <mssBlobStart>62</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_d1_clkn</mssAccessorName>
         <array>2</array>
@@ -494,7 +542,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>58</mssBlobStart>
+        <mssBlobStart>64</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cmd_actn</mssAccessorName>
         <array>2</array>
@@ -510,7 +558,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>60</mssBlobStart>
+        <mssBlobStart>66</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_casn_a15</mssAccessorName>
         <array>2</array>
@@ -526,7 +574,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>62</mssBlobStart>
+        <mssBlobStart>68</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_rasn_a16</mssAccessorName>
         <array>2</array>
@@ -542,7 +590,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>64</mssBlobStart>
+        <mssBlobStart>70</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cmd_addr_wen_a14</mssAccessorName>
         <array>2</array>
@@ -558,7 +606,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>66</mssBlobStart>
+        <mssBlobStart>72</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cmd_par</mssAccessorName>
         <array>2</array>
@@ -574,7 +622,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>68</mssBlobStart>
+        <mssBlobStart>74</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke0</mssAccessorName>
         <array>2</array>
@@ -590,7 +638,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>70</mssBlobStart>
+        <mssBlobStart>76</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_cke1</mssAccessorName>
         <array>2</array>
@@ -606,7 +654,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>72</mssBlobStart>
+        <mssBlobStart>78</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_cke0</mssAccessorName>
         <array>2</array>
@@ -622,7 +670,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>74</mssBlobStart>
+        <mssBlobStart>80</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_cke1</mssAccessorName>
         <array>2</array>
@@ -638,7 +686,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>76</mssBlobStart>
+        <mssBlobStart>82</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn0</mssAccessorName>
         <array>2</array>
@@ -654,7 +702,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>78</mssBlobStart>
+        <mssBlobStart>84</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_csn1</mssAccessorName>
         <array>2</array>
@@ -670,7 +718,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>80</mssBlobStart>
+        <mssBlobStart>86</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn0</mssAccessorName>
         <array>2</array>
@@ -686,7 +734,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>82</mssBlobStart>
+        <mssBlobStart>88</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_csn1</mssAccessorName>
         <array>2</array>
@@ -702,7 +750,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>84</mssBlobStart>
+        <mssBlobStart>90</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt0</mssAccessorName>
         <array>2</array>
@@ -718,7 +766,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>86</mssBlobStart>
+        <mssBlobStart>92</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d0_odt1</mssAccessorName>
         <array>2</array>
@@ -734,7 +782,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>88</mssBlobStart>
+        <mssBlobStart>94</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt0</mssAccessorName>
         <array>2</array>
@@ -750,7 +798,7 @@
         <valueType>uint8</valueType>
         <writeable/>
         <mssUnits>tick</mssUnits>
-        <mssBlobStart>90</mssBlobStart>
+        <mssBlobStart>96</mssBlobStart>
         <mssBlobLength>2</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_phase_rot_cntl_d1_odt1</mssAccessorName>
         <array>2</array>
@@ -761,15 +809,51 @@
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
             Default value for 2N Mode from Signal Integrity.
+            0x01 = 1N Mode , 0x02 = 2N Mode
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
         <writeable/>
-        <mssUnits>num</mssUnits>
-        <mssBlobStart>92</mssBlobStart>
-        <mssBlobLength>2</mssBlobLength>
+        <mssUnits></mssUnits>
+        <mssBlobStart>98</mssBlobStart>
+        <mssBlobLength>1</mssBlobLength>
         <mssAccessorName>vpd_mr_mc_2n_mode_autoset</mssAccessorName>
-        <array>2</array>
+    </attribute>
+
+    <attribute>
+        <id>ATTR_MSS_VPD_MR_TSYS_ADR</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            ADR WRClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase Rotator Static Offset value used to determine the Phase of the WrClk with respect to SysClk.
+            For zero delay simulations, or simulations where the delay of the SysClk tree and the WrClk tree are equal,
+            Set this field to 60h
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <mssUnits>tick</mssUnits>
+        <mssBlobStart>99</mssBlobStart>
+        <mssBlobLength>1</mssBlobLength>
+        <mssAccessorName>vpd_mr_tsys_adr</mssAccessorName>
+    </attribute>
+
+    <attribute>
+        <id>ATTR_MSS_VPD_MR_TSYS_DATA</id>
+        <targetType>TARGET_TYPE_MCS</targetType>
+        <description>
+            DP16 WrClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of clock.
+            Phase Rotator Static Offset value used to determine the Phase of the WrClk with respect to SysClk.
+            For zero delay simulations, or simulations where the delay of the SysClk tree and the WrClk tree are equal,
+            Set this field to 60h
+        </description>
+        <initToZero></initToZero>
+        <valueType>uint8</valueType>
+        <writeable/>
+        <mssUnits>tick</mssUnits>
+        <mssBlobStart>100</mssBlobStart>
+        <mssBlobLength>1</mssBlobLength>
+        <mssAccessorName>vpd_mr_tsys_data</mssAccessorName>
     </attribute>
 
 </attributes>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml
index 504232604..1448180d5 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mt_attributes.xml
@@ -25,7 +25,7 @@
 <attributes>
     <attribute>
         <id>ATTR_MSS_VPD_MT_0_VERSION_LAYOUT</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
+        <targetType>TARGET_TYPE_MCS</targetType>
         <description>
             MT Keyword Layout Version Number.  Increases when attributes are added, removed, or redefined.  Does not reset.
         </description>
@@ -40,7 +40,7 @@
 
     <attribute>
         <id>ATTR_MSS_VPD_MT_1_VERSION_DATA</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
+        <targetType>TARGET_TYPE_MCS</targetType>
         <description>
             MT Keyword Data Version Number.  Increases when data changes with the above layout version.  Resets when layout version number increments.
         </description>
@@ -55,7 +55,7 @@
 
     <attribute>
         <id>ATTR_MSS_VPD_MT_2_SIGNATURE_HASH</id>
-        <targetType>TARGET_TYPE_SYSTEM</targetType>
+        <targetType>TARGET_TYPE_MCS</targetType>
         <description>
             Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of data.
         </description>
@@ -468,7 +468,8 @@
         <id>ATTR_MSS_VPD_MT_PREAMBLE</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Number of clocks used for preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option.
+            Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option.
+            "0" means 1 nCK preamble, "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble. E.g. 0b 00010001
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
@@ -517,12 +518,12 @@
         <id>ATTR_MSS_VPD_MT_WINDAGE_RD_CTR</id>
         <targetType>TARGET_TYPE_MCS</targetType>
         <description>
-            Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps] with sign bit0 (0b0=positive, 0b1=negative) and value in bits1..31, so 0x8023 for example would mean "-35ps". If this is enabled, disable periodic rd_ctr in draminit_mc. Default
+            Derived from calibration/characterization of read centering. Number of windage offset in units of pico-seconds[ps]. If this is enabled, disable periodic rd_ctr in draminit_mc. Default is 0
         </description>
         <initToZero></initToZero>
-        <valueType>uint16</valueType>
+        <valueType>int16</valueType>
         <writeable/>
-        <mssUnits>num</mssUnits>
+        <mssUnits>signed</mssUnits>
         <mssBlobStart>214</mssBlobStart>
         <mssBlobLength>4</mssBlobLength>
         <mssAccessorName>vpd_mt_windage_rd_ctr</mssAccessorName>
diff --git a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
index 3bc0cce27..a4562b18b 100644
--- a/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
+++ b/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml
@@ -423,8 +423,19 @@
     <attribute>
       <id>ATTR_MSS_PORT_MAXPOWER</id>
     </attribute>
-    
-    <!-- =====================================================================
+    <attribute>
+      <id>ATTR_MSS_VPD_MR_DPHY_RLO</id>
+    </attribute>
+    <attribute>
+      <id>ATTR_MSS_VPD_MR_DPHY_WLO</id>
+    </attribute>
+    <attribute>
+      <id>ATTR_MSS_VPD_MR_TSYS_ADR</id>
+    </attribute>
+    <attribute>
+      <id>ATTR_MSS_VPD_MR_TSYS_DATA</id>
+    </attribute>
+<!-- =====================================================================
      End of temporary definitions
      ================================================================= -->
 
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 393ac8313..7a23a05a1 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -25508,22 +25508,6 @@ DEPRECATED!!!!
 </attribute>
 
 <attribute>
-    <id>MSS_VPD_MR_2_SIGNATURE_FREQ_DROP</id>
-    <description>MR Keyword type, nibble 0 = freq bin (0 = 1600, 1 = 1866, 2 = 2133, 3 = 2400, 4 = 2667, 5 = 2933, 6 = 3200), nibble 1 = num dimms per port (1 = single drop, 2 = dual drop)</description>
-    <simpleType>
-      <uint8_t>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_MSS_VPD_MR_2_SIGNATURE_FREQ_DROP</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
     <id>MSS_VPD_MR_2_SIGNATURE_HASH</id>
     <description>Hash Signature for the MR Keyword. The hash signature is 32bits for 256 bytes of data.</description>
     <simpleType>
@@ -27070,7 +27054,6 @@ DEPRECATED!!!!
     <description>Default value for 2N Mode from Signal Integrity.</description>
     <simpleType>
       <uint8_t></uint8_t>
-      <array>2</array>
     </simpleType>
     <persistency>volatile-zeroed</persistency>
     <writeable/>
@@ -27118,10 +27101,14 @@ DEPRECATED!!!!
 
 <attribute>
     <id>MSS_VPD_MR_TSYS_ADR</id>
-    <description>Place holder description</description>
+    <description>
+    ADR WRClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of clock.
+    Phase Rotator Static Offset value used to determine the Phase of the WrClk with respect to SysClk.
+    For zero delay simulations, or simulations where the delay of the SysClk tree and the WrClk tree are equal,
+    Set this field to 60h
+    </description>
     <simpleType>
       <uint8_t></uint8_t>
-      <array>2</array>
     </simpleType>
     <persistency>volatile-zeroed</persistency>
     <writeable/>
@@ -27133,28 +27120,15 @@ DEPRECATED!!!!
 </attribute>
 
 <attribute>
-    <id>VPD_MR_TSYS_ADR</id>
-    <description>Place holder description</description>
-    <simpleType>
-      <uint8_t></uint8_t>
-      <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_VPD_MR_TSYS_ADR</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-
-<attribute>
     <id>MSS_VPD_MR_TSYS_DATA</id>
-    <description>Place holder description</description>
+    <description>
+    DP16 WrClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of clock.
+    Phase Rotator Static Offset value used to determine the Phase of the WrClk with respect to SysClk.
+    For zero delay simulations, or simulations where the delay of the SysClk tree and the WrClk tree are equal,
+    Set this field to 60h
+    </description>
     <simpleType>
       <uint8_t></uint8_t>
-      <array>2</array>
     </simpleType>
     <persistency>volatile-zeroed</persistency>
     <writeable/>
@@ -27165,22 +27139,6 @@ DEPRECATED!!!!
     </hwpfToHbAttrMap>
 </attribute>
 
-<attribute>
-    <id>VPD_MR_TSYS_DATA</id>
-    <description>Place holder description</description>
-    <simpleType>
-      <uint8_t></uint8_t>
-      <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_VPD_MR_TSYS_DATA</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
 
 <attribute>
     <id>MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP</id>
@@ -27359,24 +27317,6 @@ DEPRECATED!!!!
     </hwpfToHbAttrMap>
 </attribute>
 
-
-
-<attribute>
-    <id>MSS_VPD_MT_2_SIGNATURE_DIMM0RANK_DIMM1RANK</id>
-    <description>Place holder description</description>
-    <simpleType>
-      <uint8_t>
-      </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <writeable/>
-    <readable/>
-    <hwpfToHbAttrMap>
-      <id>ATTR_MSS_VPD_MT_2_SIGNATURE_DIMM0RANK_DIMM1RANK</id>
-      <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
 <attribute>
     <id>MSS_VPD_MT_CKE_PRI_MAP</id>
     <description>Place holder description</description>
@@ -27867,7 +27807,7 @@ DEPRECATED!!!!
     <id>MSS_VPD_MT_WINDAGE_RD_CTR</id>
     <description>Place holder description</description>
     <simpleType>
-      <uint16_t></uint16_t>
+      <int16_t></int16_t>
       <array>2</array>
     </simpleType>
     <persistency>volatile-zeroed</persistency>
@@ -30436,4 +30376,61 @@ DEPRECATED!!!!
   </hwpfToHbAttrMap>
 </attribute>
 
+<attribute>
+  <id>MSS_VPD_MR_DPHY_GPO</id>
+  <description>
+        Global phy offset in number of clocks
+  </description>
+  <simpleType>
+    <uint8_t>
+    </uint8_t>
+    <array>2</array>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <writeable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_MSS_VPD_MR_DPHY_GPO</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>MSS_VPD_MR_DPHY_RLO</id>
+  <description>
+        Read latency offset in number of clocks
+  </description>
+  <simpleType>
+    <uint8_t>
+    </uint8_t>
+    <array>2</array>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <writeable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_MSS_VPD_MR_DPHY_RLO</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>MSS_VPD_MR_DPHY_WLO</id>
+  <description>
+        Write latency offset in number of clocks
+  </description>
+  <simpleType>
+    <uint8_t>
+    </uint8_t>
+    <array>2</array>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <writeable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_MSS_VPD_MR_DPHY_WLO</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 6e1d1224c..4dfd20009 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -759,14 +759,6 @@
     <attribute><id>MSS_MRW_FINE_REFRESH_MODE</id></attribute>
     <attribute><id>MSS_MRW_TEMP_REFRESH_RANGE</id></attribute>
     <attribute><id>MSS_MRW_RESET_DELAY_BEFORE_CAL</id></attribute>
-    <attribute><id>MSS_VPD_MR_0_VERSION_LAYOUT</id></attribute>
-    <attribute><id>MSS_VPD_MR_1_VERSION_DATA</id></attribute>
-    <attribute><id>MSS_VPD_MR_2_SIGNATURE_FREQ_DROP</id></attribute>
-    <attribute><id>MSS_VPD_MR_2_SIGNATURE_HASH</id></attribute>
-    <attribute><id>MSS_VPD_MT_0_VERSION_LAYOUT</id></attribute>
-    <attribute><id>MSS_VPD_MT_1_VERSION_DATA</id></attribute>
-    <attribute><id>MSS_VPD_MT_2_SIGNATURE_DIMM0RANK_DIMM1RANK</id></attribute>
-    <attribute><id>MSS_VPD_MT_2_SIGNATURE_HASH</id></attribute>
     <attribute><id>MSS_MRW_DRAM_2N_MODE</id></attribute>
     <attribute><id>MRW_HW_MIRRORING_ENABLE</id></attribute>
 
@@ -1586,8 +1578,6 @@
     <attribute><id>MSS_VPD_MR_TSYS_ADR</id></attribute>
     <attribute><id>MSS_VPD_MR_TSYS_DATA</id></attribute>
     <attribute><id>VPD_MR_PERIODIC_MEMCAL_MODE_OPTIONS</id></attribute>
-    <attribute><id>VPD_MR_TSYS_ADR</id></attribute>
-    <attribute><id>VPD_MR_TSYS_DATA</id></attribute>
     <attribute><id>MSS_VPD_MT_CKE_PRI_MAP</id></attribute>
     <attribute><id>MSS_VPD_MT_CKE_PWR_MAP</id></attribute>
     <attribute><id>MSS_VPD_MT_DIMM_RCD_IBT_CA</id></attribute>
@@ -1684,6 +1674,15 @@
     <attribute><id>VPD_OVERRIDE_MT_ENABLE</id></attribute>
     <attribute><id>VPD_OVERRIDE_MR</id></attribute>
     <attribute><id>VPD_OVERRIDE_MR_ENABLE</id></attribute>
+    <attribute><id>MSS_VPD_MT_0_VERSION_LAYOUT</id></attribute>
+    <attribute><id>MSS_VPD_MT_1_VERSION_DATA</id></attribute>
+    <attribute><id>MSS_VPD_MT_2_SIGNATURE_HASH</id></attribute>
+    <attribute><id>MSS_VPD_MR_0_VERSION_LAYOUT</id></attribute>
+    <attribute><id>MSS_VPD_MR_1_VERSION_DATA</id></attribute>
+    <attribute><id>MSS_VPD_MR_2_SIGNATURE_HASH</id></attribute>
+    <attribute><id>MSS_VPD_MR_DPHY_GPO</id></attribute>
+    <attribute><id>MSS_VPD_MR_DPHY_RLO</id></attribute>
+    <attribute><id>MSS_VPD_MR_DPHY_WLO</id></attribute>
 </targetType>
 
 <targetType>
@@ -1844,9 +1843,6 @@
         <default>0xE0</default>
     </attribute>
     <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute>
-    <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id>
-        <default>0x00000001</default> <!-- GARD -->
-    </attribute>
     <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute>
     <attribute><id>PARENT_PERVASIVE</id></attribute>