HWP: integrate proc_pcie_scominit

Change-Id: Iefd3083c16ab7d8347bc7c395d106ad4ec4ef2be
RTC: 42175
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2278
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

13 files changed, 2254 insertions, 78 deletions

diff --git a/src/include/usr/hwpf/istepreasoncodes.H b/src/include/usr/hwpf/istepreasoncodes.H
index b7be2abff..cf4f8a4d5 100644
--- a/src/include/usr/hwpf/istepreasoncodes.H
+++ b/src/include/usr/hwpf/istepreasoncodes.H
@@ -99,6 +99,7 @@ enum istepModuleId
     ISTEP_HOST_VERIFY_HDAT                              = 0x32,
     ISTEP_HOST_START_PAYLOAD                            = 0x33,
     ISTEP_PROC_CHECK_SLAVE_SBE_SEEPROM_COMPLETE         = 0x34,
+    ISTEP_PROC_PCIE_SCOMINIT                            = 0x35,
 };
 
 /**
diff --git a/src/makefile b/src/makefile
index 622ef02f4..2d8b48e81 100644
--- a/src/makefile
+++ b/src/makefile
@@ -83,8 +83,9 @@ include ${ROOTPATH}/src/usr/diag/prdf/common/prd_ruletable.mk
 # image later.
 hbicore_DATA_MODULES =  sample.if p8.dmi.scom.if cen.dmi.scom.if \
                         p8.fbc.scom.if mbs_def.if mba_def.if cen_ddrphy.if \
+                        p8.pe.phase1.scom.if \
                         dimmspd.dat centaur.sbe_pnor.bin procmvpd.dat \
-						procpore.dat ${PRDR_RULE_TABLE_TARGETS}
+                        procpore.dat ${PRDR_RULE_TABLE_TARGETS}
 
 hbicore_LIDNUMBER = 80f00100
 
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index 9b5769265..9b5769265 100755..100644
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
diff --git a/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile
new file mode 100644
index 000000000..892b3c1f6
--- /dev/null
+++ b/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile
@@ -0,0 +1,1285 @@
+#-- $Id: p8.pe.phase1.scom.initfile,v 1.1 2012/11/05 21:39:30 jmcgill Exp $
+#-------------------------------------------------------------------------------
+#--
+#-- (C) Copyright International Business Machines Corp. 2011
+#-- All Rights Reserved -- Property of IBM
+#-- *** IBM Confidential ***
+#--
+#-- TITLE       : p8.pcie.phase1.scom.initfile
+#-- DESCRIPTION : Perform PCIe Physical IO Inits (Phase 1, Steps 5-6)
+#--
+#-- OWNER NAME  : Joe McDonald            Email: joemc@us.ibm.com
+#-- OWNER NAME  : Rick Mata               Email: ricmata@us.ibm.com
+#--
+#--------------------------------------------------------------------------------
+
+SyntaxVersion = 1
+
+#--------------------------------------------------------------------------------
+#-- Includes
+#--------------------------------------------------------------------------------
+
+#--------------------------------------------------------------------------------
+#-- Defines
+#--------------------------------------------------------------------------------
+
+#--------------------------------------------------------------------------------
+#-- SCOM initializations
+#--------------------------------------------------------------------------------
+
+#--
+#-- IOP 0
+#--
+
+#-- G3 PLL Control Register 0
+scom 0x800008010901143F {
+    bits,  scom_data;
+    51:63, ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[0];
+}
+
+#-- G2 PLL Control Register 0
+scom 0x800008050901143F {
+    bits,     scom_data;
+    51:63,    ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0[0];
+}
+
+#-- PLL Global Control Register 0
+scom 0x800008080901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0[0];
+}
+
+#-- PLL Global Control Register 1
+scom 0x800008090901143F {
+    bits,     scom_data;
+    51:63,    ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1[0];
+}
+
+#-- PCS Control Register 0
+scom 0x800008800901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_PCS_CONTROL0[0];
+}
+
+#-- PCS Control Register 1
+scom 0x800008810901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_PCS_CONTROL1[0];
+}
+
+#-- TX FIFO Offset Register (A0)
+scom 0x800004010901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][0];
+}
+
+#-- TX FIFO Offset Register (A1)
+scom 0x800004410901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][1];
+}
+
+#-- TX FIFO Offset Register (A2)
+scom 0x800004810901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][2];
+}
+
+#-- TX FIFO Offset Register (A3)
+scom 0x800004C10901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][3];
+}
+
+#-- TX FIFO Offset Register (A4)
+scom 0x800005010901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][4];
+}
+
+#-- TX FIFO Offset Register (A5)
+scom 0x800005410901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][5];
+}
+
+#-- TX FIFO Offset Register (A6)
+scom 0x800005810901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][6];
+}
+
+#-- TX FIFO Offset Register (A7)
+scom 0x800005C10901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][7];
+}
+
+#-- TX FIFO Offset Register (B0)
+scom 0x800006010901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][8];
+}
+
+#-- TX FIFO Offset Register (B1)
+scom 0x800006410901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][9];
+}
+
+#-- TX FIFO Offset Register (B2)
+scom 0x800006810901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][10];
+}
+
+#-- TX FIFO Offset Register (B3)
+scom 0x800006C10901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][11];
+}
+
+#-- TX FIFO Offset Register (B4)
+scom 0x800007010901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][12];
+}
+
+#-- TX FIFO Offset Register (B5)
+scom 0x800007410901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][13];
+}
+
+#-- TX FIFO Offset Register (B6)
+scom 0x800007810901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][14];
+}
+
+#-- TX FIFO Offset Register (B7)
+scom 0x800007C10901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][15];
+}
+
+#-- TX Receiver Detect Control Register (A0)
+scom 0x800004020901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][0];
+}
+
+#-- TX Receiver Detect Control Register (A1)
+scom 0x800004420901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][1];
+}
+
+#-- TX Receiver Detect Control Register (A2)
+scom 0x800004820901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][2];
+}
+
+#-- TX Receiver Detect Control Register (A3)
+scom 0x800004C20901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][3];
+}
+
+#-- TX Receiver Detect Control Register (A4)
+scom 0x800005020901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][4];
+}
+
+#-- TX Receiver Detect Control Register (A5)
+scom 0x800005420901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][5];
+}
+
+#-- TX Receiver Detect Control Register (A6)
+scom 0x800005820901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][6];
+}
+
+#-- TX Receiver Detect Control Register (A7)
+scom 0x800005C20901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][7];
+}
+
+#-- TX Receiver Detect Control Register (B0)
+scom 0x800006020901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][8];
+}
+
+#-- TX Receiver Detect Control Register (B1)
+scom 0x800006420901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][9];
+}
+
+#-- TX Receiver Detect Control Register (B2)
+scom 0x800006820901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][10];
+}
+
+#-- TX Receiver Detect Control Register (B3)
+scom 0x800006C20901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][11];
+}
+
+#-- TX Receiver Detect Control Register (B4)
+scom 0x800007020901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][12];
+}
+
+#-- TX Receiver Detect Control Register (B5)
+scom 0x800007420901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][13];
+}
+
+#-- TX Receiver Detect Control Register (B6)
+scom 0x800007820901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][14];
+}
+
+#-- TX Receiver Detect Control Register (B7)
+scom 0x800007C20901143F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][15];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A0)
+scom 0x8000041B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][0];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A1)
+scom 0x8000045B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][1];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A2)
+scom 0x8000049B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][2];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A3)
+scom 0x800004DB0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][3];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A4)
+scom 0x8000051B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][4];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A5)
+scom 0x8000055B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][5];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A6)
+scom 0x8000059B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][6];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A7)
+scom 0x800005DB0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][7];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B0)
+scom 0x8000061B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][8];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B1)
+scom 0x8000065B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][9];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B2)
+scom 0x8000069B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][10];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B3)
+scom 0x800006DB0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][11];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B4)
+scom 0x8000071B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][12];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B5)
+scom 0x8000075B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][13];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B6)
+scom 0x8000079B0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][14];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B7)
+scom 0x800007DB0901143F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][15];
+}
+
+#-- RX VGA Control Register2 (A0)
+scom 0x8000000C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][0];
+}
+
+#-- RX VGA Control Register2 (A1)
+scom 0x8000004C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][1];
+}
+
+#-- RX VGA Control Register2 (A2)
+scom 0x8000008C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][2];
+}
+
+#-- RX VGA Control Register2 (A3)
+scom 0x800000CC0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][3];
+}
+
+#-- RX VGA Control Register2 (A4)
+scom 0x8000010C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][4];
+}
+
+#-- RX VGA Control Register2 (A5)
+scom 0x8000014C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][5];
+}
+
+#-- RX VGA Control Register2 (A6)
+scom 0x8000018C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][6];
+}
+
+#-- RX VGA Control Register2 (A7)
+scom 0x800001CC0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][7];
+}
+
+#-- RX VGA Control Register2 (B0)
+scom 0x8000020C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][8];
+}
+
+#-- RX VGA Control Register2 (B1)
+scom 0x8000024C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][9];
+}
+
+#-- RX VGA Control Register2 (B2)
+scom 0x8000028C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][10];
+}
+
+#-- RX VGA Control Register2 (B3)
+scom 0x800002CC0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][11];
+}
+
+#-- RX VGA Control Register2 (B4)
+scom 0x8000030C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][12];
+}
+
+#-- RX VGA Control Register2 (B5)
+scom 0x8000034C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][13];
+}
+
+#-- RX VGA Control Register2 (B6)
+scom 0x8000038C0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][14];
+}
+
+#-- RX VGA Control Register2 (B7)
+scom 0x800003CC0901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][15];
+}
+
+#-- RX Receiver Peaking Register (A0)
+scom 0x800000100901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][0];
+}
+
+#-- RX Receiver Peaking Register (A1)
+scom 0x800000500901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][1];
+}
+
+#-- RX Receiver Peaking Register (A2)
+scom 0x800000900901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][2];
+}
+
+#-- RX Receiver Peaking Register (A3)
+scom 0x800000D00901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][3];
+}
+
+#-- RX Receiver Peaking Register (A4)
+scom 0x800001100901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][4];
+}
+
+#-- RX Receiver Peaking Register (A5)
+scom 0x800001500901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][5];
+}
+
+#-- RX Receiver Peaking Register (A6)
+scom 0x800001900901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][6];
+}
+
+#-- RX Receiver Peaking Register (A7)
+scom 0x800001D00901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][7];
+}
+
+#-- RX Receiver Peaking Register (B0)
+scom 0x800002100901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][8];
+}
+
+#-- RX Receiver Peaking Register (B1)
+scom 0x800002500901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][9];
+}
+
+#-- RX Receiver Peaking Register (B2)
+scom 0x800002900901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][10];
+}
+
+#-- RX Receiver Peaking Register (B3)
+scom 0x800002D00901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][11];
+}
+
+#-- RX Receiver Peaking Register (B4)
+scom 0x800003100901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][12];
+}
+
+#-- RX Receiver Peaking Register (B5)
+scom 0x800003500901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][13];
+}
+
+#-- RX Receiver Peaking Register (B6)
+scom 0x800003900901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][14];
+}
+
+#-- RX Receiver Peaking Register (B7)
+scom 0x800003D00901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[0][15];
+}
+
+#-- RX Signal Detect Level Register (A0)
+scom 0x800000370901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][0];
+}
+
+#-- RX Signal Detect Level Register (A1)
+scom 0x800000770901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][1];
+}
+
+#-- RX Signal Detect Level Register (A2)
+scom 0x800000B70901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][2];
+}
+
+#-- RX Signal Detect Level Register (A3)
+scom 0x800000F70901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][3];
+}
+
+#-- RX Signal Detect Level Register (A4)
+scom 0x800001370901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][4];
+}
+
+#-- RX Signal Detect Level Register (A5)
+scom 0x800001770901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][5];
+}
+
+#-- RX Signal Detect Level Register (A6)
+scom 0x800001B70901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][6];
+}
+
+#-- RX Signal Detect Level Register (A7)
+scom 0x800001F70901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][7];
+}
+
+#-- RX Signal Detect Level Register (B0)
+scom 0x800002370901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][8];
+}
+
+#-- RX Signal Detect Level Register (B1)
+scom 0x800002770901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][9];
+}
+
+#-- RX Signal Detect Level Register (B2)
+scom 0x800002B70901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][10];
+}
+
+#-- RX Signal Detect Level Register (B3)
+scom 0x800002F70901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][11];
+}
+
+#-- RX Signal Detect Level Register (B4)
+scom 0x800003370901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][12];
+}
+
+#-- RX Signal Detect Level Register (B5)
+scom 0x800003770901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][13];
+}
+
+#-- RX Signal Detect Level Register (B6)
+scom 0x800003B70901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][14];
+}
+
+#-- RX Signal Detect Level Register (B7)
+scom 0x800003F70901143F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[0][15];
+}
+
+#-- ZCAL Control Register
+scom 0x800008400901143F {
+    bits,     scom_data;
+    53:60,    ATTR_PROC_PCIE_IOP_ZCAL_CONTROL[0];
+}
+
+#-- ZCAL Override Register
+scom 0x800008420901143F {
+    bits,     scom_data;
+    48:63,    0xEC30;
+}
+
+
+#--
+#-- IOP 1
+#--
+
+#-- G3 PLL Control Register 0
+scom 0x800008010901187F {
+    bits,     scom_data;
+    51:63,    ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[1];
+}
+
+#-- G2 PLL Control Register 0
+scom 0x800008050901187F {
+    bits,     scom_data;
+    51:63,    ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0[1];
+}
+
+#-- PLL Global Control Register 0
+scom 0x800008080901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0[1];
+}
+
+#-- PLL Global Control Register 1
+scom 0x800008090901187F {
+    bits,     scom_data;
+    51:63,    ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1[1];
+}
+
+#-- PCS Control Register 0
+scom 0x800008800901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_PCS_CONTROL0[1];
+}
+
+#-- PCS Control Register 1
+scom 0x800008810901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_PCS_CONTROL1[1];
+}
+
+#-- TX FIFO Offset Register (A0)
+scom 0x800004010901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][0];
+}
+
+#-- TX FIFO Offset Register (A1)
+scom 0x800004410901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][1];
+}
+
+#-- TX FIFO Offset Register (A2)
+scom 0x800004810901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][2];
+}
+
+#-- TX FIFO Offset Register (A3)
+scom 0x800004C10901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][3];
+}
+
+#-- TX FIFO Offset Register (A4)
+scom 0x800005010901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][4];
+}
+
+#-- TX FIFO Offset Register (A5)
+scom 0x800005410901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][5];
+}
+
+#-- TX FIFO Offset Register (A6)
+scom 0x800005810901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][6];
+}
+
+#-- TX FIFO Offset Register (A7)
+scom 0x800005C10901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][7];
+}
+
+#-- TX FIFO Offset Register (B0)
+scom 0x800006010901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][8];
+}
+
+#-- TX FIFO Offset Register (B1)
+scom 0x800006410901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][9];
+}
+
+#-- TX FIFO Offset Register (B2)
+scom 0x800006810901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][10];
+}
+
+#-- TX FIFO Offset Register (B3)
+scom 0x800006C10901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][11];
+}
+
+#-- TX FIFO Offset Register (B4)
+scom 0x800007010901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][12];
+}
+
+#-- TX FIFO Offset Register (B5)
+scom 0x800007410901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][13];
+}
+
+#-- TX FIFO Offset Register (B6)
+scom 0x800007810901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][14];
+}
+
+#-- TX FIFO Offset Register (B7)
+scom 0x800007C10901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][15];
+}
+
+#-- TX Receiver Detect Control Register (A0)
+scom 0x800004020901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][0];
+}
+
+#-- TX Receiver Detect Control Register (A1)
+scom 0x800004420901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][1];
+}
+
+#-- TX Receiver Detect Control Register (A2)
+scom 0x800004820901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][2];
+}
+
+#-- TX Receiver Detect Control Register (A3)
+scom 0x800004C20901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][3];
+}
+
+#-- TX Receiver Detect Control Register (A4)
+scom 0x800005020901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][4];
+}
+
+#-- TX Receiver Detect Control Register (A5)
+scom 0x800005420901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][5];
+}
+
+#-- TX Receiver Detect Control Register (A6)
+scom 0x800005820901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][6];
+}
+
+#-- TX Receiver Detect Control Register (A7)
+scom 0x800005C20901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][7];
+}
+
+#-- TX Receiver Detect Control Register (B0)
+scom 0x800006020901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][8];
+}
+
+#-- TX Receiver Detect Control Register (B1)
+scom 0x800006420901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][9];
+}
+
+#-- TX Receiver Detect Control Register (B2)
+scom 0x800006820901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][10];
+}
+
+#-- TX Receiver Detect Control Register (B3)
+scom 0x800006C20901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][11];
+}
+
+#-- TX Receiver Detect Control Register (B4)
+scom 0x800007020901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][12];
+}
+
+#-- TX Receiver Detect Control Register (B5)
+scom 0x800007420901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][13];
+}
+
+#-- TX Receiver Detect Control Register (B6)
+scom 0x800007820901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][14];
+}
+
+#-- TX Receiver Detect Control Register (B7)
+scom 0x800007C20901187F {
+    bits,     scom_data;
+    49:63,    ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][15];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A0)
+scom 0x8000041B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][0];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A1)
+scom 0x8000045B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][1];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A2)
+scom 0x8000049B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][2];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A3)
+scom 0x800004DB0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][3];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A4)
+scom 0x8000051B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][4];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A5)
+scom 0x8000055B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][5];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A6)
+scom 0x8000059B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][6];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (A7)
+scom 0x800005DB0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][7];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B0)
+scom 0x8000061B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][8];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B1)
+scom 0x8000065B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][9];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B2)
+scom 0x8000069B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][10];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B3)
+scom 0x800006DB0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][11];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B4)
+scom 0x8000071B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][12];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B5)
+scom 0x8000075B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][13];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B6)
+scom 0x8000079B0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][14];
+}
+
+#-- TX Bandwidth Loss Coefficient Register (B7)
+scom 0x800007DB0901187F {
+    bits,     scom_data;
+    52:63,    ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][15];
+}
+
+#-- RX VGA Control Register2 (A0)
+scom 0x8000000C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][0];
+}
+
+#-- RX VGA Control Register2 (A1)
+scom 0x8000004C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][1];
+}
+
+#-- RX VGA Control Register2 (A2)
+scom 0x8000008C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][2];
+}
+
+#-- RX VGA Control Register2 (A3)
+scom 0x800000CC0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][3];
+}
+
+#-- RX VGA Control Register2 (A4)
+scom 0x8000010C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][4];
+}
+
+#-- RX VGA Control Register2 (A5)
+scom 0x8000014C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][5];
+}
+
+#-- RX VGA Control Register2 (A6)
+scom 0x8000018C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][6];
+}
+
+#-- RX VGA Control Register2 (A7)
+scom 0x800001CC0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][7];
+}
+
+#-- RX VGA Control Register2 (B0)
+scom 0x8000020C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][8];
+}
+
+#-- RX VGA Control Register2 (B1)
+scom 0x8000024C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][9];
+}
+
+#-- RX VGA Control Register2 (B2)
+scom 0x8000028C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][10];
+}
+
+#-- RX VGA Control Register2 (B3)
+scom 0x800002CC0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][11];
+}
+
+#-- RX VGA Control Register2 (B4)
+scom 0x8000030C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][12];
+}
+
+#-- RX VGA Control Register2 (B5)
+scom 0x8000034C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][13];
+}
+
+#-- RX VGA Control Register2 (B6)
+scom 0x8000038C0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][14];
+}
+
+#-- RX VGA Control Register2 (B7)
+scom 0x800003CC0901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][15];
+}
+
+#-- RX Receiver Peaking Register (A0)
+scom 0x800000100901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][0];
+}
+
+#-- RX Receiver Peaking Register (A1)
+scom 0x800000500901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][1];
+}
+
+#-- RX Receiver Peaking Register (A2)
+scom 0x800000900901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][2];
+}
+
+#-- RX Receiver Peaking Register (A3)
+scom 0x800000D00901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][3];
+}
+
+#-- RX Receiver Peaking Register (A4)
+scom 0x800001100901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][4];
+}
+
+#-- RX Receiver Peaking Register (A5)
+scom 0x800001500901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][5];
+}
+
+#-- RX Receiver Peaking Register (A6)
+scom 0x800001900901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][6];
+}
+
+#-- RX Receiver Peaking Register (A7)
+scom 0x800001D00901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][7];
+}
+
+#-- RX Receiver Peaking Register (B0)
+scom 0x800002100901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][8];
+}
+
+#-- RX Receiver Peaking Register (B1)
+scom 0x800002500901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][9];
+}
+
+#-- RX Receiver Peaking Register (B2)
+scom 0x800002900901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][10];
+}
+
+#-- RX Receiver Peaking Register (B3)
+scom 0x800002D00901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][11];
+}
+
+#-- RX Receiver Peaking Register (B4)
+scom 0x800003100901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][12];
+}
+
+#-- RX Receiver Peaking Register (B5)
+scom 0x800003500901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][13];
+}
+
+#-- RX Receiver Peaking Register (B6)
+scom 0x800003900901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][14];
+}
+
+#-- RX Receiver Peaking Register (B7)
+scom 0x800003D00901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_PEAK[1][15];
+}
+
+#-- RX Signal Detect Level Register (A0)
+scom 0x800000370901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][0];
+}
+
+#-- RX Signal Detect Level Register (A1)
+scom 0x800000770901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][1];
+}
+
+#-- RX Signal Detect Level Register (A2)
+scom 0x800000B70901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][2];
+}
+
+#-- RX Signal Detect Level Register (A3)
+scom 0x800000F70901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][3];
+}
+
+#-- RX Signal Detect Level Register (A4)
+scom 0x800001370901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][4];
+}
+
+#-- RX Signal Detect Level Register (A5)
+scom 0x800001770901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][5];
+}
+
+#-- RX Signal Detect Level Register (A6)
+scom 0x800001B70901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][6];
+}
+
+#-- RX Signal Detect Level Register (A7)
+scom 0x800001F70901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][7];
+}
+
+#-- RX Signal Detect Level Register (B0)
+scom 0x800002370901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][8];
+}
+
+#-- RX Signal Detect Level Register (B1)
+scom 0x800002770901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][9];
+}
+
+#-- RX Signal Detect Level Register (B2)
+scom 0x800002B70901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][10];
+}
+
+#-- RX Signal Detect Level Register (B3)
+scom 0x800002F70901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][11];
+}
+
+#-- RX Signal Detect Level Register (B4)
+scom 0x800003370901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][12];
+}
+
+#-- RX Signal Detect Level Register (B5)
+scom 0x800003770901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][13];
+}
+
+#-- RX Signal Detect Level Register (B6)
+scom 0x800003B70901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][14];
+}
+
+#-- RX Signal Detect Level Register (B7)
+scom 0x800003F70901187F {
+    bits,     scom_data;
+    48:63,    ATTR_PROC_PCIE_IOP_RX_SDL[1][15];
+}
+
+#-- ZCAL Control Register
+scom 0x800008400901187F {
+    bits,     scom_data;
+    53:60,    ATTR_PROC_PCIE_IOP_ZCAL_CONTROL[1];
+}
+
+#-- ZCAL Override Register
+scom 0x800008420901187F {
+    bits,     scom_data;
+    48:63,    0xEC30;
+}
diff --git a/src/usr/hwpf/hwp/nest_chiplets/makefile b/src/usr/hwpf/hwp/nest_chiplets/makefile
index 35e4fd3d6..b7c2982ac 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/makefile
+++ b/src/usr/hwpf/hwp/nest_chiplets/makefile
@@ -40,20 +40,23 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chip
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_scomoverride_chiplets
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit
 
 ##  NOTE: add new object files when you add a new HWP
 OBJS =  nest_chiplets.o \
-		proc_start_clocks_chiplets.o \
+        proc_start_clocks_chiplets.o \
         proc_chiplet_scominit.o \
         proc_scomoverride_chiplets.o \
         proc_a_x_pci_dmi_pll_initf.o \
-        proc_a_x_pci_dmi_pll_setup.o
+        proc_a_x_pci_dmi_pll_setup.o \
+        proc_pcie_scominit.o
         
 ##  NOTE: add a new directory onto the vpaths when you add a new HWP
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_scomoverride_chiplets
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit
 
 include ${ROOTPATH}/config.mk
 
diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
index 40791be2a..8a76dfef9 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C
@@ -68,6 +68,7 @@
 #include    "proc_scomoverride_chiplets/proc_scomoverride_chiplets.H"
 #include    "proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H"
 #include    "proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H"
+#include    "proc_pcie_scominit/proc_pcie_scominit.H"
 
 namespace   NEST_CHIPLETS
 {
@@ -101,24 +102,22 @@ void*    call_proc_a_x_pci_dmi_pll_initf( void    *io_pArgs )
         return  l_err ;
     }
 
-    uint8_t l_cpuNum = 0;
-
-    TARGETING::TargetHandleList l_cpuTargetList;
-
-    getAllChips(l_cpuTargetList, TYPE_PROC);
+    TARGETING::TargetHandleList l_procTargetList;
+    getAllChips(l_procTargetList, TYPE_PROC);
 
-    for ( l_cpuNum=0; l_cpuNum < l_cpuTargetList.size(); l_cpuNum++ )
+    for ( TargetHandleList::iterator l_iter = l_procTargetList.begin();
+          l_iter != l_procTargetList.end(); ++l_iter )
     {
-        const TARGETING::Target*  l_cpu_target = l_cpuTargetList[l_cpuNum];
+        const TARGETING::Target*  l_proc_target = *l_iter;
         const fapi::Target l_fapi_proc_target(
                             TARGET_TYPE_PROC_CHIP,
                             reinterpret_cast<void *>
-                            ( const_cast<TARGETING::Target*>(l_cpu_target) ) );
+                            ( const_cast<TARGETING::Target*>(l_proc_target) ) );
 
         TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                    "Running proc_a_x_pci_dmi_pll_initf HWP");
         EntityPath l_path;
-        l_path  =   l_cpu_target->getAttr<ATTR_PHYS_PATH>();
+        l_path  =   l_proc_target->getAttr<ATTR_PHYS_PATH>();
         l_path.dump();
 
         //  call proc_a_x_pci_dmi_pll_initf
@@ -136,7 +135,7 @@ void*    call_proc_a_x_pci_dmi_pll_initf( void    *io_pArgs )
                       " HWP returns error",
                       l_err->reasonCode());
 
-            ErrlUserDetailsTarget myDetails(l_cpu_target);
+            ErrlUserDetailsTarget myDetails(l_proc_target);
 
             // capture the target data in the elog
             myDetails.addToLog(l_err );
@@ -169,7 +168,7 @@ void*    call_proc_a_x_pci_dmi_pll_initf( void    *io_pArgs )
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                "call_proc_a_x_pci_dmi_pll_initf exit" );
-    return l_err;
+    return l_StepError.getErrorHandle();
 }
 
 //*****************************************************************************
@@ -195,13 +194,13 @@ void*    call_proc_a_x_pci_dmi_pll_setup( void    *io_pArgs )
         return  l_err ;
     }
 
-    uint8_t l_procNum = 0;
     TARGETING::TargetHandleList l_procTargetList;
     getAllChips(l_procTargetList, TYPE_PROC);
 
-    for ( l_procNum=0; l_procNum < l_procTargetList.size(); l_procNum++ )
+    for ( TargetHandleList::iterator l_iter = l_procTargetList.begin();
+          l_iter != l_procTargetList.end(); ++l_iter )
     {
-        const TARGETING::Target*  l_proc_target = l_procTargetList[l_procNum];
+        const TARGETING::Target*  l_proc_target = *l_iter;
         const fapi::Target l_fapi_proc_target(
                 TARGET_TYPE_PROC_CHIP,
                 reinterpret_cast<void *>
@@ -278,25 +277,24 @@ void*    call_proc_startclock_chiplets( void    *io_pArgs )
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, 
                "call_proc_startclock_chiplets entry" );
 
-    uint8_t l_cpuNum = 0;
-
-    TARGETING::TargetHandleList l_cpuTargetList;
-    getAllChips(l_cpuTargetList, TYPE_PROC);
+    TARGETING::TargetHandleList l_procTargetList;
+    getAllChips(l_procTargetList, TYPE_PROC);
 
-    for ( l_cpuNum=0; l_cpuNum < l_cpuTargetList.size(); l_cpuNum++ )
+    for ( TargetHandleList::iterator l_iter = l_procTargetList.begin();
+          l_iter != l_procTargetList.end(); ++l_iter )
     {
-        const TARGETING::Target*  l_cpu_target = l_cpuTargetList[l_cpuNum];
+        const TARGETING::Target*  l_proc_target = *l_iter;
         const fapi::Target l_fapi_proc_target(
                 TARGET_TYPE_PROC_CHIP,
                 reinterpret_cast<void *>
-                ( const_cast<TARGETING::Target*>(l_cpu_target) )
+                ( const_cast<TARGETING::Target*>(l_proc_target) )
         );
 
         TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, 
                    "Running proc_startclock_chiplets HWP on..." );
         //  dump physical path to targets
         EntityPath l_path;
-        l_path  =   l_cpu_target->getAttr<ATTR_PHYS_PATH>();
+        l_path  =   l_proc_target->getAttr<ATTR_PHYS_PATH>();
         l_path.dump();
 
         //  call the HWP with each fapi::Target
@@ -312,7 +310,7 @@ void*    call_proc_startclock_chiplets( void    *io_pArgs )
                       "returns error",
                        l_err->reasonCode());
 
-            ErrlUserDetailsTarget myDetails(l_cpu_target);
+            ErrlUserDetailsTarget myDetails(l_proc_target);
 
             // capture the target data in the elog
             myDetails.addToLog(l_err );
@@ -374,60 +372,75 @@ void*    call_proc_chiplet_scominit( void    *io_pArgs )
 void*    call_proc_pcie_scominit( void    *io_pArgs )
 {
     errlHndl_t          l_errl      =   NULL;
+    IStepError          l_StepError;
 
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, 
-               "call_proc_pcie_scominit entry" );
-
-#if 0
-    // @@@@@    CUSTOM BLOCK:   @@@@@
-    //  figure out what targets we need
-    //  customize any other inputs
-    //  set up loops to go through all targets (if parallel, spin off a task)
-
-    //  print call to hwp and dump physical path of the target(s)
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "=====  proc_pcie_scominit HWP(? ? ? )",
-                    ?
-                    ?
-                    ? );
-    //  dump physical path to targets
-    EntityPath l_path;
-    l_path  =   l_@targetN_target->getAttr<ATTR_PHYS_PATH>();
-    l_path.dump();
-    TRACFCOMP( g_trac_mc_init, "===== " );
-
-    // cast OUR type of target to a FAPI type of target.
-    const fapi::Target l_fapi_@targetN_target(
-                    TARGET_TYPE_MEMBUF_CHIP,
-                    reinterpret_cast<void *>
-                        (const_cast<TARGETING::Target*>(l_@targetN_target)) );
-
-    //  call the HWP with each fapi::Target
-    l_fapirc  =   proc_pcie_scominit( ? , ?, ? );
-
-    //  process return code.
-    if ( l_fapirc== fapi::FAPI_RC_SUCCESS )
-    {
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "SUCCESS :  proc_pcie_scominit HWP(? ? ? )" );
-    }
-    else
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                            "call_proc_pcie_scominit entry" );
+
+    TARGETING::TargetHandleList l_procTargetList;
+    getAllChips(l_procTargetList, TYPE_PROC);
+
+    for ( TargetHandleList::iterator l_iter = l_procTargetList.begin();
+          l_iter != l_procTargetList.end(); ++l_iter )
     {
-        /**
-         * @todo fapi error - just print out for now...
-         */
+        const TARGETING::Target*  l_proc_target = *l_iter;
+        const fapi::Target l_fapi_proc_target(
+                TARGET_TYPE_PROC_CHIP,
+                reinterpret_cast<void *>
+                ( const_cast<TARGETING::Target*>(l_proc_target) )
+        );
+
         TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "ERROR 0x%.8X:  proc_pcie_scominit HWP(? ? ?) ",
-                static_cast<uint32_t>(l_fapirc) );
+                   "Running proc_pcie_scominit HWP on..." );
+
+        //  dump physical path to targets
+        EntityPath l_path;
+        l_path  =   l_proc_target->getAttr<ATTR_PHYS_PATH>();
+        l_path.dump();
+
+        //  call the HWP with each fapi::Target
+        FAPI_INVOKE_HWP(l_errl, proc_pcie_scominit, l_fapi_proc_target);
+
+        if (l_errl)
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                      "ERROR 0x%.8X : proc_pcie_scominit HWP returns error",
+                      l_errl->reasonCode());
+
+            /*@
+             * @errortype
+             * @reasoncode  ISTEP_NEST_CHIPLETS_FAILED
+             * @severity    ERRORLOG::ERRL_SEV_UNRECOVERABLE
+             * @moduleid    ISTEP_PROC_PCIE_SCOMINIT
+             * @userdata1   bytes 0-1: plid identifying first error
+             *              bytes 2-3: reason code of first error
+             * @userdata2   bytes 0-1: total number of elogs included
+             *              bytes 2-3: N/A
+             * @devdesc     call to proc_pcie_scominit has failed
+             */
+            l_StepError.addErrorDetails(ISTEP_NEST_CHIPLETS_FAILED,
+                                        ISTEP_PROC_PCIE_SCOMINIT,
+                                        l_errl);
+
+            // capture the target data in the elog
+            ErrlUserDetailsTarget(l_proc_target).addToLog( l_errl );
+
+            errlCommit( l_errl, HWPF_COMP_ID );
+
+            break;
+        }
+        else
+        {
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "SUCCESS :  proc_pcie_scominit HWP" );
+        }
     }
-    // @@@@@    END CUSTOM BLOCK:   @@@@@
-#endif
 
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, 
-               "call_proc_pcie_scominit exit" );
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                            "call_proc_pcie_scominit exit" );
 
     // end task, returning any errorlogs to IStepDisp 
-    return l_errl;
+    return l_StepError.getErrorHandle();
 }
 
 //*****************************************************************************
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C
new file mode 100644
index 000000000..95ff319f4
--- /dev/null
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C
@@ -0,0 +1,403 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_pcie_scominit.C,v 1.1 2012/11/05 21:52:40 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.C,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : proc_pcie_scominit.C
+// *! DESCRIPTION : Perform PCIe Physical IO Inits (Phase 1, Steps 1-9) (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill        Email: jmcgill@us.ibm.com
+// *!
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+//  Includes
+//------------------------------------------------------------------------------
+#include <fapiHwpExecInitFile.H>
+#include "proc_pcie_scominit.H"
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// function: initialize IOP/PHB
+//             set master IOP lane configuration and IOP swap bits via PCIe GP4
+//             set PHB iovalids via PCIe GP0
+//             remove IOP logic from reset via PCIe GP4
+// parameters: i_target => processor chip target
+// returns: FAPI_RC_SUCCESS if all actions are successful,
+//          RC_PROC_PCIE_SCOMINIT_IOP_CONFIG_ATTR_ERR if invalid IOP lane
+//            configuration attribute value is presented,
+//          RC_PROC_PCIE_SCOMINIT_IOP_SWAP_ATTR_ERR if invalid IOP swap
+//            attribute value is presented,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_pcie_scominit_iop_init(
+    const fapi::Target & i_target)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+
+    // attribute storage
+    uint8_t iop_config;
+    uint8_t iop_swap[PROC_PCIE_SCOMINIT_NUM_IOP];
+    uint8_t phb_active_mask;
+    bool    phb_active[PROC_PCIE_SCOMINIT_NUM_PHB];
+
+    // data buffers for GP4/GP0 accesses
+    ecmdDataBufferBase gp4_data(64);
+    ecmdDataBufferBase gp0_data(64);
+
+    // mark function entry
+    FAPI_INF("proc_pcie_scominit_iop_init: Start");
+
+    do
+    {
+        // retrieve IOP lane configuration and check value received
+        FAPI_DBG("proc_pcie_scominit_iop_init: Querying IOP lane configuration attribute");
+        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_IOP_CONFIG,
+                           &i_target,
+                           iop_config);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_IOP_CONFIG)");
+            break;
+        }
+        FAPI_DBG("proc_pcie_scominit_iop_init: ATTR_PROC_PCIE_IOP_CONFIG = %02X",
+                 iop_config);
+        // ensure that encoded value is supported
+        if (iop_config > PCIE_GP4_IOP_LANE_CFG_MAX)
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Invalid IOP lane configuration attribute value 0x%02X",
+                     iop_config);
+            const uint8_t& ATTR_DATA = iop_config;
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_PCIE_SCOMINIT_IOP_CONFIG_ATTR_ERR);
+            break;
+        }
+
+        // retrieve per-IOP swap configuration and check value received
+        FAPI_DBG("proc_pcie_scominit_iop_init: Querying per-IOP swap attribute");
+        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_IOP_SWAP,
+                           &i_target,
+                           iop_swap);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_IOP_SWAP)");
+            break;
+        }
+        for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_IOP) && rc.ok(); i++)
+        {
+            FAPI_DBG("proc_pcie_scominit_iop_init: ATTR_PROC_PCIE_IOP_SWAP[%d]= %02X",
+                     i, iop_swap[i]);
+            if (iop_swap[i] > PCIE_GP4_IOP_SWAP_MAX)
+            {
+                FAPI_ERR("proc_pcie_scominit_iop_init: Invalid IOP%d swap attribute value 0x%02X",
+                         i, iop_swap[i]);
+                const uint8_t& IOP_DATA = i;
+                const uint8_t ATTR_DATA = iop_swap[i];
+                FAPI_SET_HWP_ERROR(rc, RC_PROC_PCIE_SCOMINIT_IOP_SWAP_ATTR_ERR);
+                break;
+            }
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+
+        // set PCIe GP4 mask for IOP lane configuration/swap setup
+        rc_ecmd |= gp4_data.insertFromRight(
+            iop_config,
+            PCIE_GP4_IOP_LANE_CFG_START_BIT,
+            (PCIE_GP4_IOP_LANE_CFG_END_BIT-
+             PCIE_GP4_IOP_LANE_CFG_START_BIT+1));
+
+        for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_IOP) && !rc_ecmd; i++)
+        {
+            rc_ecmd |= gp4_data.insertFromRight(
+                iop_swap[i],
+                PCIE_GP4_IOP_SWAP_START_BIT[i],
+                (PCIE_GP4_IOP_SWAP_END_BIT[i]-
+                 PCIE_GP4_IOP_SWAP_START_BIT[i]+1));
+        }
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Error 0x%x setting up PCIe GP4 IOP config data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write PCIe GP4 data via OR mask register
+        FAPI_DBG("proc_pcie_scominit_iop_init: Writing PCIe GP4 to set IOP configuration");
+        rc = fapiPutScom(i_target, PCIE_GP4_OR_0x09000007, gp4_data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Error from fapiPutScom (PCIE_GP4_OR_0x09000007)");
+            break;
+        }
+
+        // retrieve active PHB attribute and check value received
+        FAPI_DBG("proc_pcie_scominit_iop_init: Querying PHB active attribute");
+        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_PHB_ACTIVE,
+                           &i_target,
+                           phb_active_mask);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_PHB_ACTIVE)");
+            break;
+        }
+        for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_PHB); i++)
+        {
+            phb_active[i] = ((phb_active_mask >> (7-i)) & 0x1)?(true):(false);
+        }
+
+        // set PCIe GP0 mask for PHB iovalid
+        for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_PHB) && !rc_ecmd; i++)
+        {
+            rc_ecmd |= gp0_data.writeBit(
+                PCIE_GP0_PHB_IOVALID_BIT[i],
+                phb_active[i]);
+        }
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Error 0x%x setting up PCIe GP0 data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write PCIe GP0 data via OR mask register
+        FAPI_DBG("proc_pcie_scominit_iop_init: Writing PCIe GP0 to set PHB iovalids");
+        rc = fapiPutScom(i_target, PCIE_GP0_OR_0x09000005, gp0_data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Error from fapiPutScom (PCIE_GP0_OR_0x09000005)");
+            break;
+        }
+
+        // set PCIe GP4 mask for IOP reset
+        rc_ecmd |= gp4_data.flushTo0();
+        for (size_t i = 0; (i < PROC_PCIE_SCOMINIT_NUM_IOP) && !rc_ecmd; i++)
+        {
+            rc_ecmd |= gp4_data.setBit(
+                PCIE_GP4_IOP_RESET_BIT[i]);
+        }
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Error 0x%x setting up PCIe GP4 IOP reset data buffer (set)",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write PCIe GP4 OR mask register (set reset bit)
+        FAPI_DBG("proc_pcie_scominit_iop_init: Writing PCIe GP4 to set IOP reset");
+        rc = fapiPutScom(i_target, PCIE_GP4_OR_0x09000007, gp4_data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Error from fapiPutScom (PCIE_GP4_OR_0x09000007)");
+            break;
+        }
+
+        // invert data buffer to clear reset bits
+        rc_ecmd |= gp4_data.invert();
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Error 0x%x setting up PCIe GP4 IOP reset data buffer (clear)",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // write PCIe GP4 AND mask register (clear reset bit)
+        FAPI_DBG("proc_pcie_scominit_iop_init: Writing PCIe GP4 to clear IOP reset");
+        rc = fapiPutScom(i_target, PCIE_GP4_AND_0x09000006, gp4_data);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_init: Error from fapiPutScom (PCIE_GP4_AND_0x09000006)");
+            break;
+        }
+
+    } while(0);
+
+    // mark function exit
+    FAPI_INF("proc_pcie_scominit_iop_init: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: apply IOP customization via SCOM initfile
+// parameters: i_target => processor chip target
+// returns: FAPI_RC_SUCCESS if initfile evaluation is successful,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_pcie_scominit_iop_config(
+    const fapi::Target & i_target)
+{
+    fapi::ReturnCode rc;
+    std::vector<fapi::Target> targets;
+
+    // mark function entry
+    FAPI_INF("proc_pcie_scominit_iop_config: Start");
+
+    do
+    {
+        // execute Phase1 SCOM initfile
+        targets.push_back(i_target);
+        FAPI_INF("proc_pcie_scominit_iop_config: Executing %s on %s",
+                 PROC_PCIE_SCOMINIT_PHASE1_IF, i_target.toEcmdString());
+        FAPI_EXEC_HWP(
+            rc,
+            fapiHwpExecInitFile,
+            targets,
+            PROC_PCIE_SCOMINIT_PHASE1_IF);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_config: Error from fapiHwpExecInitfile executing %s on %s",
+                     PROC_PCIE_SCOMINIT_PHASE1_IF,
+                     i_target.toEcmdString());
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_INF("proc_pcie_scominit_iop_config: End");
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: mark IOP programming complete (executed after all IOP
+//           customization is complete)
+// parameters: i_target => processor chip target
+// returns: FAPI_RC_SUCCESS if program complete is successful for all IOPs,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_pcie_scominit_iop_complete(
+    const fapi::Target & i_target)
+{
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+    ecmdDataBufferBase data(64), mask(64);
+
+    // mark function entry
+    FAPI_INF("proc_pcie_scominit_iop_complete: Start");
+
+    do
+    {
+        // configure data/mask required to set program complete data pattern
+        rc_ecmd |= data.setBit(PLL_GLOBAL_CONTROL2_PROG_COMPLETE_BIT);
+        rc_ecmd |= mask.setBit(PLL_GLOBAL_CONTROL2_PROG_COMPLETE_BIT);
+        if (rc_ecmd)
+        {
+            FAPI_ERR("proc_pcie_scominit_iop_complete: Error 0x%x setting up PCIe PLL Global Control 2 register data buffer",
+                     rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+
+        // set IOP program complete
+        for (size_t i = 0; i < PROC_PCIE_SCOMINIT_NUM_IOP; i++)
+        {
+            rc = fapiPutScomUnderMask(i_target,
+                                      PROC_PCIE_SCOMINIT_PLL_GLOBAL_CONTROL2[i],
+                                      data,
+                                      mask);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_pcie_scominit_iop_complete: Error from fapiPutScomUnderMask (PCIE_IOP%d_PLL_GLOBAL_CONTROL2_0x%016llX)",
+                         i, PROC_PCIE_SCOMINIT_PLL_GLOBAL_CONTROL2[i]);
+                break;
+            }
+        }
+        if (!rc.ok())
+        {
+            break;
+        }
+    } while(0);
+
+    // mark function exit
+    FAPI_INF("proc_pcie_scominit_iop_complete: End");
+    return rc;
+}
+
+
+// HWP entry point, comments in header
+fapi::ReturnCode proc_pcie_scominit(
+    const fapi::Target & i_target)
+{
+    fapi::ReturnCode rc;
+
+    // mark HWP entry
+    FAPI_INF("proc_pcie_scominit: Start");
+
+    do
+    {
+        // check for supported target type
+        if (i_target.getType() != fapi::TARGET_TYPE_PROC_CHIP)
+        {
+            FAPI_ERR("proc_pcie_scominit: Unsupported target type");
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_PCIE_SCOMINIT_INVALID_TARGET);
+            break;
+        }
+
+        // initialize/configure/finalize IOP programming
+        rc = proc_pcie_scominit_iop_init(i_target);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_init");
+            break;
+        }
+
+        rc = proc_pcie_scominit_iop_config(i_target);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_config");
+            break;
+        }
+
+        rc = proc_pcie_scominit_iop_complete(i_target);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_pcie_scominit: Error from proc_pcie_scominit_iop_complete");
+            break;
+        }
+
+    } while(0);
+
+    // mark HWP exit
+    FAPI_INF("proc_pcie_scominit: End");
+    return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H
new file mode 100644
index 000000000..212ddddad
--- /dev/null
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H
@@ -0,0 +1,135 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_pcie_scominit.H,v 1.1 2012/11/05 21:52:43 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.H,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : proc_pcie_scominit.H
+// *! DESCRIPTION : Perform PCIe Physical IO Inits (Phase 1, Steps 1-9) (FAPI)
+// *!
+// *! OWNER NAME  : Joe McGill        Email: jmcgill@us.ibm.com
+// *!
+// *! ADDITIONAL COMMENTS :
+// *!   Set IOP lane config/swap bits
+// *!   Set iovalid for active PHBs
+// *!   Remove active IOPs from reset
+// *!   Perform IOP overrides/customization
+// *!   Mark IOP programming complete
+// *!
+//------------------------------------------------------------------------------
+
+#ifndef PROC_PCIE_SCOMINIT_H_
+#define PROC_PCIE_SCOMINIT_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi.H>
+#include "p8_scom_addresses.H"
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+
+// SCOM initfile to execute
+const char * const PROC_PCIE_SCOMINIT_PHASE1_IF = "p8.pe.phase1.scom.if";
+
+// PCIe physical constants
+const uint8_t PROC_PCIE_SCOMINIT_NUM_IOP = 2;
+const uint8_t PROC_PCIE_SCOMINIT_NUM_PHB = 3;
+
+// PCIe GP0 register field/bit definitions
+const uint32_t PCIE_GP0_PHB_IOVALID_BIT[PROC_PCIE_SCOMINIT_NUM_PHB] =
+{
+    48,
+    49,
+    50
+};
+
+// PCIe GP4 register field/bit definitions
+const uint32_t PCIE_GP4_IOP_RESET_BIT[PROC_PCIE_SCOMINIT_NUM_IOP] =
+{
+    37,
+    38
+};
+const uint32_t PCIE_GP4_IOP_LANE_CFG_START_BIT = 41;
+const uint32_t PCIE_GP4_IOP_LANE_CFG_END_BIT = 44;
+const uint32_t PCIE_GP4_IOP_SWAP_START_BIT[PROC_PCIE_SCOMINIT_NUM_IOP] =
+{
+    47,
+    53
+};
+const uint32_t PCIE_GP4_IOP_SWAP_END_BIT[PROC_PCIE_SCOMINIT_NUM_IOP] =
+{
+    49,
+    55
+};
+
+// Murano/Venice support lane configurations bewtween 0x0 & 0xC,
+// swap values between 0x0 & 0x7
+const uint8_t PCIE_GP4_IOP_LANE_CFG_MAX = 0xC;
+const uint8_t PCIE_GP4_IOP_SWAP_MAX = 0x7;
+
+
+// PCIe PLL Global Control Register 2 field/bit definitions
+const uint64_t PROC_PCIE_SCOMINIT_PLL_GLOBAL_CONTROL2[PROC_PCIE_SCOMINIT_NUM_IOP] =
+{
+    PCIE_IOP0_PLL_GLOBAL_CONTROL2_0x8000080A0901143F,
+    PCIE_IOP1_PLL_GLOBAL_CONTROL2_0x8000080A0901187F,
+};
+const uint32_t PLL_GLOBAL_CONTROL2_PROG_COMPLETE_BIT = 50;
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode
+(*proc_pcie_scominit_FP_t)(const fapi::Target & i_target);
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// function: perform PCIe Physical IO Inits (Phase 1, Steps 1-9)
+// parameters: i_target => processor chip target
+// returns: FAPI_RC_SUCCESS if all programming is successful,
+//          RC_PROC_PCIE_SCOMINIT_IOP_CONFIG_ATTR_ERR if invalid IOP lane
+//            configuration attribute value is presented,
+//          RC_PROC_PCIE_SCOMINIT_IOP_SWAP_ATTR_ERR if invalid IOP swap
+//            attribute value is presented,
+//          RC_PROC_PCIE_SCOMINIT_INVALID_TARGET if invalid target is supplied,
+//          else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_pcie_scominit(const fapi::Target & i_target);
+
+
+} // extern "C"
+
+#endif // PROC_PCIE_SCOMINIT_H_
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml
new file mode 100644
index 000000000..448658c9d
--- /dev/null
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml
@@ -0,0 +1,287 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- proc_pcie_scominit_attributes.xml -->
+<attributes>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_CONFIG</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>PCIE IOP lane configuration
+      creator: platform
+      consumer: proc_pcie_scominit
+      firmware notes:
+        Encoded PCIE IOP lane configuration
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_SWAP</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>PCIE IOP swap configuration
+      creator: platform
+      consumer: proc_pcie_scominit
+      firmware notes:
+        Encoded PCIE IOP swap configuration
+        Array index: IOP number (0:1)
+    </description>
+    <valueType>uint8</valueType>
+    <array>2</array>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_PHB_ACTIVE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>PCIE PHB valid mask
+      creator: platform
+      consumer: proc_pcie_scominit
+      firmware notes:
+        Bit mask defining set of active/valid PHBs
+        bit0=PHB0, bit1=PHB1, bit2=PHB2
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <persistRuntime/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      firmware notes:
+        PCIe Gen3 PLL Control Register 0.
+        ATUNE/CPISEL.
+        Array index: IOP number(0:1)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe Gen2/Gen1 PLL Control Register 0.
+        ATUNE/CPISEL.
+        Array index: IOP number (0:1)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe PLL Global Control Register 0.
+        REFISRC/REFISINK.
+        Array index: IOP number (0:1)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe PLL Global Control Register 1.
+	ENBGDOCPSRC/ENBGDOCAMP/REFVREG.
+        Array index: IOP number (0:1)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_PCS_CONTROL0</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe PCS Control Register 0.
+        BITLOCKTIME/ADDDREMDELTA_810_B/STARTUPDELTA_810_B/ADDDREMDELTA_810_A/
+        STARTUPDELTA_A/RXREJECTHANDLING/EQCOMLETERESPONSE.
+        Array index: IOP number (0:1)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_PCS_CONTROL1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe PCS Control Register 1.
+	RXSIGDETSETTING/ADDDREMDELTA_128130_B/STARTUPDELTA_128130_B/
+        ADDDREMDELTA_128130_A/STARTUPDELTA_128130_A.
+        Array index: IOP number (0:1)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe TX FIFO Offset Register.
+	G3OFFSET/G2OFFSET/G1OFFSET.
+        First array index: IOP number (0:1)
+        Second array index: Lane number (0:15)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2,16</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe TX Receiver Detect Control Register.
+        VREFSEL/RCVRDETCNT/DETDRVC/PH1WAIT.
+        First array index: IOP number (0:1)
+        Second array index: Lane number (0:15)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2,16</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_TX_BWLOSS1</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe TX Bandwidth Loss Coefficient Register.
+        GEN3BWCOEFF/GEN2BWCOEFF/GEN1BWCOEFF.
+        First array index: IOP number (0:1)
+        Second array index: Lane number (0:15)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2,16</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe RX VGA Control Register 2.
+        GAIN2/GAIN1.
+        First array index: IOP number (0:1)
+        Second array index: Lane number (0:15)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2,16</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_RX_PEAK</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe RX Receiver Peaking Value Register.
+	PEAK1/PEAK2/PEAK3.
+        First array index: IOP number (0:1)
+        Second array index: Lane number (0:15)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2,16</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_RX_SDL</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe RX Signal Detect Level Register.
+        SDLVL3/SDLVL2/SDLVL1.
+        First array index: IOP number (0:1)
+        Second array index: Lane number (0:15)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2,16</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_PROC_PCIE_IOP_ZCAL_CONTROL</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      creator: platform (MRW)
+      consumer: proc_pcie_scominit
+      notes:
+        PCIe ZCAL Control Register.
+        CMPEVALDLY.
+        Array index: IOP number (0:1)
+    </description>
+    <valueType>uint32</valueType>
+    <array>2</array>
+    <platInit/>
+  </attribute>
+  <!-- ********************************************************************* -->
+</attributes>
\ No newline at end of file
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_errors.xml
new file mode 100644
index 000000000..e93077e64
--- /dev/null
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_errors.xml
@@ -0,0 +1,41 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_errors.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for proc_pcie_scominit -->
+<hwpErrors>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_PCIE_SCOMINIT_INVALID_TARGET</rc>
+    <description>Invalid target type provided to HWP.</description>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_PCIE_SCOMINIT_IOP_CONFIG_ATTR_ERR</rc>
+    <description>Unsupported/invalid IOP lane configuration attribute value.</description>
+    <ffdc>ATTR_DATA</ffdc>
+  </hwpError>
+  <hwpError>
+    <rc>RC_PROC_PCIE_SCOMINIT_IOP_SWAP_ATTR_ERR</rc>
+    <description>Unsupported/invalid IOP swap configuration attribute value.</description>
+    <ffdc>IOP_DATA</ffdc>
+    <ffdc>ATTR_DATA</ffdc>
+  </hwpError>
+</hwpErrors>
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index d2e0ec9f6..4a7f93da2 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -49,9 +49,10 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml   \
     hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml \
     hwp/activate_powerbus/proc_build_smp/proc_adu_utils_errors.xml \
     hwp/thread_activate/proc_thread_control/proc_thread_control.xml \
-    hwp/erepair_errors.xml  \
+    hwp/erepair_errors.xml \
+    hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_errors.xml \
     hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar_errors.xml  \
-    hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup_errors.xml    \
+    hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup_errors.xml \
     hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_errors.xml   \
     hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_check_slave_sbe_seeprom_complete_errors.xml \
     hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc_errors.xml \
@@ -91,7 +92,8 @@ HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \
                      hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml \
                      hwp/activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml    \
                      hwp/runtime_attributes/pm_attributes_all_plat.xml \
-                     hwp/runtime_attributes/pm_attributes_all_hwp.xml
+                     hwp/runtime_attributes/pm_attributes_all_hwp.xml \
+                     hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml
 
 #------------------------------------------------------------------------------
 # Initfiles
@@ -102,7 +104,8 @@ HWP_INITFILES = hwp/initfiles/sample.initfile \
                 hwp/initfiles/mbs_def.initfile \
                 hwp/initfiles/mba_def.initfile \
                 hwp/initfiles/cen_ddrphy.initfile \
-                hwp/initfiles/p8.fbc.scom.initfile
+                hwp/initfiles/p8.fbc.scom.initfile \
+                hwp/initfiles/p8.pe.phase1.scom.initfile
 
 HWP_IF_DEFINE_DIR = hwp/initfiles
 
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 82d677ac7..cd5291fe5 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -6855,6 +6855,7 @@ Consumers: proc_build_gpstate_table.C (among others)
   <simpleType><uint8_t></uint8_t></simpleType>
   <persistency>non-volatile</persistency>
   <readable/>
+  <writeable/>
   <hwpfToHbAttrMap>
       <id>ATTR_PROC_PCIE_IOP_CONFIG</id>
       <macro>DIRECT</macro>
@@ -6876,6 +6877,7 @@ Consumers: proc_build_gpstate_table.C (among others)
   </simpleType>
   <persistency>non-volatile</persistency>
   <readable/>
+  <writeable/>
   <hwpfToHbAttrMap>
       <id>ATTR_PROC_PCIE_IOP_SWAP</id>
       <macro>DIRECT</macro>
@@ -6894,6 +6896,7 @@ Consumers: proc_build_gpstate_table.C (among others)
   <simpleType><uint8_t></uint8_t></simpleType>
   <persistency>non-volatile</persistency>
   <readable/>
+  <writeable/>
   <hwpfToHbAttrMap>
       <id>ATTR_PROC_PCIE_PHB_ACTIVE</id>
       <macro>DIRECT</macro>
diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk
index 5493824be..741fd9d2b 100644
--- a/src/usr/targeting/common/xmltohb/common.mk
+++ b/src/usr/targeting/common/xmltohb/common.mk
@@ -71,7 +71,8 @@ FAPI_ATTR_SOURCES =          \
     dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml \
     activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml \
     runtime_attributes/pm_attributes_all_hwp.xml \
-    runtime_attributes/pm_attributes_all_plat.xml 
+    runtime_attributes/pm_attributes_all_plat.xml \
+    nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml
 
 
 XMLTOHB_GENERIC_XML     = generic.xml