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authorcrgeddes <crgeddes@us.ibm.com>2015-06-29 16:24:27 -0500
committerStephen Cprek <smcprek@us.ibm.com>2016-02-19 17:06:20 -0600
commita4dd69b10ae11f0ad49726964fdb86966b5a05c8 (patch)
treee740ed09e6bc5e32aaacbfcfa87931bb240d3914
parent3bb5a40112c6e23b436edfc03d95f3175f7a32a0 (diff)
downloadtalos-hostboot-a4dd69b10ae11f0ad49726964fdb86966b5a05c8.tar.gz
talos-hostboot-a4dd69b10ae11f0ad49726964fdb86966b5a05c8.zip
P9 Targeting Updates: SCOM Translation
Added p9 scom translation interface created by hw team Modified scomtrans.C to consume the new interface Added test cases to scomtests.H to ensure p9 translation work Change-Id: I96ad729113235e264bbe864d677a8519362b5a4c RTC: 118804 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22785 Tested-by: Jenkins Server Reviewed-by: Elizabeth Liner <eliner@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat
-rw-r--r--src/include/usr/scom/scomreasoncodes.H10
-rw-r--r--src/makefile3
-rw-r--r--src/usr/scom/scom.mk14
-rw-r--r--src/usr/scom/scomtrans.C1132
-rw-r--r--src/usr/scom/scomtrans.H118
-rw-r--r--src/usr/scom/test/scomtest.H1802
-rw-r--r--src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml963
7 files changed, 1950 insertions, 2092 deletions
diff --git a/src/include/usr/scom/scomreasoncodes.H b/src/include/usr/scom/scomreasoncodes.H
index a8fb2d396..6bd96d52d 100644
--- a/src/include/usr/scom/scomreasoncodes.H
+++ b/src/include/usr/scom/scomreasoncodes.H
@@ -5,7 +5,9 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* COPYRIGHT International Business Machines Corp. 2011,2014 */
+/* Contributors Listed Below - COPYRIGHT 2012,2016 */
+/* [+] International Business Machines Corp. */
+/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
@@ -34,6 +36,7 @@ namespace SCOM
SCOM_PERFORM_TRANSLATE = 0x02,
SCOM_FIND_PARENT_TARGET = 0x03,
SCOM_CHECK_INDIRECT_AND_DO_SCOM = 0x04,
+ SCOM_TRANSLATE_P9 = 0x05,
};
enum scomReasonCode
@@ -46,6 +49,11 @@ namespace SCOM
SCOM_INDIRECT_READ_TIMEOUT = SCOM_COMP_ID | 0x06,
SCOM_INDIRECT_WRITE_FAIL = SCOM_COMP_ID | 0x07,
SCOM_INDIRECT_WRITE_TIMEOUT = SCOM_COMP_ID | 0x08,
+ SCOM_P9_TRANS_INVALID_TYPE = SCOM_COMP_ID | 0x09,
+ SCOM_INVALID_TRANSLATION = SCOM_COMP_ID | 0x0A,
+ SCOM_TRANS_CANT_FIND_PARENT = SCOM_COMP_ID | 0x0B,
+ SCOM_TARGET_ADDR_MISMATCH = SCOM_COMP_ID | 0x0C,
+ SCOM_ISCHIPUNITSCOM_INVALID = SCOM_COMP_ID | 0x0D,
};
};
diff --git a/src/makefile b/src/makefile
index f40dbc04c..285f453b2 100644
--- a/src/makefile
+++ b/src/makefile
@@ -191,6 +191,7 @@ TESTCASE_MODULES += testerrl
TESTCASE_MODULES += testhwas
TESTCASE_MODULES += testvpd
TESTCASE_MODULES += testsyslib
+TESTCASE_MODULES += testscom
#Requires main store memory @TODO RTC: 132577
#TESTCASE_MODULES += $(if $(CONFIG_VPO_COMPILE),,testdump)
@@ -215,8 +216,6 @@ TESTCASE_MODULES += testsyslib
#@TODO RTC: 138226 (p9 work in progress)
#TESTCASE_MODULES += testsbe
-#@TODO RTC: 118804
-#TESTCASE_MODULES += testscom
#*******************************************************
#These modules do not work and are not tracked by any stories
diff --git a/src/usr/scom/scom.mk b/src/usr/scom/scom.mk
index 7eaf2225c..5c8cbacbc 100644
--- a/src/usr/scom/scom.mk
+++ b/src/usr/scom/scom.mk
@@ -5,7 +5,9 @@
#
# OpenPOWER HostBoot Project
#
-# COPYRIGHT International Business Machines Corp. 2013,2014
+# Contributors Listed Below - COPYRIGHT 2013,2016
+# [+] International Business Machines Corp.
+#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
@@ -20,6 +22,14 @@
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG
-# common objects between hostboot and runtime hostboot
+
+
+VPATH += ${ROOTPATH}/src/import/chips/p9/common/scominfo/
+EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/scominfo/
+
+# Local Objects
OBJS += scom.o
OBJS += scomtrans.o
+
+# Objects From Import Directory
+OBJS += p9_scominfo.o
diff --git a/src/usr/scom/scomtrans.C b/src/usr/scom/scomtrans.C
index a4a59eca5..54e87b06d 100644
--- a/src/usr/scom/scomtrans.C
+++ b/src/usr/scom/scomtrans.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2012,2015 */
+/* Contributors Listed Below - COPYRIGHT 2012,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -23,17 +23,23 @@
/* */
/* IBM_PROLOG_END_TAG */
/**
- * @file scomtrans.C
- *
- * @brief Implementation of SCOM operations
- */
+* @file scomtrans.C
+*
+* @brief Implementation of SCOM operations
+*/
// Code up to date for version: p8 1.9/s1 1.3 of p8.chipunit.scominfo
-/*****************************************************************************/
+//Flow of the file:
+//Call startScomProcess --which calls--> scomTranslate
+// --which calls--> p9 translate --which returns to-->
+//startScomProcces --which then calls--> SCOM::checkIndirectAndDoScom
+
+/****************************************************************************/
// I n c l u d e s
-/*****************************************************************************/
+/****************************************************************************/
+#include <string.h>
#include <assert.h>
#include <devicefw/driverif.H>
#include <trace/interface.H>
@@ -44,9 +50,11 @@
#include <scom/scomreasoncodes.H>
#include <errl/errludtarget.H>
#include <initservice/initserviceif.H>
+#include <p9_scom_addr.H>
+#include <p9_scominfo.H>
#if __HOSTBOOT_RUNTIME
- #include "handleSpecialWakeup.H"
+ #include "handleSpecialWakeup.H"
#endif
// Trace definition
@@ -58,541 +66,133 @@ namespace SCOM
bool g_wakeupInProgress = false;
DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
- DeviceFW::SCOM,
- TARGETING::TYPE_EX,
- scomTranslate);
+ DeviceFW::SCOM,
+ TARGETING::TYPE_EX,
+ startScomProcess);
DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
- DeviceFW::SCOM,
- TARGETING::TYPE_MBA,
- scomTranslate);
+ DeviceFW::SCOM,
+ TARGETING::TYPE_MBA,
+ startScomProcess);
DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
- DeviceFW::SCOM,
- TARGETING::TYPE_MCS,
- scomTranslate);
+ DeviceFW::SCOM,
+ TARGETING::TYPE_MCS,
+ startScomProcess);
DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
- DeviceFW::SCOM,
- TARGETING::TYPE_XBUS,
- scomTranslate);
+ DeviceFW::SCOM,
+ TARGETING::TYPE_XBUS,
+ startScomProcess);
DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
- DeviceFW::SCOM,
- TARGETING::TYPE_ABUS,
- scomTranslate);
-
-
-///////////////////////////////////////////////////////////////////////////////
-///////////////////////////////////////////////////////////////////////////////
-errlHndl_t scomTranslate(DeviceFW::OperationType i_opType,
- TARGETING::Target* i_target,
- void* io_buffer,
- size_t& io_buflen,
- int64_t i_accessType,
- va_list i_args)
-
-{
- errlHndl_t l_err = NULL;
- bool l_invalidAddr = false;
- uint64_t l_instance = 0;
-
- uint64_t i_addr = va_arg(i_args,uint64_t);
-#if __HOSTBOOT_RUNTIME
- static const uint64_t l_lowerBound = 0x0000000010000000;
- static const uint64_t l_upperBound = 0x00000000100F0000;
-
- //true => FSP present, false =>OP HBRT
- bool isFSP_HBRT = INITSERVICE::spBaseServicesEnabled();
- TARGETING::Target* l_target_SW = NULL;
-#endif
- // Get the attribute type.
- TARGETING::TYPE l_type = i_target->getAttr<TARGETING::ATTR_TYPE>();
-
- // get the specific entry to determine the address.
- TARGETING::EntityPath epath;
+ DeviceFW::SCOM,
+ TARGETING::TYPE_ABUS,
+ startScomProcess);
- if (i_target->tryGetAttr<TARGETING::ATTR_PHYS_PATH>(epath))
- {
- if (l_type == TARGETING::TYPE_EX)
- {
-#if __HOSTBOOT_RUNTIME
- if(i_addr >= l_lowerBound && i_addr < l_upperBound
- && !g_wakeupInProgress && !isFSP_HBRT)
- {
- g_wakeupInProgress = true;
-
- l_err = handleSpecialWakeup(i_target,true);
- if(l_err)
- {
- TRACFCOMP(g_trac_scom,
- "Enable p8_cpu_special_wakeup ERROR");
-
- //capture the target data in the elog
- ERRORLOG::ErrlUserDetailsTarget(i_target).addToLog(l_err);
- }
- l_target_SW = i_target;
- g_wakeupInProgress = false;
- }
-#endif
-
- // Below are the assumptions used for the EX translate
- // EX
- // Mask : 0x1F00_0000
- // Range 1 : 0x1000_0000 - 0x10FF_FFFF
- //
- // bits 3:7 correspond to what EX chiplet is targeted.
- // where 0x10XXXXXX is for EX0
- //
- // where 0x13XXXXXX is for EX3
- // where 0x14XXXXXX is for EX4
- // ...
- // where 0x1CXXXXXX is for EX12
-
- // EX Mask = 0x7F000000 to catch other chiplets.
-
- // no indirect addresses to worry about*/
-
- // check to see that the Address is in the correct range
- if ((i_addr & SCOM_TRANS_EX_MASK) == SCOM_TRANS_EX_BASEADDR)
- {
- // Call the function that performs the translate
- l_err = scomPerformTranslate(epath,
- TARGETING::TYPE_EX,
- TARGETING::TYPE_PROC,
- 24,
- SCOM_TRANS_EX_MASK,
- i_target,
- i_addr );
- }
- else
- {
- // set invalid addr to true.. and create errorlog below.
- l_invalidAddr = true;
- }
- }
- else if (l_type == TARGETING::TYPE_MCS)
- {
-
- // MC0 MCS0 = 0x02011800 MCS-0 range 0
- // MC0 MCS1 = 0x02011880 MCS-1 range 0 + remainder
- // MC1 MCS0 = 0x02011900 MCS-2 range 1
- // MC1 MCS0 = 0x02011980 MCS-3 range 1 + remainder
- // IOMC0 = 0x02011A00 -NOT targeting this range..
-
- // MC2 MCS0 = 0x02011C00 MCS-4 range 2
- // MC2 MCS1 = 0x02011C80 MCS-5 range 2 + remainder
- // MC3 MCS0 = 0x02011D00 MCS-6 range 3
- // MC3 MCS1 = 0x02011D80 MCS-7 range 3 + remainder
-
-
- // SCOM_TRANS_MCS_MASK = 0xFFFFFFFF7FFFFF80
-
-
- // Check that we are working with the correct MCS direct address range
- if ((i_addr & SCOM_TRANS_MCS_MASK) == SCOM_TRANS_MCS_BASEADDR )
- {
-
- // Need to extract what instance of the entity we are at
- l_instance =
- epath.pathElementOfType(TARGETING::TYPE_MCS).instance;
-
- // based on the instance, update the address
-
- // range 1 - add 0x100 to the addr
- if( (l_instance / 2) == 1)
- {
- i_addr += 0x100;
- }
- // range 2 - add 0x400 to the addr
- else if( (l_instance / 2) == 2)
- {
- i_addr += 0x400;
- }
- // range 3 - add 0x500 to the addr
- else if( (l_instance / 2) == 3)
- {
- i_addr += 0x500;
- }
-
- // add 0x80 if the instance%2 is nonzero.
- if (l_instance % 2)
- {
- i_addr += 0x80;
- }
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_MCA,
+ startScomProcess);
- // Call to set the target to the parent target type
- l_err = scomfindParentTarget(epath,
- TARGETING::TYPE_PROC,
- i_target);
- }
- // 0x00000000_02011A00 MCS 0-3 # MCS/DMI0 Direct SCOM
- // 0x00000000_02011E00 MCS 4-7 # MCS/DMI4 Direct SCOM
- // Address translation from DMI0 (A->E)
- // SCOM_TRANS_MCS_DMI_BASEADDR = 0x0000000002011A00,
- // If the base address passed in is 0x2011A00 - we are dealing with
- // MCS/DMI. Use the instance to determine which one wanted. If
- // MCS 4-7 is targeted, translations is required.
- //
- // Also if we have a indirect address then we need to update the
- // same address bits as above whether indirect or not.. for
- // indirect specifically need to update bits 25-26 to get the
- // correct address range.
-
- // MCS Indirect mask = 0x80000060_FFFFFFFF
- // 0x80000060_02011A3F MCS 0 # DMI0 Indirect SCOM RX3
- // 0x80000040_02011A3F MCS 1 # DMI1 Indirect SCOM RX2
- // 0x80000000_02011A3F MCS 2 # DMI3 Indirect SCOM RX0
- // 0x80000020_02011A3F MCS 3 # DMI2 Indirect SCOM RX1
- //
- // 0x80000060_02011E3F MCS 4 # DMI4 Indirect SCOM RX3
- // 0x80000040_02011E3F MCS 5 # DMI5 Indirect SCOM RX2
- // 0x80000000_02011E3F MCS 6 # DMI7 Indirect SCOM RX0
- // 0x80000020_02011E3F MCS 7 # DMI6 Indirect SCOM RX1
- //
- // 0x80000460_02011A3F MCS 0 # DMI0 Indirect SCOM TX3
- // 0x80000440_02011A3F MCS 1 # DMI1 Indirect SCOM TX2
- // 0x80000400_02011A3F MCS 2 # DMI3 Indirect SCOM TX0
- // 0x80000420_02011A3F MCS 3 # DMI2 Indirect SCOM TX1
- //
- // 0x80000460_02011E3F MCS 4 # DMI4 Indirect SCOM TX3
- // 0x80000440_02011E3F MCS 5 # DMI5 Indirect SCOM TX2
- // 0x80000400_02011E3F MCS 6 # DMI7 Indirect SCOM TX0
- // 0x80000420_02011E3F MCS 7 # DMI6 Indirect SCOM TX1
- //
- // SCOM_TRANS_IND_MCS_BASEADDR = 0x8000006002011A00,
-
-
- // check that we are working with a MCS/DMI address range..
- // can be indirect or direct.
- else if (((i_addr & SCOM_TRANS_MCS_MASK) ==
- SCOM_TRANS_MCS_DMI_BASEADDR) || ((i_addr & SCOM_TRANS_IND_MCS_DMI_MASK) ==
- SCOM_TRANS_IND_MCS_DMI_BASEADDR))
- {
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_CORE,
+ startScomProcess);
- // Need to extract what instance of the entity we are at
- l_instance =
- epath.pathElementOfType(TARGETING::TYPE_MCS).instance;
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_PERV,
+ startScomProcess);
- // If we are dealing with an indirect SCOM MCS address
- // Need to update the address based on instance
- if ((i_addr & SCOM_TRANS_IND_MCS_DMI_MASK) ==
- SCOM_TRANS_IND_MCS_DMI_BASEADDR)
- {
- // based on the instance, update the address
- // If instance 0 or 4 then no updating required.
- if (l_instance % 4 != 0)
- {
- // zero out the instance bits that need to change
- i_addr = i_addr & 0xFFFFFF9FFFFFFFFF;
-
- // instance 1 or 5 - update instance in the addr
- if (l_instance % 4 == 1)
- {
- i_addr |= 0x4000000000;
- }
- // instance 3 or 7
- else if (l_instance % 4 == 3)
- {
- i_addr |= 0x2000000000;
- }
- // instance 2 or 6 is 0 so no bits to turn on.
- }
- }
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_EQ,
+ startScomProcess);
- // Need to update the address whether we are indirect or not
- // for the MCS/DMI address ranges.
- // need to do this check after above because we modify the base
- // address based on instance and the mask check would then fail
- if (l_instance > 3)
- {
- // or 0x400 to change 0x2011Axx to 0x2011Exx
- i_addr = i_addr | 0x400;
- }
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_MCBIST,
+ startScomProcess);
- // Call to set the target to the parent target type
- l_err = scomfindParentTarget(epath,
- TARGETING::TYPE_PROC,
- i_target);
- }
- else
- {
- l_invalidAddr = true;
- }
- }
- else if (l_type == TARGETING::TYPE_XBUS)
- {
- // XBUS Direct Address info
- // XBUS mask = 0xFFFFFC00
- // default>physical:sys-0/node-0/proc-0/xbus-0</default>
- // startAddr target
- // 0x04011000 XBUS 0 # XBUS0 Direct SCOM
- // 0x04011400 XBUS 1 # XBUS1 Direct SCOM
- // 0x04011C00 XBUS 2 # XBUS2 Direct SCOM
- // 0x04011800 XBUS 3 # XBUS3 Direct SCOM
- //
- // XBUS Indirect Address info
- // mask = 0x80000000_FFFFFFC0
- // 0x800000000401103F XBUS 0 # XBUS0 RX0 Indirect SCOM
- // 0x800000000401143F XBUS 1 # XBUS1 RX1 Indirect SCOM
- // 0x8000000004011C3F XBUS 2 # XBUS2 RX2 Indirect SCOM
- // 0x800000000401183F XBUS 3 # XBUS3 RX3 Indirect SCOM
- //
- // 0x800004000401103F XBUS 0 # XBUS0 TX0 Indirect SCOM
- // 0x800004000401143F XBUS 1 # XBUS1 TX1 Indirect SCOM
- // 0x8000040004011C3F XBUS 2 # XBUS2 TX2 Indirect SCOM
- // 0x800004000401183F XBUS 3 # XBUS3 TX3 Indirect SCOM
-
-
- // no differentiation between direct and indirect.. translate the same way
- // Check that we are working with the correct address range
- if ((i_addr & SCOM_TRANS_XBUS_MASK) == SCOM_TRANS_XBUS_BASEADDR )
- {
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_MI,
+ startScomProcess);
- // Need to extract what instance of the entity we are at
- l_instance =
- epath.pathElementOfType(TARGETING::TYPE_XBUS).instance;
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_DMI,
+ startScomProcess);
- // based on the instance, update the address
- if (l_instance != 0)
- {
- // zero out the address bits that need to change
- i_addr = i_addr & 0xFFFFFFFFFFFFF3FF;
-
- // range 1 - add 0x400 to the addr
- if (l_instance == 1)
- {
- i_addr += 0x400;
- }
- // range 2 - add 0xC00 to the addr
- else if (l_instance == 2)
- {
- i_addr += 0xC00;
- }
- // range 3 - add 0x800 to the addr
- else if (l_instance == 3)
- {
- i_addr += 0x800;
- }
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_OBUS,
+ startScomProcess);
- }
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_NVBUS,
+ startScomProcess);
- // Call to set the target to the parent target type
- l_err = scomfindParentTarget(epath,
- TARGETING::TYPE_PROC,
- i_target);
- }
- else
- {
- l_invalidAddr = true;
- }
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_SBE,
+ startScomProcess);
- }
- else if (l_type == TARGETING::TYPE_ABUS)
- {
- // ABUS
- // Mask : 0xFFFFFC00
- // Range 1 : 0x08010C00 - 0x08010C3F
-
- // default>physical:sys-0/node-0/proc-0/abus-0</default>
- // ABUS Direct addresses
- // ABUS mask 0x000000FF_FFFFFF80
- // 0x00000000_08010C00 # ABUS0-2 Direct SCOM
- //
- // Abus Indirect Addresses
- // Abus Indirect MASK = 0x80000060FFFFFFFF
- // 0x80000000_08010C3F ABUS 0 # ABUS0 RX0 Indirect SCOM
- // 0x80000020_08010C3F ABUS 1 # ABUS1 RX1 Indirect SCOM
- // 0x80000040_08010C3F ABUS 2 # ABUS2 RX2 Indirect SCOM
- //
- // 0x80000400_08010C3F ABUS 0 # ABUS0 TX0 Indirect SCOM
- // 0x80000420_08010C3F ABUS 1 # ABUS1 TX1 Indirect SCOM
- // 0x80000440_08010C3F ABUS 2 # ABUS2 TX2 Indirect SCOM
-
-
-
- // Check that we are working with the correct address range
- // the base address bits 32 to 64 are the same for both
- if ((i_addr & SCOM_TRANS_ABUS_MASK) == SCOM_TRANS_ABUS_BASEADDR )
- {
- // If we have an indirect address.. then need to translate
- if ((i_addr & SCOM_TRANS_INDIRECT_MASK) == SCOM_TRANS_INDIRECT_ADDRESS)
- {
-
- // Need to extract what instance of the entity we are at
- l_instance =
- epath.pathElementOfType(TARGETING::TYPE_ABUS).instance;
-
-
- // Need to update the upper bits of the indirect scom address.
- uint64_t temp_instance = l_instance << 37;
- i_addr = i_addr | temp_instance;
-
- }
- // get the parent..
- l_err = scomfindParentTarget(epath,
- TARGETING::TYPE_PROC,
- i_target);
- }
-
- else
- {
- // got and error.. bad address.. write an errorlog..
- l_invalidAddr = true;
- }
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_PPE,
+ startScomProcess);
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_PEC,
+ startScomProcess);
- }
- else if (l_type == TARGETING::TYPE_MBA)
- {
- // MBA
- // SCOM_TRANS_MBA_MASK = 0xFFFFFFFF7FFFFC00,
- // SCOM_TRANS_MBA_BASEADDR = 0x0000000003010400,
- //
- // SCOM_TRANS_TCM_MBA_MASK = 0xFFFFFFFFFFFFFC00
- // SCOM_TRANS_TCM_MBA_BASEADDR = 0x0000000003010800
- //
- // In the XML.. the
- // <default>physical:sys-0/node-0/membuf-10/mbs-0/mba-1</default>
- //
- // Assuming the MBA we are accessing is under the Centaur
- // not the processor.. for now.
- //
- // 0x00000000_03010400 MBA 0 # MBA01
- // 0x00000000_03010C00 MBA 1 # MBA23
-
- // 0x00000000_03010880 MBA 0 # Trace for MBA01
- // 0x00000000_030110C0 MBA 1 # Trace for MBA23
-
- // 0x00000000_03011400 MBA 0 # DPHY01 (indirect addressing)
- // 0x00000000_03011800 MBA 1 # DPHY23 (indirect addressing)
-
- // 0x80000000_0301143f MBA 0 # DPHY01 (indirect addressing)
- // 0x80000000_0301183f MBA 1 # DPHY23 (indirect addressing)
-
- // 0x80000000_0701143f MBA 0 # DPHY01 (indirect addressing)
- // 0x80000000_0701183f MBA 1 # DPHY23 (indirect addressing)
- //
-
- // SCOM_TRANS_IND_MBA_MASK = 0x80000000FFFFFFFF,
- // SCOM_TRANS_IND_MBA_BASEADDR = 0x800000000301143f,
-
- // check to see that the Address is in the correct direct
- // scom MBA address range.
- if ( (i_addr & SCOM_TRANS_MBA_MASK) == SCOM_TRANS_MBA_BASEADDR )
- {
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_PHB,
+ startScomProcess);
- l_err = scomPerformTranslate(epath,
- TARGETING::TYPE_MBA,
- TARGETING::TYPE_MEMBUF,
- 11,
- SCOM_TRANS_MBA_MASK,
- i_target,
- i_addr );
- }
+DEVICE_REGISTER_ROUTE(DeviceFW::WILDCARD,
+ DeviceFW::SCOM,
+ TARGETING::TYPE_OCC,
+ startScomProcess);
- // New TCM MBA registers for DD2.0
- else if ( (i_addr & SCOM_TRANS_TCM_MBA_MASK) ==
- SCOM_TRANS_TCM_MBA_BASEADDR )
- {
- l_instance = epath.pathElementOfType(TARGETING::TYPE_MBA).instance;
- i_addr = i_addr + (l_instance * SCOM_TRANS_TCM_MBA_OFFSET);
- // Call to set the target to the parent target type
- l_err = scomfindParentTarget(epath,
- TARGETING::TYPE_MEMBUF,
- i_target);
- }
-
- // check to see if valid MBA 0 indirect address range
- else if ((i_addr & SCOM_TRANS_IND_MBA_MASK) ==
- SCOM_TRANS_IND_MBA_BASEADDR)
- {
- // Need to extract what instance of the entity we are
- l_instance =
- epath.pathElementOfType(TARGETING::TYPE_MBA).instance;
- // If instance is 1 then need to update address
- if (l_instance == 1)
- {
- // Have address 0301143f need address 0301183f
- i_addr = i_addr & 0xFFFFFFFFFFFFFBFF;
- i_addr = i_addr | 0x00000800;
- }
- // Call to set the target to the parent target type
- l_err = scomfindParentTarget(epath,
- TARGETING::TYPE_MEMBUF,
- i_target);
- }
- else
- {
- // got and error.. bad address.. write an errorlog..
- l_invalidAddr = true;
- }
- }
- else
- {
- // Send an errorlog because we are called with an unsupported type.
- TRACFCOMP(g_trac_scom, "SCOM_TRANSLATE.. Invalid target type=0x%X", l_type);
+//////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////
- /*@
- * @errortype
- * @moduleid SCOM::SCOM_TRANSLATE
- * @reasoncode SCOM::SCOM_TRANS_INVALID_TYPE
- * @userdata1 Address
- * @userdata2 Target Type that failed
- * @devdesc Scom Translate not supported for this type
- */
- l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
- SCOM_TRANSLATE,
- SCOM_TRANS_INVALID_TYPE,
- i_addr,
- l_type,
- true/*SW Error*/);
- //Add this target to the FFDC
- ERRORLOG::ErrlUserDetailsTarget(i_target,"SCOM Target")
- .addToLog(l_err);
- }
- }
+errlHndl_t startScomProcess(DeviceFW::OperationType i_opType,
+ TARGETING::Target* i_target,
+ void* io_buffer,
+ size_t& io_buflen,
+ int64_t i_accessType,
+ va_list i_args)
+{
+ errlHndl_t l_err = NULL;
+ TARGETING::Target* l_target_SW = NULL;
- if (l_invalidAddr)
- {
+ //will hold the value of parent chip for indirect scom
+ TARGETING::Target* l_parentChip =
+ const_cast<TARGETING::Target *>(TARGETING::getParentChip(i_target));
+ uint64_t l_addr = va_arg(i_args,uint64_t);
- TRACFCOMP(g_trac_scom, "scomTranslate-Invalid Address i_addr=0x%X, Type 0x%.8X, HUID 0x%.8X",
- i_addr, l_type, TARGETING::get_huid(i_target));
-
- /*@
- * @errortype
- * @moduleid SCOM::SCOM_TRANSLATE
- * @reasoncode SCOM::SCOM_INVALID_ADDR
- * @userdata1 Address
- * @userdata2 Unit type that failed
- * @devdesc Invalid address for that unit
- */
- l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
- SCOM_TRANSLATE,
- SCOM_INVALID_ADDR,
- i_addr,
- l_type,
- true/*SW Error*/);
- //Add this target to the FFDC
- ERRORLOG::ErrlUserDetailsTarget(i_target,"SCOM Target")
- .addToLog(l_err);
- l_err->collectTrace(SCOM_COMP_NAME,1024);
+ l_err = scomTranslate(i_target, l_addr, l_target_SW);
- }
if (l_err == NULL)
{
-
- // call the routine that will do the indirect scom
- // and then call the correct device driver.
- l_err = SCOM::checkIndirectAndDoScom(i_opType,
- i_target,
+ // call the routine that will do the indirect scom
+ // and then call the correct device driver.
+ l_err = SCOM::checkIndirectAndDoScom(i_opType,
+ l_parentChip,
io_buffer,
io_buflen,
i_accessType,
- i_addr);
+ l_addr);
}
// @todo RTC:124196 need to move this to a more general location so that
@@ -623,136 +223,448 @@ errlHndl_t scomTranslate(DeviceFW::OperationType i_opType,
return l_err;
}
-///////////////////////////////////////////////////////////////////////////////
-///////////////////////////////////////////////////////////////////////////////
-errlHndl_t scomPerformTranslate(TARGETING::EntityPath i_epath,
- TARGETING::TYPE i_ctype,
- TARGETING::TYPE i_ptype,
- int i_shift,
- uint64_t i_mask,
- TARGETING::Target * &o_target,
- uint64_t &i_addr )
+//////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////
+errlHndl_t scomTranslate(TARGETING::Target * &i_target,
+ uint64_t & io_addr,
+ TARGETING::Target * io_target_SW)
{
-
errlHndl_t l_err = NULL;
- uint64_t l_instance;
+ // Get the type attribute.
+ TARGETING::TYPE l_type = i_target->getAttr<TARGETING::ATTR_TYPE>();
- // Need to extract what instance of the entity we are at we are
- // for this target.
- l_instance = i_epath.pathElementOfType(i_ctype).instance;
+ //Need to support centaur still @TODO RTC: 139953
- // shift the instance variable over specificed number of
- // bits with the chiplet area
- l_instance = l_instance << i_shift;
+ l_err = p9_translation(i_target,
+ l_type,
+ io_addr,
+ io_target_SW);
- // Check the address against the mask
- if (i_addr & i_mask)
- {
- // add the instance of this target to the address
- i_addr = i_addr | l_instance;
- }
- else
- {
- TRACFCOMP(g_trac_scom,"SCOMPERFORMTRANSLATE Invalid Address.i_addr =0x%X for mask = 0x%X", i_addr, i_mask);
-
- /*@
- * @errortype
- * @moduleid SCOM::SCOM_PERFORM_TRANSLATE
- * @reasoncode SCOM::SCOM_INVALID_ADDR
- * @userdata1 Address
- * @userdata2 Unit type that failed
- * @devdesc Invalid Address for the mask passed in.
- */
- l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
- SCOM_PERFORM_TRANSLATE,
- SCOM_INVALID_ADDR,
- i_addr,
- o_target->getAttr<TARGETING::ATTR_TYPE>(),
- true/*SW Error*/);
- //Add this target to the FFDC
- ERRORLOG::ErrlUserDetailsTarget(o_target,"SCOM Target")
- .addToLog(l_err);
+ return l_err;
+}
- l_err->collectTrace(SCOM_COMP_NAME,1024);
+//////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////
+errlHndl_t p9_translation (TARGETING::Target * &i_target,
+ TARGETING::TYPE i_type,
+ uint64_t &io_addr,
+ TARGETING::Target * io_target_SW)
+{
+ errlHndl_t l_err = NULL;
+ do {
+ uint64_t l_original_addr = io_addr;
+ uint32_t l_chip_mode = STANDARD_MODE;
+ bool l_scomAddrIsRelatedToUnit = false;
+ bool l_scomAddrAndTargetTypeMatch = false;
- return (l_err);
- }
+ uint16_t l_instance = 0;
+ p9ChipUnits_t l_chipUnit = NONE;
+ std::vector<p9_chipUnitPairing_t> l_scomPairings;
- l_err = scomfindParentTarget(i_epath,
- i_ptype,
- o_target);
+ //Make sure that scom addr is related to a chip unit
+ uint32_t isChipUnitScomRC = p9_scominfo_isChipUnitScom(io_addr,
+ l_scomAddrIsRelatedToUnit,
+ l_scomPairings,
+ l_chip_mode);
- return l_err;
+ if(isChipUnitScomRC)
+ {
+ /*@
+ * @errortype
+ * @moduleid SCOM::SCOM_TRANSLATE_P9
+ * @reasoncode SCOM::SCOM_ISCHIPUNITSCOM_INVALID
+ * @userdata1 Input address
+ * @userdata2[0:31] Target huid
+ * @userdata2[32:63] Target Type
+ * @devdesc EKB code has detected and error in the scom
+ * @custdesc Firmware error during system IPL
+ */
+ l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+ SCOM_TRANSLATE_P9,
+ SCOM_ISCHIPUNITSCOM_INVALID,
+ l_original_addr,
+ TWO_UINT32_TO_UINT64(
+ i_target->getAttr<TARGETING::ATTR_HUID>(),
+ i_type),
+ true/*SW Error*/);
+ //Add this target to the FFDC
+ ERRORLOG::ErrlUserDetailsTarget(i_target,"SCOM Target")
+ .addToLog(l_err);
+ l_err->collectTrace(SCOM_COMP_NAME,1024);
+ break;
+ }
-}
-///////////////////////////////////////////////////////////////////////////////
-///////////////////////////////////////////////////////////////////////////////
-errlHndl_t scomfindParentTarget( TARGETING::EntityPath i_epath,
- TARGETING::TYPE i_ptype,
- TARGETING::Target * &o_target)
-{
+#if __HOSTBOOT_RUNTIME
+ //true => FSP present, false =>OP HBRT
+ bool isFSP_HBRT = INITSERVICE::spBaseServicesEnabled();
- errlHndl_t l_err = NULL;
+ if(((i_type == TARGETING::TYPE_EX) || (i_type == TARGETING::TYPE_CORE)) &&
+ (!g_wakeupInProgress) && (!isFSP_HBRT) )
+ {
+ bool l_needsWakeup = true;
+ for(uint16_t i = 0; i < l_scomPairings.size(); i++)
+ {
+ if( l_scomPairings[i].chipUnitType == PU_PERV_CHIPUNIT)
+ {
+ l_needsWakeup = false;
+ break;
+ }
+ }
+ if(l_needsWakeup)
+ {
+ g_wakeupInProgress = true;
- bool foundParent = false;
+ l_err = handleSpecialWakeup(i_target,true);
+ if(l_err)
+ {
+ TRACFCOMP(g_trac_scom,
+ "Enable handleSpecialWakeup ERROR");
- // This routine passes in a given target.. the goal is to find its parent
- // target that matches the passed in parent type.
+ //capture the target data in the elog
+ ERRORLOG::ErrlUserDetailsTarget(i_target,"SCOM Target")
+ .addToLog(l_err);
+ l_err->collectTrace(SCOM_COMP_NAME,1024);
+ break;
+ }
+ io_target_SW = i_target;
+ g_wakeupInProgress = false;
+ }
+ }
+#endif
- // This loop takes the last item off the entity path and
- // checks to see if it matches the parent type.. If it does
- // we exit.. it continues to loop until it either finds
- // a match, or runs out of elements.
- do
- {
- // remove the last entry from the entity path..
- i_epath.removeLast();
- int lastEntry = i_epath.size() - 1;
+ if(!l_scomAddrIsRelatedToUnit)
+ {
+ TRACFCOMP(g_trac_scom, "Address provided does not match any targets.");
+ TRACFCOMP(g_trac_scom, "scomTranslate-Invalid Address io_addr=0x%X, Type 0x%.8X, HUID 0x%.8X",
+ io_addr, i_type, TARGETING::get_huid(i_target));
+
+
+ uint32_t userdata32_1 = TWO_UINT16_TO_UINT32(
+ i_type,
+ l_instance);
+ uint16_t userdata16_1 = TWO_UINT8_TO_UINT16(
+ l_scomAddrIsRelatedToUnit,
+ l_scomAddrAndTargetTypeMatch);
+ uint16_t userdata16_2 = TWO_UINT8_TO_UINT16(
+ l_chipUnit,
+ TARGETING::MODEL_POWER9);
+ uint32_t userdata32_2 = TWO_UINT16_TO_UINT32(
+ userdata16_1,
+ userdata16_2);
+ uint64_t userdata64_1 = TWO_UINT32_TO_UINT64(
+ userdata32_1,
+ userdata32_2);
+ /*@
+ * @errortype
+ * @moduleid SCOM::SCOM_TRANSLATE_P9
+ * @reasoncode SCOM::SCOM_INVALID_ADDR
+ * @userdata1 Address
+ * @userdata2[0:15] Target's Type
+ * @userdata2[16:31] Instance of this type
+ * @userdata2[32:39] Is this SCOM addr related to a chip unit?
+ * @userdata2[40:47] Does the target type and addr type match?
+ * @userdata2[48:55] Chip unit of the target
+ * @userdata2[56:63] Model of the target (ex: POWER9)
+ * @devdesc The scom address provided was invalid, check
+ * to see if the address matches a target in the
+ * scomdef file.
+ * @custdesc Firmware error during system IPL
+ */
+ l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+ SCOM_TRANSLATE_P9,
+ SCOM_INVALID_ADDR,
+ io_addr,
+ userdata64_1,
+ true/*SW Error*/);
+ //Add this target to the FFDC
+ ERRORLOG::ErrlUserDetailsTarget(i_target,"SCOM Target")
+ .addToLog(l_err);
+ l_err->collectTrace(SCOM_COMP_NAME,1024);
+ break;
+ }
- // if the type equals the type passed in. then create the target
- if (i_epath[lastEntry].type == i_ptype)
+ if(getChipUnit (i_type, l_chipUnit))
{
- // return the target to be the parent type.
- o_target = TARGETING::targetService().toTarget(i_epath);
+ //Send an errorlog because we are targeting an unsupported type.
+ TRACFCOMP(g_trac_scom, "SCOM_TRANSLATE.. Invalid target type=0x%X", i_type);
+
+ /*@
+ * @errortype
+ * @moduleid SCOM::SCOM_TRANSLATE_P9
+ * @reasoncode SCOM::SCOM_P9_TRANS_INVALID_TYPE
+ * @userdata1 Address
+ * @userdata2[0:31] Target's Type
+ * @userdata2[32:63] Target's Huid
+ * @devdesc Scom Translate not supported for this type
+ */
+ l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+ SCOM_TRANSLATE_P9,
+ SCOM_P9_TRANS_INVALID_TYPE,
+ io_addr,
+ TWO_UINT32_TO_UINT64(i_type,
+ TARGETING::get_huid(i_target)),
+ true/*SW Error*/);
+ //Add this target to the FFDC
+ ERRORLOG::ErrlUserDetailsTarget(i_target,"SCOM Target")
+ .addToLog(l_err);
+ l_err->collectTrace(SCOM_COMP_NAME,1024);
+ break;
+ }
- foundParent = true;
+ //check each scom pairing to make sure we have a match
+ for(uint32_t i = 0; i < l_scomPairings.size(); i++)
+ {
+ if( l_scomPairings[i].chipUnitType == l_chipUnit)
+ {
+ l_scomAddrAndTargetTypeMatch = true;
+ break;
+ }
- break;
}
- }
- while (i_epath.size() != 0);
- if (!foundParent)
+ if(!l_scomAddrAndTargetTypeMatch)
+ {
+ TRACFCOMP(g_trac_scom, "Target type and scom Addr do not match.");
+ TRACFCOMP(g_trac_scom, "scomTranslate-Invalid Address io_addr=0x%X, Type 0x%.8X, HUID 0x%.8X",
+ io_addr, i_type, TARGETING::get_huid(i_target));
+
+
+ uint32_t userdata32_1 = TWO_UINT16_TO_UINT32(
+ i_type,
+ l_instance);
+ uint16_t userdata16_1 = TWO_UINT8_TO_UINT16(
+ l_scomAddrIsRelatedToUnit,
+ l_scomAddrAndTargetTypeMatch);
+ uint16_t userdata16_2 = TWO_UINT8_TO_UINT16(
+ l_chipUnit,
+ TARGETING::MODEL_POWER9);
+ uint32_t userdata32_2 = TWO_UINT16_TO_UINT32(
+ userdata16_1,
+ userdata16_2);
+ uint64_t userdata64_1 = TWO_UINT32_TO_UINT64(
+ userdata32_1,
+ userdata32_2);
+ /*@
+ * @errortype
+ * @moduleid SCOM::SCOM_TRANSLATE_P9
+ * @reasoncode SCOM::SCOM_TARGET_ADDR_MISMATCH
+ * @userdata1 Address
+ * @userdata2[0:15] Target's Type
+ * @userdata2[16:31] Instance of this type
+ * @userdata2[32:39] Is this SCOM addr related to a chip unit?
+ * @userdata2[40:47] Does the target type and addr type match?
+ * @userdata2[48:55] Chip unit of the target
+ * @userdata2[56:63] Model of the target (ex: POWER9)
+ * @devdesc The scom target did not match the provided
+ * address
+ * @custdesc Firmware error during system IPL
+ */
+ l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+ SCOM_TRANSLATE_P9,
+ SCOM_TARGET_ADDR_MISMATCH,
+ io_addr,
+ userdata64_1,
+ true/*SW Error*/);
+ //Add this target to the FFDC
+ ERRORLOG::ErrlUserDetailsTarget(i_target,"SCOM Target")
+ .addToLog(l_err);
+ l_err->collectTrace(SCOM_COMP_NAME,1024);
+ break;
+ }
+
+ l_instance = i_target->getAttr<TARGETING::ATTR_CHIP_UNIT>();
+ io_addr = p9_scominfo_createChipUnitScomAddr(l_chipUnit,
+ l_instance,
+ io_addr,
+ l_chip_mode);
+
+ if(io_addr == FAILED_TRANSLATION)
+ {
+ TRACFCOMP(g_trac_scom, "Address failed to translate.");
+ TRACFCOMP(g_trac_scom, "Scom Target HUID: 0x%x", TARGETING::get_huid(i_target));
+ TRACFCOMP(g_trac_scom, "Scom Address: 0x%lx", io_addr);
+ TRACFCOMP(g_trac_scom, "Scom Target Type: 0x%x", i_type);
+ for(uint32_t i = 0; i < l_scomPairings.size(); i++)
+ {
+ TRACFCOMP(g_trac_scom, "Scom Pairing %d: %d",
+ i, l_scomPairings[i].chipUnitType);
+ }
+ uint32_t userdata32 = TWO_UINT16_TO_UINT32(
+ l_chipUnit,
+ l_instance);
+ uint64_t userdata64 = TWO_UINT32_TO_UINT64(
+ userdata32,
+ TARGETING::get_huid(i_target));
+ /*@
+ * @errortype
+ * @moduleid SCOM::SCOM_TRANSLATE_P9
+ * @reasoncode SCOM::SCOM_INVALID_TRANSLATION
+ * @userdata1 Original Address
+ * @userdata2[0:15] l_chipUnit
+ * @userdata2[16:31] instance of target
+ * @userdata2[32:63] HUID of target
+ * @devdesc Scom Translation did not modify the address
+ */
+ l_err = new ERRORLOG::ErrlEntry(
+ ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+ SCOM_TRANSLATE_P9,
+ SCOM_INVALID_TRANSLATION,
+ l_original_addr,
+ userdata64,
+ true/*SW Error*/);
+ //Add this target to the FFDC
+ ERRORLOG::ErrlUserDetailsTarget(i_target,"SCOM Target")
+ .addToLog(l_err);
+ l_err->collectTrace(SCOM_COMP_NAME,1024);
+ break;
+ }
+
+ } while (0);
+ return l_err;
+}
+
+bool getChipUnit (TARGETING::TYPE i_type,
+ p9ChipUnits_t &o_chipUnit)
+{
+ bool l_isError = false;
+ switch(i_type)
{
- TRACFCOMP(g_trac_scom, "TRANSLATE..Did not find parent type=0x%X ", i_ptype);
- /*@
- * @errortype
- * @moduleid SCOM::SCOM_PERFORM_TRANSLATE
- * @reasoncode SCOM::SCOM_NO_MATCHING_PARENT
- * @userdata1 Parent type requested
- * @userdata2 Unit type that failed
- * @devdesc Did not find parent type requested
- */
- l_err = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
- SCOM_FIND_PARENT_TARGET,
- SCOM_NO_MATCHING_PARENT,
- i_ptype,
- o_target->getAttr<TARGETING::ATTR_TYPE>(),
- true/*SW Error*/);
-
- //Add this target to the FFDC
- ERRORLOG::ErrlUserDetailsTarget(o_target,"SCOM Target")
- .addToLog(l_err);
-
- l_err->collectTrace(SCOM_COMP_NAME,1024);
+ case(TARGETING::TYPE_EX):
+ {
+ o_chipUnit = PU_EX_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_MCS):
+ {
+ o_chipUnit = PU_MCS_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_XBUS):
+ {
+ o_chipUnit = PU_XBUS_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_CORE) :
+ {
+ o_chipUnit = PU_C_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_PERV) :
+ {
+ o_chipUnit = PU_PERV_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_EQ) :
+ {
+ o_chipUnit = PU_EQ_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_MCBIST) :
+ {
+ o_chipUnit = PU_MCBIST_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_MCA) :
+ {
+ o_chipUnit = PU_MCA_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_MI) :
+ {
+ o_chipUnit = PU_MI_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_DMI) :
+ {
+ o_chipUnit = PU_DMI_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_OBUS) :
+ {
+ o_chipUnit = PU_OBUS_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_NVBUS) :
+ {
+ o_chipUnit = PU_NVBUS_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_SBE) :
+ {
+ o_chipUnit = PU_SBE_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_PPE) :
+ {
+ o_chipUnit = PU_PPE_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_PEC) :
+ {
+ o_chipUnit = PU_PEC_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_PHB) :
+ {
+ o_chipUnit = PU_PHB_CHIPUNIT;
+ break;
+ }
+ case(TARGETING::TYPE_OCC) :
+ {
+ o_chipUnit = PU_OCC_CHIPUNIT;
+ break;
+ }
+ //Need to add centaur support for Cumulus
+ //@TODO RTC: 139953
+ default:
+ {
+ l_isError = true;
+ break;
+ }
}
- return l_err;
+ return l_isError;
}
} // end namespace
+//@TODO RTC: 139953
+//Need to support centaur chip translations
+// MBA
+// SCOM_TRANS_MBA_MASK = 0xFFFFFFFF7FFFFC00,
+// SCOM_TRANS_MBA_BASEADDR = 0x0000000003010400,
+//
+// SCOM_TRANS_TCM_MBA_MASK = 0xFFFFFFFFFFFFFC00
+// SCOM_TRANS_TCM_MBA_BASEADDR = 0x0000000003010800
+//
+// In the XML.. the
+// <default>physical:sys-0/node-0/membuf-10/mbs-0/mba-1</default>
+//
+// Assuming the MBA we are accessing is under the Centaur
+// not the processor.. for now.
+//
+// 0x00000000_03010400 MBA 0 # MBA01
+// 0x00000000_03010C00 MBA 1 # MBA23
+
+// 0x00000000_03010880 MBA 0 # Trace for MBA01
+// 0x00000000_030110C0 MBA 1 # Trace for MBA23
+
+// 0x00000000_03011400 MBA 0 # DPHY01 (indirect addressing)
+// 0x00000000_03011800 MBA 1 # DPHY23 (indirect addressing)
+
+// 0x80000000_0301143f MBA 0 # DPHY01 (indirect addressing)
+// 0x80000000_0301183f MBA 1 # DPHY23 (indirect addressing)
+
+// 0x80000000_0701143f MBA 0 # DPHY01 (indirect addressing)
+// 0x80000000_0701183f MBA 1 # DPHY23 (indirect addressing)
+//
+
+// SCOM_TRANS_IND_MBA_MASK = 0x80000000FFFFFFFF,
+// SCOM_TRANS_IND_MBA_BASEADDR = 0x800000000301143f,
+
+// check to see that the Address is in the correct direct
+// scom MBA address range. \ No newline at end of file
diff --git a/src/usr/scom/scomtrans.H b/src/usr/scom/scomtrans.H
index 54ffc741e..d89874ce1 100644
--- a/src/usr/scom/scomtrans.H
+++ b/src/usr/scom/scomtrans.H
@@ -5,7 +5,9 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* COPYRIGHT International Business Machines Corp. 2011,2014 */
+/* Contributors Listed Below - COPYRIGHT 2012,2016 */
+/* [+] International Business Machines Corp. */
+/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
@@ -24,6 +26,7 @@
#define __SCOMTRANS_H
#include <devicefw/driverif.H>
+#include <p9_cu.H>
/** @file scomtrans.H
* @brief Provides the interfaces to perform a SCom
@@ -31,44 +34,8 @@
namespace SCOM
{
-
-
- enum ScomTransMask
- {
- SCOM_TRANS_EX_MASK = 0xFFFFFFFF7F000000,
- SCOM_TRANS_MCS_MASK = 0xFFFFFFFF7FFFFF80,
- SCOM_TRANS_MBA_MASK = 0xFFFFFFFF7FFFFC00,
- SCOM_TRANS_TCM_MBA_MASK = 0xFFFFFFFFFFFFFC00,
- SCOM_TRANS_XBUS_MASK = 0x00000000FFFFFC00,
- SCOM_TRANS_IND_MCS_DMI_MASK = 0x80000060FFFFFFFF,
- SCOM_TRANS_IND_MBA_MASK = 0x80000000FFFFFFFF,
- SCOM_TRANS_ABUS_MASK = 0x00000060FFFFFC00,
- SCOM_TRANS_INDIRECT_MASK = 0x8000000000000000,
- };
-
- enum ScomTransBaseAddr
- {
- SCOM_TRANS_EX_BASEADDR = 0x0000000010000000,
- SCOM_TRANS_MCS_BASEADDR = 0x0000000002011800,
- SCOM_TRANS_MCS_DMI_BASEADDR = 0x0000000002011A00,
- SCOM_TRANS_IND_MCS_BASEADDR = 0x8000006002011A00,
- SCOM_TRANS_MBA_BASEADDR = 0x0000000003010400,
- SCOM_TRANS_TCM_MBA_BASEADDR = 0x0000000003010800,
- SCOM_TRANS_XBUS_BASEADDR = 0x0000000004011000,
- SCOM_TRANS_ABUS_BASEADDR = 0x0000000008010C00,
- SCOM_TRANS_IND_MBA_BASEADDR = 0x800000000301143f,
- SCOM_TRANS_IND_MCS_DMI_BASEADDR = 0x8000006002011A3F,
- SCOM_TRANS_INDIRECT_ADDRESS = 0x8000000000000000,
- };
-
- enum ScomTransOffset
- {
- SCOM_TRANS_TCM_MBA_OFFSET = 0x840,
- };
-
-
/**
- * @brief Performs a SCom Translation of the scom address
+ * @brief Performs translates the scom, handles indirect and does scom
* This function performs the translation and get the
* correct target and continues the scom Operation.
*
@@ -86,51 +53,54 @@ namespace SCOM
* In this function, there's only one argument,
* which is the SCom address value.
*/
-errlHndl_t scomTranslate(DeviceFW::OperationType i_opType,
- TARGETING::Target* i_target,
- void* io_buffer,
- size_t& io_buflen,
- int64_t i_accessType,
- va_list i_args);
+errlHndl_t startScomProcess(DeviceFW::OperationType i_opType,
+ TARGETING::Target* i_target,
+ void* io_buffer,
+ size_t& io_buflen,
+ int64_t i_accessType,
+ va_list i_args);
+/**
+ * @brief Performs a SCom Translation of the scom address
+ * This function performs the translation and gets the
+ * correct target.
+ *
+ * @param[in] i_target SCom target
+ * @param[in|out] io_addr SCom address
+ * @param[in|out] io_target_SW target for SW
+ * @return errlHndl_t
+ */
+errlHndl_t scomTranslate(TARGETING::Target * &i_target,
+ uint64_t & io_addr,
+ TARGETING::Target * io_target_SW);
/**
- * @brief Utility function does the address translation for
- * unit types that have similar unit identifying strategy
+ * @brief This function translates a scom address using the
+ * the interface that the HW team provided.
*
- * @param[in] i_epath entity path is passed in
- * @param[in] i_ctype Current targets target type
- * @param[in] i_ptype Target type of the parent
- * @param[in] i_shift Number of bits the instance needs to shift
- * @param[in] i_mask Mask value
- * @param[in|out] o_target SCom target is passed in and after
- * translation return a scomable target
- * @param[in|out} i_addr Address passed in and return as a
- * translated address
- * @return errlHndl_t
+ * @param[in] i_target SCom target is passed in
+ * @param[in] i_type Type of the target
+ * @param[in|out] io_addr Address to be translated
+ * @param[in|out] io_target_SW SW target for HBRT
+ * @return errlHndl_t
*/
-errlHndl_t scomPerformTranslate(TARGETING::EntityPath i_epath,
- TARGETING::TYPE i_ctype,
- TARGETING::TYPE i_ptype,
- int i_shift,
- uint64_t i_mask,
- TARGETING::Target * &o_target,
- uint64_t &i_addr );
+errlHndl_t p9_translation (TARGETING::Target * &i_target,
+ TARGETING::TYPE i_type,
+ uint64_t &io_addr,
+ TARGETING::Target * io_target_SW);
/**
- * @brief This function finds the parent target type and returns
- * that as the new target
+ * @brief This function translates a scom address using the
+ * the interface that the HW team provided.
*
- * @param[in] i_epath SCom target is passed in and return
- * the parent type requested
- * @param[in] i_ptype Target type needed for the parent requested
- * @param[in|out] o_target SCom target is passed in and after
- * translation return a parent target
- * @return errlHndl_t
+ * @param[in] i_type Type of the target
+ * @param[out] o_chipUnit Chip unit related to target type
+ * @return bool True if there was an error trying to find
+ * a chipUnit related to the inputed target type
*/
-errlHndl_t scomfindParentTarget( TARGETING::EntityPath i_epath,
- TARGETING::TYPE i_ptype,
- TARGETING::Target * &o_target);
+bool getChipUnit (TARGETING::TYPE i_type,
+ p9ChipUnits_t &o_chipUnit);
+
}; // End namespace
diff --git a/src/usr/scom/test/scomtest.H b/src/usr/scom/test/scomtest.H
index 52170a065..ee429175e 100644
--- a/src/usr/scom/test/scomtest.H
+++ b/src/usr/scom/test/scomtest.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2011,2015 */
+/* Contributors Listed Below - COPYRIGHT 2011,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -44,7 +44,12 @@
extern trace_desc_t* g_trac_scom;
-
+namespace SCOM
+{
+extern errlHndl_t scomTranslate(TARGETING::Target* &i_target,
+ uint64_t &io_addr,
+ TARGETING::Target* io_target_SW);
+}
class ScomTest: public CxxTest::TestSuite
{
public:
@@ -64,7 +69,6 @@ public:
// Setup some targets to use
enum {
- PROCWRAP,
PROC1,
NUM_TARGETS
};
@@ -74,15 +78,10 @@ public:
scom_targets[x] = NULL;
}
- // Target Proc 9 - the FSI wrap-back connection in simics
+ // processor target (physical:sys-0/node-0/proc-1)
TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
epath.addLast(TARGETING::TYPE_SYS,0);
epath.addLast(TARGETING::TYPE_NODE,0);
- epath.addLast(TARGETING::TYPE_PROC,9);
- scom_targets[PROCWRAP] = TARGETING::targetService().toTarget(epath);
-
- // other processor target (physical:sys-0/node-0/proc-1)
- epath.removeLast();
epath.addLast(TARGETING::TYPE_PROC,1);
scom_targets[PROC1] = TARGETING::targetService().toTarget(epath);
@@ -121,12 +120,8 @@ public:
uint64_t addr;
uint64_t data;
} test_data[] = {
- { scom_targets[PROCWRAP], 0x120F0000 ,0xFEEDB0B000001234},
- { scom_targets[PROCWRAP], 0x120F0166, 0xFEDCBA9876543210},
- { scom_targets[PROCWRAP], 0x01010803, 0x0000000000000000},
- { scom_targets[PROCWRAP], 0x02040004, 0xFFFFFFFFFFFFFFFF},
- { scom_targets[PROC1], 0x01010803, 0x1234567887654321},
- { scom_targets[PROC1], 0x02040004, 0x1122334455667788},
+ { scom_targets[PROC1], 0x040110C4, 0x1234567887654321},
+ { scom_targets[PROC1], 0x02040008, 0x1122334455667788},
};
const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
@@ -387,1291 +382,557 @@ public:
* @brief SCOM test Indirect SCOM
*
*/
-
- void test_IndirectScom(void)
- {
- TRACFCOMP( g_trac_scom, "ScomTest::test_IndirectScomReadWrite> Start" );
-
- uint64_t fails = 0;
- uint64_t total = 0;
- errlHndl_t l_err = NULL;
-
- //@VBU workaround - Disable Indirect SCOM test case o
- //Test case read/writes to valid addresses and is
- //potentially destructive on VBU
- if (TARGETING::is_vpo())
- {
- return;
- }
-
- // Setup some targets to use
- enum {
- myPROC0,
- NUM_TARGETS
- };
- TARGETING::Target* scom_targets[NUM_TARGETS];
- for( uint64_t x = 0; x < NUM_TARGETS; x++ )
- {
- scom_targets[x] = NULL;
- }
-
-
- // Target Proc 9 - the FSI wrap-back connection in simics
- TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
- epath.addLast(TARGETING::TYPE_SYS,0);
- epath.addLast(TARGETING::TYPE_NODE,0);
- epath.addLast(TARGETING::TYPE_PROC,0);
-
- scom_targets[myPROC0] = TARGETING::targetService().toTarget(epath);
-
- for( uint64_t x = 0; x < NUM_TARGETS; x++ )
- {
- //only run if the target exists
- if(scom_targets[x] == NULL)
- {
- TRACDCOMP( g_trac_scom, "ScomTest - TARGET = NULL - 1 x = %d", x);
- continue;
- }
- else if ((scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
- (scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
- {
- // If both FSI and XSCOM are not enabled.. then ignore..
- TRACDCOMP(g_trac_scom, "INDIRECT SCOM>> SKIPPING ");
- scom_targets[x] = NULL; //remove from our list
- }
- else if (scom_targets[x]->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Target %d is not functional", x );
- scom_targets[x] = NULL; //remove from our list
- }
-
-
- }
-
- // scratch data to use
- //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid
- // corrupting the HW.
-
- struct {
- TARGETING::Target* target;
- uint64_t addr;
- uint64_t data;
- } test_data[] = {
- { scom_targets[myPROC0], 0x8000F06002011E3F ,0x1234432112344321},
- { scom_targets[myPROC0], 0x8000086002011E3F, 0x123443211234ABAB},
- };
- const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
-
-
- size_t op_size = sizeof(uint32_t);
-
- // write all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceWrite( test_data[x].target,
- &(test_data[x].data),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
- if( l_err )
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_IndirectScom_proc> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_IndirectScom_proc> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- }
- }
-
- // allocate space for read data
- uint64_t read_data[NUM_ADDRS];
-
- memset(read_data, 0, sizeof read_data);
-
- // read all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceRead( test_data[x].target,
- &(read_data[x]),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
-
- if( l_err )
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_IndirectScomreadWrite_proc> [%d] Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_IndirectScomreadWrite_proc> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- }
- else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF))
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_IndirectScomreadWrite_proc> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
- TS_FAIL( "ScomTest::test_IndirectScomreadWrite_proc> ERROR : Data miss-match between read and expected data" );
- fails++;
- }
-
- }
-
- TRACFCOMP( g_trac_scom, "ScomTest::test_IndirectScomreadWrite_proc> %d/%d fails", fails, total );
-
- }
-
-
-
-
-
- void test_TranslateScom_EX(void)
- {
-
- TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom> Start" );
-
- uint64_t fails = 0;
- uint64_t total = 0;
- errlHndl_t l_err = NULL;
-
-
- //@VBU workaround - Disable Indirect SCOM test case o
- //Test case read/writes to valid addresses and is
- //potentially destructive on VBU
- if (TARGETING::is_vpo())
- {
- return;
- }
-
- // Setup some targets to use
- enum {
- myProc0,
- myEX1,
- myEX5,
- NUM_TARGETS
- };
-
- TARGETING::Target* scom_targets[NUM_TARGETS];
- for( uint64_t x = 0; x < NUM_TARGETS; x++ )
- {
- scom_targets[x] = NULL;
- }
-
- // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes
- TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
- epath.addLast(TARGETING::TYPE_SYS,0);
- epath.addLast(TARGETING::TYPE_NODE,0);
- epath.addLast(TARGETING::TYPE_PROC,0);
-
- scom_targets[myProc0] = TARGETING::targetService().toTarget(epath);
-
- // Only check the Proc or Membuf targets to look at the SCOM attributes
- if ((scom_targets[myProc0] != NULL) &&
- (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
- (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
- {
- // If both FSI and XSCOM are not enabled.. then ignore..
- TRACDCOMP(g_trac_scom, "TRANSLATE SCOM>> SKIPPING ");
- scom_targets[myProc0] = NULL; //remove from our list
- }
-
-
- if (scom_targets[myProc0] != NULL)
- {
- // Add the Ex1 to the path and create new target
- epath.addLast(TARGETING::TYPE_EX,1);
- scom_targets[myEX1] = TARGETING::targetService().toTarget(epath);
-
- // remote EX1 target (off of sys-0/node-0/proc-0/EX1)
- epath.removeLast();
-
- // add EX5 target.
- epath.addLast(TARGETING::TYPE_EX,5);
- scom_targets[myEX5] = TARGETING::targetService().toTarget(epath);
- }
- // scratch data to use
- //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid
- // corrupting the HW.
-
- struct {
- TARGETING::Target* target;
- uint64_t addr;
- uint64_t data;
- } test_data[] = {
- { scom_targets[myEX1], 0x10040000 ,0x7676767676767676},
- { scom_targets[myEX5], 0x10040002, 0x9191919191919191},
- { scom_targets[myEX5], 0x13040002, 0xabcdabcdabcdabcd}, // invalid unit 0 address
- { scom_targets[myEX1], 0x000F0166, 0xabcdabcdabcdabcd}, // invalid address range for target
- };
- const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
-
- size_t op_size = sizeof(uint32_t);
-
- // write all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
- // check to see if the target is functional.. if not.. skip this target
- else if (test_data[x].target->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_EX> Target %d is not functional", x );
- continue;
- }
-
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceWrite( test_data[x].target,
- &(test_data[x].data),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
- if( l_err )
- {
- // last 2 writes have expected failure conditions.
- if ((x == NUM_ADDRS-1) || (x == NUM_ADDRS-2))
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate_EX.. Expected Error log returned> " );
- }
- else
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_translate_scom_EX> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_translate_EX> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- }
-
- delete l_err;
- }
- }
-
- // allocate space for read data
- uint64_t read_data[NUM_ADDRS];
-
- memset(read_data, 0, sizeof (read_data));
-
-
- // read all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS-2; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceRead( test_data[x].target,
- &(read_data[x]),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
-
- if( l_err )
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_translate_scom_EX> [%d] Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_translate_scom_EX> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- }
- else if((read_data[x]) != (test_data[x].data))
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_translate_scom_EX> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
- TS_FAIL( "ScomTest::test_translate_scom_EX> ERROR : Data miss-match between read and expected data" );
- fails++;
- }
-
- }
-
- TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_EX> %d/%d fails", fails, total );
-
- }
-
-
- void test_TranslateScom_MCS(void)
- {
-
- TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom_MCS Start" );
- errlHndl_t l_err = NULL;
-
- uint64_t fails = 0;
- uint64_t total = 0;
-
-
-
- //@VBU workaround - Disable Indirect SCOM test case o
- //Test case read/writes to valid addresses and is
- //potentially destructive on VBU
- if (TARGETING::is_vpo())
- {
- return;
- }
-
- // Setup some targets to use
- enum {
- myProc0,
- myMCS1,
- myMCS2,
- myMCS7,
- myMCS4,
- NUM_TARGETS
- };
-
- TARGETING::Target* scom_targets[NUM_TARGETS];
- for( uint64_t x = 0; x < NUM_TARGETS; x++ )
- {
- scom_targets[x] = NULL;
- }
-
- // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes
- TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
- epath.addLast(TARGETING::TYPE_SYS,0);
- epath.addLast(TARGETING::TYPE_NODE,0);
- epath.addLast(TARGETING::TYPE_PROC,0);
-
- scom_targets[myProc0] = TARGETING::targetService().toTarget(epath);
-
- // Only check the Proc or Membuf targets to look at the SCOM attributes
- if ((scom_targets[myProc0] != NULL) &&
- (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
- (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
- {
- // If both FSI and XSCOM are not enabled.. then ignore..
- TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_MCS>> SKIPPING ");
- scom_targets[myProc0] = NULL; //remove from our list
- }
-
-
- if (scom_targets[myProc0] != NULL)
- {
- // Add the MCS(1) to the path and create new target
- epath.addLast(TARGETING::TYPE_MCS,1);
- scom_targets[myMCS1] = TARGETING::targetService().toTarget(epath);
-
- // remote MCS(1) (off of sys-0/node-0/proc-0/MCS1)
- epath.removeLast();
-
- // add MCS4 target.
- epath.addLast(TARGETING::TYPE_MCS,4);
- scom_targets[myMCS4] = TARGETING::targetService().toTarget(epath);
-
- // remote MCS4 target (off of sys-0/node-0/proc-0/MCS4)
- epath.removeLast();
-
- // add MCS2 target.
- epath.addLast(TARGETING::TYPE_MCS,2);
- scom_targets[myMCS2] = TARGETING::targetService().toTarget(epath);
-
- // remove MCS2 target (off of sys-0/node-0/proc-0/MCS4)
- epath.removeLast();
-
- // add MCS7 target.
- epath.addLast(TARGETING::TYPE_MCS,7);
- scom_targets[myMCS7] = TARGETING::targetService().toTarget(epath);
- }
-
- // scratch data to use
- //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid
- // corrupting the HW.
- struct {
- TARGETING::Target* target;
- uint64_t addr;
- uint64_t data;
- } test_data[] = {
- { scom_targets[myMCS1], 0x0201184A ,0x1111111122222222},
- { scom_targets[myMCS4], 0x0201184A, 0x3333333344444444},
- { scom_targets[myMCS2], 0x0201184A, 0x5555555566666666},
- { scom_targets[myMCS7], 0x0201184A, 0x7777777788888888},
- { scom_targets[myMCS4], 0x0601184A, 0x0101010101010101}, // invalid address range
- { scom_targets[myMCS4], 0x0200184A, 0x2323232323232323}, // Invalid address range for target
- };
- const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
-
- size_t op_size = sizeof(uint32_t);
-
- // write all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
- // check to see if the target is functional.. if not.. skip this target
- else if (test_data[x].target->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_MCS> Target %d is not functional", x );
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceWrite( test_data[x].target,
- &(test_data[x].data),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
- if( l_err )
- {
- if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2))
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS.. Expected Error log returned> x = %d", x );
- }
- else
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MCS> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_Translate_SCOM_mcs> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- }
-
- delete l_err;
- }
- }
-
- // allocate space for read data
- uint64_t read_data[NUM_ADDRS];
-
- memset(read_data, 0, sizeof read_data);
-
- // read all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS-2; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceRead( test_data[x].target,
- &(read_data[x]),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
-
- if( l_err )
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MCS> [%d] Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_TranslateScom_MCS> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- }
- else if((read_data[x]) != (test_data[x].data))
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MCS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
-
- //temp workaround for MCSs that have been turned off (RTC Issue 84907)
- if (read_data[x] != 0x0)
- {
- TS_FAIL( "ScomTest::test_TranslateScom_MCS> ERROR : Data miss-match between read and expected data" );
- fails++;
- }
- }
-
- }
-
- TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_MCS> %d/%d fails", fails, total );
-
- }
-
-
- void test_TranslateScom_MCS_DMI(void)
+// @TODO RTC 142928 Enable Indirect Scoms in Simics
+// void _test_IndirectScom(void)
+// {
+// TRACFCOMP( g_trac_scom, "ScomTest::test_IndirectScomReadWrite> Start" );
+//
+// uint64_t fails = 0;
+// uint64_t total = 0;
+// errlHndl_t l_err = NULL;
+//
+// //@VBU workaround - Disable Indirect SCOM test case o
+// //Test case read/writes to valid addresses and is
+// //potentially destructive on VBU
+// if (TARGETING::is_vpo())
+// {
+// return;
+// }
+//
+// // Setup some targets to use
+// enum {
+// myPROC0,
+// NUM_TARGETS
+// };
+// TARGETING::Target* scom_targets[NUM_TARGETS];
+// for( uint64_t x = 0; x < NUM_TARGETS; x++ )
+// {
+// scom_targets[x] = NULL;
+// }
+//
+//
+// // Target Proc 9 - the FSI wrap-back connection in simics
+// TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
+// epath.addLast(TARGETING::TYPE_SYS,0);
+// epath.addLast(TARGETING::TYPE_NODE,0);
+// epath.addLast(TARGETING::TYPE_PROC,0);
+//
+// scom_targets[myPROC0] = TARGETING::targetService().toTarget(epath);
+//
+// for( uint64_t x = 0; x < NUM_TARGETS; x++ )
+// {
+// //only run if the target exists
+// if(scom_targets[x] == NULL)
+// {
+// TRACDCOMP( g_trac_scom, "ScomTest - TARGET = NULL - 1 x = %d", x);
+// continue;
+// }
+// else if ((scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
+// (scom_targets[x]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
+// {
+// // If both FSI and XSCOM are not enabled.. then ignore..
+// TRACDCOMP(g_trac_scom, "INDIRECT SCOM>> SKIPPING ");
+// scom_targets[x] = NULL; //remove from our list
+// }
+// else if (scom_targets[x]->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
+// {
+// TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_centaur> Target %d is not functional", x );
+// scom_targets[x] = NULL; //remove from our list
+// }
+//
+//
+// }
+//
+// // scratch data to use
+// //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid
+// // corrupting the HW.
+//
+// struct {
+// TARGETING::Target* target;
+// uint64_t addr;
+// uint64_t data;
+// } test_data[] = {
+// { scom_targets[myPROC0], 0x8000F06002011E3F ,0x1234432112344321},
+// { scom_targets[myPROC0], 0x8000086002011E3F, 0x123443211234ABAB},
+// };
+// const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
+//
+//
+// size_t op_size = sizeof(uint32_t);
+//
+// // write all the test registers
+// for( uint64_t x = 0; x < NUM_ADDRS; x++ )
+// {
+// //only run if the target exists
+// if(test_data[x].target == NULL)
+// {
+// continue;
+// }
+//
+// op_size = sizeof(uint64_t);
+//
+// total++;
+// l_err = deviceWrite( test_data[x].target,
+// &(test_data[x].data),
+// op_size,
+// DEVICE_SCOM_ADDRESS(test_data[x].addr) );
+// if( l_err )
+// {
+// TRACFCOMP(g_trac_scom, "ScomTest::test_IndirectScom_proc> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
+// TS_FAIL( "ScomTest::test_IndirectScom_proc> ERROR : Unexpected error log from write1" );
+// fails++;
+// errlCommit(l_err,SCOM_COMP_ID);
+// }
+// }
+//
+// // allocate space for read data
+// uint64_t read_data[NUM_ADDRS];
+//
+// memset(read_data, 0, sizeof read_data);
+//
+// // read all the test registers
+// for( uint64_t x = 0; x < NUM_ADDRS; x++ )
+// {
+// //only run if the target exists
+// if(test_data[x].target == NULL)
+// {
+// continue;
+// }
+//
+// op_size = sizeof(uint64_t);
+//
+// total++;
+// l_err = deviceRead( test_data[x].target,
+// &(read_data[x]),
+// op_size,
+// DEVICE_SCOM_ADDRESS(test_data[x].addr) );
+//
+// if( l_err )
+// {
+// TRACFCOMP(g_trac_scom, "ScomTest::test_IndirectScomreadWrite_proc> [%d] Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
+// TS_FAIL( "ScomTest::test_IndirectScomreadWrite_proc> ERROR : Unexpected error log from write1" );
+// fails++;
+// errlCommit(l_err,SCOM_COMP_ID);
+// }
+// else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF))
+// {
+// TRACFCOMP(g_trac_scom, "ScomTest::test_IndirectScomreadWrite_proc> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
+// TS_FAIL( "ScomTest::test_IndirectScomreadWrite_proc> ERROR : Data miss-match between read and expected data" );
+// fails++;
+// }
+//
+// }
+//
+// TRACFCOMP( g_trac_scom, "ScomTest::test_IndirectScomreadWrite_proc> %d/%d fails", fails, total );
+//
+// }
+
+
+ //@TODO RTC: 131502
+ //write tests to verify connection between XSCOM and FSISCOM
+ //write error path testcase for FSI scom using bad address
+
+ void test_P9_ScomTranslations(void)
{
+ TRACFCOMP( g_trac_scom, "ScomTest::test_P9_ScomTranslations> Start" );
+
+ uint64_t fails = 0;
+ uint64_t total = 0;
+ errlHndl_t l_err = NULL;
+
+ // Setup some targets to use
+ enum {
+ myEX0,
+ myEX1,
+ myCORE0,
+ myCORE1,
+ myEQ0,
+ myEQ5,
+ myMCS0,
+ myMCS3,
+ myXBUS1,
+ myMCBIST0,
+ myMCBIST1,
+ myMCA0,
+ myMCA1,
+ myPERV1,
+ myPERV32,
+ myPEC0,
+ myPEC1,
+ myPHB0,
+ myPHB5,
+ myOBUS0,
+ myOBUS3,
+ myNVBUS0,
+ myNVBUS1,
+ myPPE0,
+ myPPE1,
+ myOCC0,
+ myOCC1,
+ mySBE0,
+ mySBE1,
+ NUM_TARGETS
+ };
+
+
+ TARGETING::Target* scom_targets[NUM_TARGETS];
+ for( uint64_t x = 0; x < NUM_TARGETS; x++ )
+ {
+ scom_targets[x] = NULL;
+ }
+
+
+ /////////////////////////////////////////////////////////////////
+ // Set up targets
+ /////////////////////////////////////////////////////////////////
+
+ // Target Proc 0
+ TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
+ epath.addLast(TARGETING::TYPE_SYS,0);
+ epath.addLast(TARGETING::TYPE_NODE,0);
+ epath.addLast(TARGETING::TYPE_PROC,0);
+
+ epath.addLast(TARGETING::TYPE_EQ,0);
+ scom_targets[myEQ0] = TARGETING::targetService().toTarget(epath);
+
+ //add EX0 target
+ epath.addLast(TARGETING::TYPE_EX,0);
+ scom_targets[myEX0] = TARGETING::targetService().toTarget(epath);
+
+ //add CORE0 target
+ epath.addLast(TARGETING::TYPE_CORE,0);
+ scom_targets[myCORE0] = TARGETING::targetService().toTarget(epath);
+
+ // remove CORE0 target
+ epath.removeLast();
+
+ // add CORE1 target.
+ epath.addLast(TARGETING::TYPE_CORE,1);
+ scom_targets[myCORE1] = TARGETING::targetService().toTarget(epath);
+
+ // remove CORE1 target
+ epath.removeLast();
+
+ // remove EX0 target
+ epath.removeLast();
+
+ // add EX1 target.
+ epath.addLast(TARGETING::TYPE_EX,1);
+ scom_targets[myEX1] = TARGETING::targetService().toTarget(epath);
+
+ // remove EX1 target
+ epath.removeLast();
+
+ // remove EQ0 target
+ epath.removeLast();
+
+ // add EQ5 target.
+ epath.addLast(TARGETING::TYPE_EQ,5);
+ scom_targets[myEQ5] = TARGETING::targetService().toTarget(epath);
+
+ // remove EQ5 target
+ epath.removeLast();
+
+ //add MCS0 target
+ epath.addLast(TARGETING::TYPE_MCS,0);
+ scom_targets[myMCS0] = TARGETING::targetService().toTarget(epath);
+
+ //add MCA0 target
+ epath.addLast(TARGETING::TYPE_MCA,0);
+ scom_targets[myMCA0] = TARGETING::targetService().toTarget(epath);
+
+ // remove MCA0 target
+ epath.removeLast();
+
+ // add MCA1 target.
+ epath.addLast(TARGETING::TYPE_MCA,1);
+ scom_targets[myMCA1] = TARGETING::targetService().toTarget(epath);
- TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom_MCS_DMI Start" );
- errlHndl_t l_err = NULL;
+ // remove MCA1 target
+ epath.removeLast();
- uint64_t fails = 0;
- uint64_t total = 0;
+ // remove MCS0 target
+ epath.removeLast();
+ // add MCS3 target.
+ epath.addLast(TARGETING::TYPE_MCS,3);
+ scom_targets[myMCS3] = TARGETING::targetService().toTarget(epath);
+ // remove MCS3 target
+ epath.removeLast();
- //@VBU workaround - Disable Indirect SCOM test case o
- //Test case read/writes to valid addresses and is
- //potentially destructive on VBU
- if (TARGETING::is_vpo())
- {
- return;
- }
+ //add XBUS1 target
+ epath.addLast(TARGETING::TYPE_XBUS,0);
+ scom_targets[myXBUS1] = TARGETING::targetService().toTarget(epath);
- // Setup some targets to use
- enum {
- myProc0,
- myMCS1,
- myMCS2,
- myMCS7,
- myMCS4,
- NUM_TARGETS
- };
+ // remove XBUS1 target
+ epath.removeLast();
- TARGETING::Target* scom_targets[NUM_TARGETS];
- for( uint64_t x = 0; x < NUM_TARGETS; x++ )
- {
- scom_targets[x] = NULL;
- }
+ //add MCBIST0 target
+ epath.addLast(TARGETING::TYPE_MCBIST,0);
+ scom_targets[myMCBIST0] = TARGETING::targetService().toTarget(epath);
- // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes
- TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
- epath.addLast(TARGETING::TYPE_SYS,0);
- epath.addLast(TARGETING::TYPE_NODE,0);
- epath.addLast(TARGETING::TYPE_PROC,0);
+ // remove MCBIST0 target
+ epath.removeLast();
- scom_targets[myProc0] = TARGETING::targetService().toTarget(epath);
+ // add MCBIST1 target.
+ epath.addLast(TARGETING::TYPE_MCBIST,1);
+ scom_targets[myMCBIST1] = TARGETING::targetService().toTarget(epath);
- // Only check the Proc or Membuf targets to look at the SCOM attributes
- if ((scom_targets[myProc0] != NULL) &&
- (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
- (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
- {
- // If both FSI and XSCOM are not enabled.. then ignore..
- TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_MCS_DMI>> SKIPPING ");
- scom_targets[myProc0] = NULL; //remove from our list
- }
+ // remove MCBIST1 target
+ epath.removeLast();
+ //add PERV1 target
+ epath.addLast(TARGETING::TYPE_PERV,1);
+ scom_targets[myPERV1] = TARGETING::targetService().toTarget(epath);
- if (scom_targets[myProc0] != NULL)
- {
- // Add the MCS(1) to the path and create new target
- epath.addLast(TARGETING::TYPE_MCS,1);
- scom_targets[myMCS1] = TARGETING::targetService().toTarget(epath);
+ // remove PERV1 target
+ epath.removeLast();
- // remote MCS(1) (off of sys-0/node-0/proc-0/MCS1)
- epath.removeLast();
+ // add PERV32 target.
+ epath.addLast(TARGETING::TYPE_PERV,32);
+ scom_targets[myPERV32] = TARGETING::targetService().toTarget(epath);
- // add MCS4 target.
- epath.addLast(TARGETING::TYPE_MCS,4);
- scom_targets[myMCS4] = TARGETING::targetService().toTarget(epath);
+ // remove PERV32 target
+ epath.removeLast();
- // remote MCS4 target (off of sys-0/node-0/proc-0/MCS4)
- epath.removeLast();
+ //add PEC0 target
+ epath.addLast(TARGETING::TYPE_PEC,0);
+ scom_targets[myPEC0] = TARGETING::targetService().toTarget(epath);
- // add MCS2 target.
- epath.addLast(TARGETING::TYPE_MCS,2);
- scom_targets[myMCS2] = TARGETING::targetService().toTarget(epath);
+ //add PHB0 target
+ epath.addLast(TARGETING::TYPE_PHB,0);
+ scom_targets[myPHB0] = TARGETING::targetService().toTarget(epath);
- // remove MCS2 target (off of sys-0/node-0/proc-0/MCS4)
- epath.removeLast();
+ // remove PHB0 target
+ epath.removeLast();
- // add MCS7 target.
- epath.addLast(TARGETING::TYPE_MCS,7);
- scom_targets[myMCS7] = TARGETING::targetService().toTarget(epath);
- }
+ // add PHB5 target.
+ epath.addLast(TARGETING::TYPE_PHB,5);
+ scom_targets[myPHB5] = TARGETING::targetService().toTarget(epath);
- // scratch data to use
- //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid
- // corrupting the HW.
- struct {
- TARGETING::Target* target;
- uint64_t addr;
- uint64_t data;
- } test_data[] = {
- { scom_targets[myMCS1], 0x800EAC6002011A3F ,0x1111111122222222},
- { scom_targets[myMCS4], 0x800EAC6002011A3F, 0x3333333344444444},
- { scom_targets[myMCS2], 0x800EAC6002011A3F, 0x5555555566666666},
- { scom_targets[myMCS7], 0x800EAC6002011A3F, 0x7777777788888888},
- { scom_targets[myMCS4], 0x800EAC0002011A3F, 0x0101010101010101}, // invalid address range
- { scom_targets[myMCS4], 0x800EAC4002011E3F, 0x2323232323232323}, // Invalid address range for target
- };
- const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
+ // remove PHB5 target
+ epath.removeLast();
- size_t op_size = sizeof(uint32_t);
+ // remove PEC0 target
+ epath.removeLast();
- // write all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
-
- // check to see if the target is functional.. if not.. skip this target
- else if (test_data[x].target->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_MCS_DMI> Target %d is not functional", x );
- continue;
- }
-
- op_size = sizeof(uint64_t);
+ // add PEC1 target.
+ epath.addLast(TARGETING::TYPE_PEC,1);
+ scom_targets[myPEC1] = TARGETING::targetService().toTarget(epath);
- total++;
- l_err = deviceWrite( test_data[x].target,
- &(test_data[x].data),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
- if( l_err )
- {
- if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2))
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate MCS_DMI.. Expected Error log returned> x = %d", x );
- }
- else
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MCS_DMI> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_Translate_SCOM_mcs_DMI> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- }
-
- delete l_err;
- }
- }
-
- // allocate space for read data
- uint64_t read_data[NUM_ADDRS];
-
- memset(read_data, 0, sizeof read_data);
-
- // read all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS-2; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceRead( test_data[x].target,
- &(read_data[x]),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
-
- if( l_err )
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MCS_DMI> [%d] Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_TranslateScom_MCS_DMI> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- delete l_err;
- }
- else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF))
- // else if((read_data[x]) != (test_data[x].data))
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MCS_DMI> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
- //temp workaround for MCSs that have been turned off (RTC Issue 84907)
- if (read_data[x] != 0x0)
- {
- TS_FAIL( "ScomTest::test_TranslateScom_MCS_DMI> ERROR : Data miss-match between read and expected data" );
- fails++;
- }
- }
-
- }
-
- TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_MCS_DMI> %d/%d fails", fails, total );
-
- }
-
- void test_TranslateScom_MBA_MBS(void)
- {
- TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom_MBA_MBS Start" );
-
- uint64_t fails = 0;
- uint64_t total = 0;
- errlHndl_t l_err = NULL;
-
- //@VBU workaround - Disable Indirect SCOM test case o
- //Test case read/writes to valid addresses and is
- //potentially destructive on VBU
- if (TARGETING::is_vpo())
- {
- return;
- }
-
- // Setup some targets to use
- enum {
- myMembuf0,
- myMBA0,
- myMBA1,
- NUM_TARGETS
- };
-
-
- TARGETING::Target* scom_targets[NUM_TARGETS];
- for( uint64_t x = 0; x < NUM_TARGETS; x++ )
- {
- scom_targets[x] = NULL;
- }
-
- // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes
- TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
- epath.addLast(TARGETING::TYPE_SYS,0);
- epath.addLast(TARGETING::TYPE_NODE,0);
- epath.addLast(TARGETING::TYPE_MEMBUF,0);
-
- scom_targets[myMembuf0] = TARGETING::targetService().toTarget(epath);
-
- if ( (scom_targets[myMembuf0] != NULL) &&
- (scom_targets[myMembuf0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
- (scom_targets[myMembuf0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
- {
- // If both FSI and XSCOM are not enabled.. then ignore..
- TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_MBA_MBS>> SKIPPING ");
- scom_targets[myMembuf0] = NULL; //remove from our list
- }
-
- if(scom_targets[myMembuf0] != NULL)
- {
-
- // add MBA0 target.
- epath.addLast(TARGETING::TYPE_MBA,0);
- scom_targets[myMBA0] = TARGETING::targetService().toTarget(epath);
-
- // remote MBA0 target (off of sys-0/node-0/membuf-0/MBA0)
- epath.removeLast();
-
- // Add MBA1 to the path and create new target
- epath.addLast(TARGETING::TYPE_MBA,1);
- scom_targets[myMBA1] = TARGETING::targetService().toTarget(epath);
- }
- // scratch data to use
- //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid
- // corrupting the HW.
- struct {
- TARGETING::Target* target;
- uint64_t addr;
- uint64_t data;
- } test_data[] = {
- { scom_targets[myMBA0], 0x03010655 ,0x111111111111DDDD},
- { scom_targets[myMBA1], 0x03010655, 0x333333334444EEEE},
- { scom_targets[myMBA0], 0x8000C0140301143F,0x1111111111111212},
- { scom_targets[myMBA1], 0x8000C0140301143F, 0x333333334444abcd},
- { scom_targets[myMBA0], 0x8000C0140301183F,0x111111111111ccee}, // invalid non zero indirect address
- { scom_targets[myMBA0], 0x03010E55, 0x010101010101CCCC}, // invalid passing in a non-0 unit address
- };
- const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
-
- size_t op_size = sizeof(uint32_t);
-
- // write all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS; x++ )
+ // remove PEC1 target
+ epath.removeLast();
+
+ //add OBUS0 target
+ epath.addLast(TARGETING::TYPE_OBUS,0);
+ scom_targets[myOBUS0] = TARGETING::targetService().toTarget(epath);
+
+ // remove OBUS0 target
+ epath.removeLast();
+
+ // add OBUS3 target.
+ epath.addLast(TARGETING::TYPE_OBUS,3);
+ scom_targets[myOBUS3] = TARGETING::targetService().toTarget(epath);
+
+ // remove OBUS3 target
+ epath.removeLast();
+
+ //add NVBUS0 target
+ epath.addLast(TARGETING::TYPE_NVBUS,0);
+ scom_targets[myNVBUS0] = TARGETING::targetService().toTarget(epath);
+
+ // remove NVBUS0 target
+ epath.removeLast();
+
+ // add NVBUS1 target.
+ epath.addLast(TARGETING::TYPE_NVBUS,1);
+ scom_targets[myNVBUS1] = TARGETING::targetService().toTarget(epath);
+
+ // remove NVBUS1 target
+ epath.removeLast();
+
+ //add PPE0 target
+ epath.addLast(TARGETING::TYPE_PPE,0);
+ scom_targets[myPPE0] = TARGETING::targetService().toTarget(epath);
+
+ // remove PPE0 target
+ epath.removeLast();
+
+ // add PPE1 target.
+ epath.addLast(TARGETING::TYPE_PPE,1);
+ scom_targets[myPPE1] = TARGETING::targetService().toTarget(epath);
+
+ // remove PPE1 target
+ epath.removeLast();
+
+ //add OCC0 target
+ epath.addLast(TARGETING::TYPE_OCC,0);
+ scom_targets[myOCC0] = TARGETING::targetService().toTarget(epath);
+
+ // remove OCC0 target
+ epath.removeLast();
+
+ // add OCC1 target.
+ epath.addLast(TARGETING::TYPE_OCC,1);
+ scom_targets[myOCC1] = TARGETING::targetService().toTarget(epath);
+
+ // remove OCC1 target
+ epath.removeLast();
+
+ //add SBE0 target
+ epath.addLast(TARGETING::TYPE_SBE,0);
+ scom_targets[mySBE0] = TARGETING::targetService().toTarget(epath);
+
+ // remove SBE0 target
+ epath.removeLast();
+
+ // add SBE1 target.
+ epath.addLast(TARGETING::TYPE_SBE,1);
+ scom_targets[mySBE1] = TARGETING::targetService().toTarget(epath);
+
+ // remove SBE1 target
+ epath.removeLast();
+
+ struct {
+ TARGETING::Target* target;
+ uint64_t initAddr;
+ uint64_t expectedAddr;
+ bool expectError;
+ } test_data[] = {
+ //Target Address Expected error
+ { scom_targets[myEX0], 0x21000000 , 0x21000000, false},
+ { scom_targets[myEX0], 0x0FFFFFFF, 0x0FFFFFFF, true},
+ { scom_targets[myEX1], 0x21000000, 0x23000000, false},
+ { scom_targets[myEX1], 0x0FFFFFFF, 0x0FFFFFFF ,true},
+ { scom_targets[myEX1], 0x10012400, 0x10012800, false},
+ { scom_targets[myCORE0], 0x20010A46, 0x20010A46, false},
+ { scom_targets[myCORE0], 0x0FFFFFFF, 0x0FFFFFFF, true},
+ { scom_targets[myCORE1], 0x20010A46, 0x21010A46, false},
+ { scom_targets[myCORE1], 0x0FFFFFFF, 0x0FFFFFFF ,true},
+ { scom_targets[myCORE0], 0x12012826, 0x12012826, true},
+ { scom_targets[myEQ0], 0x10000008 , 0x10000008, false},
+ { scom_targets[myEQ0], 0x0FFFFFFF, 0x0FFFFFFF, true},
+ { scom_targets[myEQ5], 0x10000008, 0x15000008, false},
+ { scom_targets[myEQ5], 0x0FFFFFFF, 0x0FFFFFFF ,true},
+ { scom_targets[myEQ5], 0x24030008, 0x24030008, true},
+ { scom_targets[myMCS0], 0x05010800 , 0x05010800, false},
+ { scom_targets[myMCS0], 0x0FFFFFFF, 0x0FFFFFFF, true},
+ { scom_targets[myMCS3], 0x05010800, 0x03010880, false},
+ { scom_targets[myMCS3], 0x0FFFFFFF, 0x0FFFFFFF ,true},
+ { scom_targets[myMCS0], 0x12012826, 0x12012826, true},
+ { scom_targets[myMCS3], 0x24030008, 0x24030008, true},
+ { scom_targets[myXBUS1], 0x0FFFFFFFFFFFFFFF , 0x0FFFFFFFFFFFFFFF, true},
+ { scom_targets[myXBUS1], 0x12012826, 0x12012826, true},
+ { scom_targets[myXBUS1], 0x24030008, 0x24030008, true},
+//TODO: RTC 143005 Add MCBIST Targets to scomtest.H
+// { scom_targets[myMCBIST0], 0x07010F15 ,0x07010F15 , false},
+// { scom_targets[myMCBIST0], 0x0FFFFFFF, 0x0FFFFFFF, true},
+// { scom_targets[myMCBIST1], 0x07010F15,0x08010F15 , false},
+// { scom_targets[myMCBIST1], 0x0FFFFFFF, 0x0FFFFFFF ,true},
+// { scom_targets[myMCBIST0], 0x12012826, 0x12012826, true},
+// { scom_targets[myMCBIST1], 0x24030008, 0x24030008, true},
+ { scom_targets[myMCA0], 0x07010915, 0x07010915, false},
+ { scom_targets[myMCA0], 0x0FFFFFFF, 0x0FFFFFFF, true},
+ { scom_targets[myMCA1], 0x07010915, 0x07010955, false},
+ { scom_targets[myMCA1], 0x0FFFFFFF, 0x0FFFFFFF ,true},
+ { scom_targets[myMCA0], 0x12012826, 0x12012826, true},
+ { scom_targets[myMCA1], 0x24030008, 0x24030008, true},
+ { scom_targets[myPERV1], 0x00030009, 0x01030009, false},
+ { scom_targets[myPERV1], 0x0FF6FFFF, 0x0FF6FFFF, true},
+ { scom_targets[myPERV32], 0x00030009, 0x20030009, false},
+ { scom_targets[myPERV32], 0x0FF6FFFF, 0x0FF6FFFF ,true},
+ { scom_targets[myPERV1], 0x07010A0A, 0x32010A0A, true},
+ { scom_targets[myPERV32], 0x0D010400, 0x0D010400, true},
+ { scom_targets[myPEC0], 0x04010C03, 0x04010C03, false},
+ { scom_targets[myPEC1], 0x04010C03, 0x04011003 ,false},
+ { scom_targets[myPEC0], 0x0FFFFFFF, 0x0FFFFFFF, true},
+ { scom_targets[myPEC1], 0x0FFFFFFF, 0x0FFFFFFF ,true},
+ { scom_targets[myPEC0], 0x12012826, 0x12012826, true},
+ { scom_targets[myPEC1], 0x24030008, 0x24030008, true},
+ { scom_targets[myPHB0], 0x04010C4E, 0x04010C4E, false},
+ { scom_targets[myPHB5], 0x04010C4E, 0x04010C4E ,false},
+ { scom_targets[myPHB0], 0x0FFFFFFF, 0x0FFFFFFF, true},
+ { scom_targets[myPHB5], 0x0FFFFFFF, 0x0FFFFFFF ,true},
+ { scom_targets[myPHB0], 0x12012826, 0x12012826, true},
+ { scom_targets[myPHB5], 0x24030008, 0x24030008, true},
+ { scom_targets[myOBUS0], 0x09010C55, 0x09010C55, false},
+ { scom_targets[myOBUS3], 0x09010C55, 0x0C010C55 ,false},
+ { scom_targets[myOBUS0], 0x12012826, 0x12012826, true},
+ { scom_targets[myOBUS3], 0x24030008, 0x24030008, true},
+ { scom_targets[myNVBUS0], 0x050110D4, 0x050110D4, false},
+ { scom_targets[myNVBUS1], 0x050110D4, 0x050110F4,false},
+ { scom_targets[myNVBUS0], 0x12012826, 0x12012826, true},
+ { scom_targets[myNVBUS1], 0x24030008, 0x24030008, true},
+// @TODO RTC 131502 Scom Translation Test Updates
+// SBE TARGETS
+// { scom_targets[mySBE0], 0x000D0060, 0x000D0060, false},
+// { scom_targets[mySBE0], 0x12012826, 0x12012826, true},
+// { scom_targets[mySBE0], 0x24030008, 0x24030008, true},
+// PPE TARGETS
+// { scom_targets[myPPE0], 0x00060010, 0x00060010, false},
+// { scom_targets[myPPE1], 0x00060010, 0x00000000 ,false},
+// { scom_targets[myPPE0], 0x12012826, 0x12012826, true},
+// { scom_targets[myPPE1], 0x24030008, 0x24030008, true},
+// Maybe OCC TARGETS?
+// { scom_targets[myOCC0], 0x0006C070, 0x0006C070, false},
+// { scom_targets[myOCC0], 0x12012826, 0x12012826, true},
+// { scom_targets[myOCC0], 0x24030008, 0x24030008, true},
+ };
+
+ int numOfAddr = sizeof test_data / sizeof(test_data[0]);
+
+ for (int i = 0; i < numOfAddr; i++)
{
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
-
- // check to see if the target is functional.. if not.. skip this target
- else if (test_data[x].target->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_MBA_MBS> Target %d is not functional", x );
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceWrite( test_data[x].target,
- &(test_data[x].data),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
- if( l_err )
- {
- // checking the read of NUM_ADDRs - 1 because the last entry written above failed as expected.
- if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2))
+ if(test_data[i].target != NULL)
+ {
+ total++;
+ uint64_t tempAddr = test_data[i].initAddr;
+ l_err = SCOM::scomTranslate(test_data[i].target,
+ tempAddr,
+ NULL);
+
+ if( l_err && !test_data[i].expectError)
{
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate MBA_MBS.. Expected Errorlog Returned> x = %d", x );
+ TRACFCOMP(g_trac_scom, "ScomTest::test_P9_translate_scom> Write: Error from device : addr=0x%X, HUID 0x%X, RC=%X",
+ test_data[i].initAddr,
+ TARGETING::get_huid(test_data[i].target),
+ l_err->reasonCode() );
+ TS_FAIL( "ScomTest::test_P9_translate> ERROR : Unexpected error log from write1" );
+ fails++;
+ errlCommit(l_err,SCOM_COMP_ID);
+
+ delete l_err;
}
- else
+ else if(l_err == NULL && test_data[i].expectError)
{
- TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_MBA_MBS> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_Translate_SCOM_MBA_MBS> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- }
-
- delete l_err;
- }
- }
-
- // allocate space for read data
- uint64_t read_data[NUM_ADDRS];
-
- // read all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS-2; x++ )
- {
- memset(read_data, 0, sizeof read_data);
-
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
- // check to see if the target is functional.. if not.. skip this target
- else if (test_data[x].target->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_MBA_MBS> Target %d is not functional", x );
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceRead( test_data[x].target,
- &(read_data[x]),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
-
-
- if( l_err )
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MBA_MBS> [%d] Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_TranslateScom_MBA_MBS> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- }
- else if ((x == 2) || (x==3))
- {
- if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF))
-
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_ABUS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
- TS_FAIL( "ScomTest::test_TranslateScom_ABUS> ERROR : Data miss-match between read and expected data" );
- fails++;
- }
- }
- else if((read_data[x]) != (test_data[x].data))
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_MBA_MBS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
- TS_FAIL( "ScomTest::test_TranslateScom_MBA_MBS> ERROR : Data miss-match between read and expected data" );
- fails++;
- }
-
- }
-
- TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_MBA_MBS> %d/%d fails", fails, total );
-
- }
-
-
- void test_TranslateScom_ABUS(void)
-{
-/*
- //FIXME: RTC 129630
- TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom_ABUS Start" );
- errlHndl_t l_err = NULL;
-
- uint64_t fails = 0;
- uint64_t total = 0;
-
- //@VBU workaround - Disable Indirect SCOM test case o
- //Test case read/writes to valid addresses and is
- //potentially destructive on VBU
- if (TARGETING::is_vpo())
- {
- return;
- }
-
- // Setup some targets to use
- enum {
- myProc0,
- myABUS0,
- myABUS1,
- myABUS2,
- NUM_TARGETS
- };
-
- TARGETING::Target* scom_targets[NUM_TARGETS];
- for( uint64_t x = 0; x < NUM_TARGETS; x++ )
- {
- scom_targets[x] = NULL;
- }
-
- // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes
- TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
- epath.addLast(TARGETING::TYPE_SYS,0);
- epath.addLast(TARGETING::TYPE_NODE,0);
- epath.addLast(TARGETING::TYPE_PROC,0);
-
- scom_targets[myProc0] = TARGETING::targetService().toTarget(epath);
-
- // Only check the Proc or Membuf targets to look at the SCOM attributes
- if ((scom_targets[myProc0] != NULL) &&
- (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
- (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
- {
- // If both FSI and XSCOM are not enabled.. then ignore..
- TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_ABUS>> SKIPPING ");
- scom_targets[myProc0] = NULL; //remove from our list
- }
-
-
- if (scom_targets[myProc0] != NULL)
- {
- // Add the ABUS 0 to the path and create new target
- epath.addLast(TARGETING::TYPE_ABUS,0);
- scom_targets[myABUS0] = TARGETING::targetService().toTarget(epath);
-
- // remote ABUS 0 (off of sys-0/node-0/proc-0/ABUS0)
- epath.removeLast();
-
- // add ABUS 1 target.
- epath.addLast(TARGETING::TYPE_ABUS,1);
- scom_targets[myABUS1] = TARGETING::targetService().toTarget(epath);
-
- // remote ABUS1 target (off of sys-0/node-0/proc-0/ABUS1)
- epath.removeLast();
-
- // add ABUS2 target.
- epath.addLast(TARGETING::TYPE_ABUS,2);
- scom_targets[myABUS2] = TARGETING::targetService().toTarget(epath);
-
- }
-
- // scratch data to use
- //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid
- // corrupting the HW.
- struct {
- TARGETING::Target* target;
- uint64_t addr;
- uint64_t data;
- } test_data[] = {
-
- { scom_targets[myABUS0], 0x800C4C0008010C3F ,0x1111111101010101},
- { scom_targets[myABUS1], 0x8000B00108010C3F, 0x3333333311111111},
- { scom_targets[myABUS2], 0x800C4C0008010C3F, 0x5555555521212121},
- { scom_targets[myABUS0], 0x800C4C2008010C3F, 0x0101010101010101}, // invalid address range - non zero
- { scom_targets[myABUS2], 0x800C4C0004010C3F, 0x2323232323232323}, // Invalid address range for target
- };
- const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
-
- size_t op_size = sizeof(uint32_t);
-
- // write all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
-
- // check to see if the target is functional.. if not.. skip this target
- else if (test_data[x].target->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_ABUS> Target %d is not functional", x );
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceWrite( test_data[x].target,
- &(test_data[x].data),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
- if( l_err )
- {
- if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2))
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate ABUS.. Expected Error log returned> x = %d", x );
- }
- else
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_ABUS> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_Translate_SCOM_ABUS> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- }
-
- delete l_err;
- }
- }
-
- // allocate space for read data
- uint64_t read_data[NUM_ADDRS];
-
- memset(read_data, 0, sizeof read_data);
-
- // read all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS-2; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
- // check to see if the target is functional.. if not.. skip this target
- else if (test_data[x].target->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_ABUS> Target %d is not functional", x );
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceRead( test_data[x].target,
- &(read_data[x]),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
-
- if( l_err )
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_ABUS> [%d] Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_TranslateScom_ABUS> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- delete l_err;
- }
- else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF))
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_ABUS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
- TS_FAIL( "ScomTest::test_TranslateScom_ABUS> ERROR : Data miss-match between read and expected data" );
- fails++;
- }
-
- }
-
- TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_ABUS> %d/%d fails", fails, total );
-*/
- }
-
-
- void test_TranslateScom_XBUS(void)
-{
-
- TRACFCOMP( g_trac_scom, "ScomTest::test_TranslateScom_XBUS Start" );
- errlHndl_t l_err = NULL;
-
- uint64_t fails = 0;
- uint64_t total = 0;
-
- //@VBU workaround - Disable Indirect SCOM test case o
- //Test case read/writes to valid addresses and is
- //potentially destructive on VBU
- if (TARGETING::is_vpo())
- {
- return;
- }
-
-
- // Setup some targets to use
- enum {
- myProc0,
- myXBUS0,
- myXBUS1,
- myXBUS2,
- myXBUS3,
- NUM_TARGETS
- };
-
- TARGETING::Target* scom_targets[NUM_TARGETS];
- for( uint64_t x = 0; x < NUM_TARGETS; x++ )
- {
- scom_targets[x] = NULL;
- }
-
- // Target Proc 0 - to make sure we have XSCOM and FSISCOM attributes
- TARGETING::EntityPath epath(TARGETING::EntityPath::PATH_PHYSICAL);
- epath.addLast(TARGETING::TYPE_SYS,0);
- epath.addLast(TARGETING::TYPE_NODE,0);
- epath.addLast(TARGETING::TYPE_PROC,0);
-
- scom_targets[myProc0] = TARGETING::targetService().toTarget(epath);
-
- // Only check the Proc or Membuf targets to look at the SCOM attributes
- if ((scom_targets[myProc0] != NULL) &&
- (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useXscom == 0) &&
- (scom_targets[myProc0]->getAttr<TARGETING::ATTR_SCOM_SWITCHES>().useFsiScom == 0))
- {
- // If both FSI and XSCOM are not enabled.. then ignore..
- TRACDCOMP(g_trac_scom, "TRANSLATE_SCOM_XBUS>> SKIPPING ");
- scom_targets[myProc0] = NULL; //remove from our list
- }
-
-
- if (scom_targets[myProc0] != NULL)
- {
- // Add the XBUS 0 to the path and create new target
- epath.addLast(TARGETING::TYPE_XBUS,0);
- scom_targets[myXBUS0] = TARGETING::targetService().toTarget(epath);
-
- // remove XBUS 0 (off of sys-0/node-0/proc-0/XBUS0)
- epath.removeLast();
-
- // add XBUS 1 target.
- epath.addLast(TARGETING::TYPE_XBUS,1);
- scom_targets[myXBUS1] = TARGETING::targetService().toTarget(epath);
-
- // remove XBUS1 target (off of sys-0/node-0/proc-0/XBUS1)
- epath.removeLast();
-
- // add XBUS2 target.
- epath.addLast(TARGETING::TYPE_XBUS,2);
- scom_targets[myXBUS2] = TARGETING::targetService().toTarget(epath);
-
- // remove XBUS2 target (off of sys-0/node-0/proc-0/XBUS2)
- epath.removeLast();
-
- // add XBUS3 target.
- epath.addLast(TARGETING::TYPE_XBUS,3);
- scom_targets[myXBUS3] = TARGETING::targetService().toTarget(epath);
-
- }
-
- // scratch data to use
- //@fixme: Need to either fabricate some fake registers to use or save off data before modifying SCOMs to avoid
- // corrupting the HW.
- struct {
- TARGETING::Target* target;
- uint64_t addr;
- uint64_t data;
- } test_data[] = {
-
- { scom_targets[myXBUS0], 0x800000200401103F ,0x1111111101010101},
- { scom_targets[myXBUS1], 0x800000200401103F, 0x3333333311111111},
- { scom_targets[myXBUS2], 0x800000200401103F, 0x555555552121aaaa},
- { scom_targets[myXBUS3], 0x800000200401103F, 0x555555552121bbbb},
- { scom_targets[myXBUS0], 0x8000002004011C3F, 0x0101010101010101}, // invalid address range - non zero
- { scom_targets[myXBUS2], 0x800000200401003F, 0x2323232323232323}, // Invalid address range for target
- };
- const uint64_t NUM_ADDRS = sizeof(test_data)/sizeof(test_data[0]);
-
- size_t op_size = sizeof(uint32_t);
-
- // write all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
- // check to see if the target is functional.. if not.. skip this target
- else if (test_data[x].target->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_XBUS> Target %d is not functional", x );
- continue;
- }
- // TODO: engd data for s1 supports XBUS1 only.
- // TODO: RTC 109249, check XBUS for Naples
- // For now check if murano or naples chip and target is not XBUS1, then skip this target.
- // Long term solution would be to change HWAS per RTC 45796.
- else if ( ((scom_targets[myProc0]->getAttr<TARGETING::ATTR_MODEL>() ==
- TARGETING::MODEL_MURANO) && (x != 1)) ||
- ((scom_targets[myProc0]->getAttr<TARGETING::ATTR_MODEL>() ==
- TARGETING::MODEL_NAPLES) && (x != 1)) )
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate_scom_XBUS> Processor is Murano"
- " - skipping Target %d", x );
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceWrite( test_data[x].target,
- &(test_data[x].data),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
- if( l_err )
- {
- if ((x == NUM_ADDRS-1) || (x==NUM_ADDRS-2))
+ TRACFCOMP(g_trac_scom, "ScomTest::test_P9_translate> ERROR : Expected an error and did not recieve one for : addr=0x%X, HUID 0x%X",
+ test_data[i].initAddr,
+ TARGETING::get_huid(test_data[i].target))
+ TS_FAIL( "ScomTest::test_P9_translate> ERROR : Expected an error and did not recieve one" );
+ fails++;
+ }
+ else if(tempAddr!= test_data[i].expectedAddr &&
+ l_err == NULL && !test_data[i].expectError)
{
- TRACDCOMP( g_trac_scom, "ScomTest::test_translate XBUS.. Expected Error log returned> x = %d", x );
+ TRACFCOMP(g_trac_scom, "ScomTest::test_P9_translate_scom> Incorrect translation of: 0x%X produced: 0x%X expected: 0x%X",
+ test_data[i].initAddr, tempAddr, test_data[i].expectedAddr);
+ TS_FAIL( "ScomTest::test_P9_translate> ERROR : Unexpected error log from write1" );
+ fails++;
}
- else
+ else if(l_err && test_data[i].expectError)
{
- TRACFCOMP(g_trac_scom, "ScomTest::test_translate_Scom_XBUS> [%d] Write: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_Translate_SCOM_XBUS> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- }
-
- delete l_err;
- }
- }
-
- // allocate space for read data
- uint64_t read_data[NUM_ADDRS];
-
- memset(read_data, 0, sizeof read_data);
-
- // read all the test registers
- for( uint64_t x = 0; x < NUM_ADDRS-2; x++ )
- {
- //only run if the target exists
- if(test_data[x].target == NULL)
- {
- continue;
- }
- // check to see if the target is functional.. if not.. skip this target
- else if (test_data[x].target->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_TranslateScom_XBUS> Target %d is not functional", x );
- continue;
- }
- // TODO: engd data for s1 supports XBUS1 only.
- // TODO: RTC 109249, check XBUS for Naples
- // For now check if murano chip and target is not XBUS1, then skip this target.
- // Long term solution would be to change HWAS per RTC 45796.
- else if ( ((scom_targets[myProc0]->getAttr<TARGETING::ATTR_MODEL>() ==
- TARGETING::MODEL_MURANO) && (x != 1)) ||
- ((scom_targets[myProc0]->getAttr<TARGETING::ATTR_MODEL>() ==
- TARGETING::MODEL_NAPLES) && (x != 1)) )
- {
- TRACDCOMP( g_trac_scom, "ScomTest::test_TranslateScom_XBUS> Processor is Murano"
- " - skipping Target %d", x );
- continue;
- }
-
- op_size = sizeof(uint64_t);
-
- total++;
- l_err = deviceRead( test_data[x].target,
- &(read_data[x]),
- op_size,
- DEVICE_SCOM_ADDRESS(test_data[x].addr) );
-
- if( l_err )
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_XBUS> [%d] Read: Error from device : addr=0x%X, RC=%X", x, test_data[x].addr, l_err->reasonCode() );
- TS_FAIL( "ScomTest::test_TranslateScom_XBUS> ERROR : Unexpected error log from write1" );
- fails++;
- errlCommit(l_err,SCOM_COMP_ID);
- delete l_err;
- }
- else if((read_data[x] & 0x000000000000FFFF) != (test_data[x].data & 0x000000000000FFFF))
- {
- TRACFCOMP(g_trac_scom, "ScomTest::test_TranslateScom_XBUS> [%d] Read: Data miss-match : addr=0x%X, read_data=0x%llx, write_data=0x%llx", x, test_data[x].addr, read_data[x], test_data[x].data);
- TS_FAIL( "ScomTest::test_TranslateScom_XBUS> ERROR : Data miss-match between read and expected data" );
- fails++;
- }
-
+ delete l_err;
+ TRACFCOMP(g_trac_scom, "ScomTest::test_P9_translate_scom> Previous error expected");
+ }
+ }
+ else
+ {
+ TRACFCOMP(g_trac_scom, "ScomTest::test_P9_translate_scom> Target %d in the list of targets does not exist in the system", i);
+ }
}
-
- TRACFCOMP( g_trac_scom, "ScomTest::test_translateScom_XBUS> %d/%d fails", fails, total );
-
- }
- //@todo - write tests to verify connection between XSCOM and FSISCOM
-
- //@todo - write error path testcase for FSI scom using bad address
-
-
-
+ TRACFCOMP( g_trac_scom, "ScomTest::test_P9_translateScom_SBE> %d/%d fails", fails, total );
+}
/**
@@ -1711,7 +972,8 @@ public:
{
continue;
}
- else if (scom_targets[x]->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
+ else if
+ (scom_targets[x]->getAttr<TARGETING::ATTR_HWAS_STATE>().functional != true)
{
TRACDCOMP( g_trac_scom, "ScomTest::test_FSISCOMreadWrite_proc> Target %d is not functional", x );
scom_targets[x] = NULL; //remove from our list
diff --git a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
index 981ae7bdb..5c13545bc 100644
--- a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
@@ -37,7 +37,9 @@
* Each MCS has 2 MCA units (a total of 8 per chip)
* Each Nimbus has 2 MCBIST units (1 per MCU)
* Each Nimbus has 3 PECs
- * Each PEC has 6 PHBs
+ * PEC 0 has 1 PHB
+ * PEC 1 has 2 PHBs
+ * PEC 2 has 3 PHBs
* Each Nimbus has 1 XBUS chiplet
* Each Nimbus has 2 OBUS (OB0 and OB3)
* Each Nimbus has 2 NVBUS
@@ -1141,7 +1143,7 @@
</targetInstance>
<targetInstance>
- <id>sys0node0proc0mcs1mca1</id>
+ <id>sys0node0proc0mcs1mca3</id>
<type>unit-mca-nimbus</type>
<attribute><id>HUID</id><default>0x000D0103</default></attribute>
<attribute>
@@ -1343,17 +1345,18 @@
</attribute>
</targetInstance>
+<!-- Nimbus n0p0pec1 PHB units -->
<targetInstance>
- <id>sys0node0proc0pec0phb1</id>
+ <id>sys0node0proc0pec1phb0</id>
<type>unit-phb-nimbus</type>
<attribute><id>HUID</id><default>0x000E0101</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-0/phb-1</default>
+ <default>physical:sys-0/node-0/proc-0/pec-1/phb-0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-0/phb-1</default>
+ <default>affinity:sys-0/node-0/proc-0/pec-1/phb-0</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
@@ -1362,16 +1365,16 @@
</targetInstance>
<targetInstance>
- <id>sys0node0proc0pec0phb2</id>
+ <id>sys0node0proc0pec1phb1</id>
<type>unit-phb-nimbus</type>
<attribute><id>HUID</id><default>0x000E0102</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-0/phb-2</default>
+ <default>physical:sys-0/node-0/proc-0/pec-1/phb-1</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-0/phb-2</default>
+ <default>affinity:sys-0/node-0/proc-0/pec-1/phb-1</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
@@ -1379,17 +1382,18 @@
</attribute>
</targetInstance>
+<!-- Nimbus n0p0pec2 PHB units -->
<targetInstance>
- <id>sys0node0proc0pec0phb3</id>
+ <id>sys0node0proc0pec2phb0</id>
<type>unit-phb-nimbus</type>
<attribute><id>HUID</id><default>0x000E0103</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-0/phb-3</default>
+ <default>physical:sys-0/node-0/proc-0/pec-2/phb-0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-0/phb-3</default>
+ <default>affinity:sys-0/node-0/proc-0/pec-2/phb-0</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
@@ -1398,16 +1402,16 @@
</targetInstance>
<targetInstance>
- <id>sys0node0proc0pec0phb4</id>
+ <id>sys0node0proc0pec2phb1</id>
<type>unit-phb-nimbus</type>
<attribute><id>HUID</id><default>0x000E0104</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-0/phb-4</default>
+ <default>physical:sys-0/node-0/proc-0/pec-2/phb-1</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-0/phb-4</default>
+ <default>affinity:sys-0/node-0/proc-0/pec-2/phb-1</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
@@ -1416,16 +1420,16 @@
</targetInstance>
<targetInstance>
- <id>sys0node0proc0pec0phb5</id>
+ <id>sys0node0proc0pec2phb2</id>
<type>unit-phb-nimbus</type>
<attribute><id>HUID</id><default>0x000E0105</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-0/phb-5</default>
+ <default>physical:sys-0/node-0/proc-0/pec-2/phb-2</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-0/phb-5</default>
+ <default>affinity:sys-0/node-0/proc-0/pec-2/phb-2</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
@@ -1433,127 +1437,333 @@
</attribute>
</targetInstance>
-<!-- Nimbus n0p0pec1 PHB units -->
+<!-- Nimbus n0p0 OBUS units -->
<targetInstance>
- <id>sys0node0proc0pec1phb0</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0106</default></attribute>
+ <id>sys0node0proc0obus0</id>
+ <type>unit-obus-nimbus</type>
+ <attribute><id>HUID</id><default>0x000E0200</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-1/phb-0</default>
+ <default>physical:sys-0/node-0/proc-0/obus-0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-1/phb-0</default>
+ <default>affinity:sys-0/node-0/proc-0/obus-0</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
- <default>6</default>
+ <default>0</default>
</attribute>
</targetInstance>
<targetInstance>
- <id>sys0node0proc0pec1phb1</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0107</default></attribute>
+ <id>sys0node0proc0obus3</id>
+ <type>unit-obus-nimbus</type>
+ <attribute><id>HUID</id><default>0x000E0201</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-1/phb-1</default>
+ <default>physical:sys-0/node-0/proc-0/obus-3</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-1/phb-1</default>
+ <default>affinity:sys-0/node-0/proc-0/obus-3</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
- <default>7</default>
+ <default>3</default>
</attribute>
</targetInstance>
+<!-- Nimbus n0p0 NVBUS units -->
<targetInstance>
- <id>sys0node0proc0pec1phb2</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0108</default></attribute>
+ <id>sys0node0proc0nvbus0</id>
+ <type>unit-nvbus-nimbus</type>
+ <attribute><id>HUID</id><default>0x000E0300</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-1/phb-2</default>
+ <default>physical:sys-0/node-0/proc-0/nvbus-0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-1/phb-2</default>
+ <default>affinity:sys-0/node-0/proc-0/nvbus-0</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
- <default>8</default>
+ <default>0</default>
</attribute>
</targetInstance>
<targetInstance>
- <id>sys0node0proc0pec1phb3</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0109</default></attribute>
+ <id>sys0node0proc0nvbus1</id>
+ <type>unit-nvbus-nimbus</type>
+ <attribute><id>HUID</id><default>0x000E0301</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-1/phb-3</default>
+ <default>physical:sys-0/node-0/proc-0/nvbus-1</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-1/phb-3</default>
+ <default>affinity:sys-0/node-0/proc-0/nvbus-1</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
- <default>9</default>
+ <default>1</default>
</attribute>
</targetInstance>
+<!-- Nimbus n0p0 PPE units
+ Up to 18 PPEs per Nimbus, only create 2 in this config for now -->
<targetInstance>
- <id>sys0node0proc0pec1phb4</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E010A</default></attribute>
+ <id>sys0node0proc0ppe0</id>
+ <type>unit-ppe-nimbus</type>
+ <attribute><id>HUID</id><default>0x000E0400</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-1/phb-4</default>
+ <default>physical:sys-0/node-0/proc-0/ppe-0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-1/phb-4</default>
+ <default>affinity:sys-0/node-0/proc-0/ppe-0</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
- <default>10</default>
+ <default>0</default>
</attribute>
</targetInstance>
<targetInstance>
- <id>sys0node0proc0pec1phb5</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E010B</default></attribute>
+ <id>sys0node0proc0ppe1</id>
+ <type>unit-ppe-nimbus</type>
+ <attribute><id>HUID</id><default>0x000E0401</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-1/phb-5</default>
+ <default>physical:sys-0/node-0/proc-0/ppe-1</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-1/phb-5</default>
+ <default>affinity:sys-0/node-0/proc-0/ppe-1</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
- <default>11</default>
+ <default>1</default>
</attribute>
</targetInstance>
-<!-- Nimbus n0p0pec2 PHB units -->
+<!-- Nimbus n0p0 PERV units
+ Multiple per Nimbus-->
<targetInstance>
- <id>sys0node0proc0pec2phb0</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E010C</default></attribute>
+ <id>sys0node0proc0perv1</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0001</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-2/phb-0</default>
+ <default>physical:sys-0/node-0/proc-0/perv-1</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-2/phb-0</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-1</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>1</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv2</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0002</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-2</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-2</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>2</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv3</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0003</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-3</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-3</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>3</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv4</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0004</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-4</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-4</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>4</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv5</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0005</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-5</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-5</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>5</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv6</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0006</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-6</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-6</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>6</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv7</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0007</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-7</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-7</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>7</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv8</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0008</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-8</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-8</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>8</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv9</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0009</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-9</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-9</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>9</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv12</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C000C</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-12</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-12</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
@@ -1562,16 +1772,20 @@
</targetInstance>
<targetInstance>
- <id>sys0node0proc0pec2phb1</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E010D</default></attribute>
+ <id>sys0node0proc0perv13</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C000D</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-2/phb-1</default>
+ <default>physical:sys-0/node-0/proc-0/perv-13</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-2/phb-1</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-13</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
@@ -1580,16 +1794,20 @@
</targetInstance>
<targetInstance>
- <id>sys0node0proc0pec2phb2</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E010E</default></attribute>
+ <id>sys0node0proc0perv14</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C000E</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-2/phb-2</default>
+ <default>physical:sys-0/node-0/proc-0/perv-14</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-2/phb-2</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-14</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
@@ -1598,16 +1816,20 @@
</targetInstance>
<targetInstance>
- <id>sys0node0proc0pec2phb3</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E010F</default></attribute>
+ <id>sys0node0proc0perv15</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C000F</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-2/phb-3</default>
+ <default>physical:sys-0/node-0/proc-0/perv-15</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-2/phb-3</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-15</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
@@ -1616,16 +1838,20 @@
</targetInstance>
<targetInstance>
- <id>sys0node0proc0pec2phb4</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0110</default></attribute>
+ <id>sys0node0proc0perv16</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0010</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-2/phb-4</default>
+ <default>physical:sys-0/node-0/proc-0/perv-16</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-2/phb-4</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-16</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
@@ -1634,16 +1860,20 @@
</targetInstance>
<targetInstance>
- <id>sys0node0proc0pec2phb5</id>
- <type>unit-phb-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0111</default></attribute>
+ <id>sys0node0proc0perv17</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0011</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/pec-2/phb-5</default>
+ <default>physical:sys-0/node-0/proc-0/perv-17</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/pec-2/phb-5</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-17</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
@@ -1651,156 +1881,623 @@
</attribute>
</targetInstance>
-<!-- Nimbus n0p0 OBUS units -->
<targetInstance>
- <id>sys0node0proc0obus0</id>
- <type>unit-obus-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0200</default></attribute>
+ <id>sys0node0proc0perv18</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0012</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/obus-0</default>
+ <default>physical:sys-0/node-0/proc-0/perv-18</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/obus-0</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-18</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
+ <default>18</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv19</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0013</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-19</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
<default>0</default>
</attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-19</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>19</default>
+ </attribute>
</targetInstance>
<targetInstance>
- <id>sys0node0proc0obus3</id>
- <type>unit-obus-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0201</default></attribute>
+ <id>sys0node0proc0perv20</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0014</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/obus-3</default>
+ <default>physical:sys-0/node-0/proc-0/perv-20</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/obus-3</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-20</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
- <default>1</default>
+ <default>20</default>
</attribute>
</targetInstance>
-<!-- Nimbus n0p0 NVBUS units -->
<targetInstance>
- <id>sys0node0proc0nvbus0</id>
- <type>unit-nvbus-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0300</default></attribute>
+ <id>sys0node0proc0perv21</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0015</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/nvbus-0</default>
+ <default>physical:sys-0/node-0/proc-0/perv-21</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/nvbus-0</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-21</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>21</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv32</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0020</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-32</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-32</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
+ <default>32</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv33</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0021</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-33</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
<default>0</default>
</attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-33</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>33</default>
+ </attribute>
</targetInstance>
<targetInstance>
- <id>sys0node0proc0nvbus1</id>
- <type>unit-nvbus-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0301</default></attribute>
+ <id>sys0node0proc0perv34</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0022</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/nvbus-1</default>
+ <default>physical:sys-0/node-0/proc-0/perv-34</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/nvbus-1</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-34</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
- <default>1</default>
+ <default>34</default>
</attribute>
</targetInstance>
-<!-- Nimbus n0p0 PPE units
- Up to 18 PPEs per Nimbus, only create 2 in this config for now -->
<targetInstance>
- <id>sys0node0proc0ppe0</id>
- <type>unit-ppe-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0400</default></attribute>
+ <id>sys0node0proc0perv35</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0023</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/ppe-0</default>
+ <default>physical:sys-0/node-0/proc-0/perv-35</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/ppe-0</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-35</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
+ <default>35</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv36</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0024</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-36</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
<default>0</default>
</attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-36</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>36</default>
+ </attribute>
</targetInstance>
<targetInstance>
- <id>sys0node0proc0ppe1</id>
- <type>unit-ppe-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0401</default></attribute>
+ <id>sys0node0proc0perv37</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0025</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/ppe-1</default>
+ <default>physical:sys-0/node-0/proc-0/perv-37</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/ppe-1</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-37</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
- <default>1</default>
+ <default>37</default>
</attribute>
</targetInstance>
-<!-- Nimbus n0p0 PERV units
- Multiple per Nimbus, only create 2 in this config for now -->
<targetInstance>
- <id>sys0node0proc0perv0</id>
+ <id>sys0node0proc0perv38</id>
<type>unit-perv-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0500</default></attribute>
+ <attribute><id>HUID</id><default>0x002C0026</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/perv-0</default>
+ <default>physical:sys-0/node-0/proc-0/perv-38</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/perv-0</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-38</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
+ <default>38</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv39</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0027</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-39</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
<default>0</default>
</attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-39</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>39</default>
+ </attribute>
</targetInstance>
<targetInstance>
- <id>sys0node0proc0perv1</id>
+ <id>sys0node0proc0perv40</id>
<type>unit-perv-nimbus</type>
- <attribute><id>HUID</id><default>0x000E0501</default></attribute>
+ <attribute><id>HUID</id><default>0x002C0028</default></attribute>
<attribute>
<id>PHYS_PATH</id>
- <default>physical:sys-0/node-0/proc-0/perv-1</default>
+ <default>physical:sys-0/node-0/proc-0/perv-40</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
</attribute>
<attribute>
<id>AFFINITY_PATH</id>
- <default>affinity:sys-0/node-0/proc-0/perv-1</default>
+ <default>affinity:sys-0/node-0/proc-0/perv-40</default>
</attribute>
<attribute>
<id>CHIP_UNIT</id>
- <default>1</default>
+ <default>40</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv41</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0029</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-41</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-41</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>41</default>
</attribute>
</targetInstance>
+<targetInstance>
+ <id>sys0node0proc0perv42</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C002A</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-42</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-42</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>42</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv43</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C002B</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-43</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-43</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>43</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv44</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C002C</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-44</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-44</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>44</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv45</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C002D</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-45</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-45</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>45</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv46</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C002E</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-46</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-46</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>46</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv47</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C002F</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-47</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-47</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>47</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv48</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0030</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-48</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-48</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>48</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv49</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0031</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-49</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-49</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>49</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv50</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0032</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-50</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-50</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>50</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv51</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0033</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-51</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-51</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>51</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv52</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0034</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-52</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-52</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>52</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv53</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0035</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-53</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-53</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>53</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv54</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0036</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-54</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-54</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>54</default>
+ </attribute>
+</targetInstance>
+
+<targetInstance>
+ <id>sys0node0proc0perv55</id>
+ <type>unit-perv-nimbus</type>
+ <attribute><id>HUID</id><default>0x002C0037</default></attribute>
+ <attribute>
+ <id>PHYS_PATH</id>
+ <default>physical:sys-0/node-0/proc-0/perv-55</default>
+ </attribute>
+ <attribute>
+ <id>MRU_ID</id>
+ <default>0</default>
+ </attribute>
+ <attribute>
+ <id>AFFINITY_PATH</id>
+ <default>affinity:sys-0/node-0/proc-0/perv-55</default>
+ </attribute>
+ <attribute>
+ <id>CHIP_UNIT</id>
+ <default>55</default>
+ </attribute>
+</targetInstance>
+
+
<!-- nimbus n0p0 XBUS units -->
<targetInstance>
<id>sys0node0proc0xbus0</id>
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