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authorJenny Huynh <jhuynh@us.ibm.com>2018-10-11 17:09:40 -0500
committerChristian R. Geddes <crgeddes@us.ibm.com>2018-10-18 11:11:18 -0500
commita04dc7a75506e8668457b150e8a799f70105d843 (patch)
tree07b7c4cef2782de184a04231c8c4b7941f53549d
parent4f8994da8802111de87c90a4cd0b984b64a200f5 (diff)
downloadtalos-hostboot-a04dc7a75506e8668457b150e8a799f70105d843.tar.gz
talos-hostboot-a04dc7a75506e8668457b150e8a799f70105d843.zip
Enforce SMF size requirements and correct valid bit
- Minimum 256MB secure memory size required - Only allow 256MB offsets to avoid mismatches in hw/attr values - Only set SMF valid if there are ports in the group Change-Id: Iffe0ded1a4c11523846fbf2778c5c317affc7d8f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67376 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67380 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C20
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C14
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml6
-rw-r--r--src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml24
4 files changed, 55 insertions, 9 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
index d6178bea6..45066b62d 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
@@ -1443,6 +1443,15 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setSMFBaseSizeData(
"smfSupported 0x%llX, smfConfig 0x%llX, smfEnabled 0x%llX, smfSize 0x%.16llX",
l_smfSupported, l_smfConfig, l_smfEnabled, l_smfTotalSize);
+ // Ensure that requested secure memory size meets minimum design requirements
+ FAPI_ASSERT((l_smfTotalSize & 0xFFFFFFFFF0000000) != 0,
+ fapi2::MSS_EFF_GROUPING_SMF_256MB_MINIMUM_ERROR()
+ .set_SMF_TOTAL_BAR_SIZE(l_smfTotalSize),
+ "EffGroupingBaseSizeData::setSMFBaseSizeData: Requested size of "
+ "secure memory must meet design minimum requirement of 256MB. "
+ "smfSize 0x%.16llX",
+ l_smfTotalSize);
+
// Setup mem base and size working array depending on mirror setting
if (i_sysAttrs.iv_selectiveMode ==
fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) // Normal
@@ -1526,6 +1535,17 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setSMFBaseSizeData(
iv_smf_bar_base = l_mem_bases[l_index] + l_mem_sizes[l_index];
iv_smf_bar_base |= ((uint64_t)1 << (63 - 15));
+ // Ensure that requested secure memory offset meets design requirements
+ FAPI_ASSERT((iv_smf_bar_base & 0x000000000FFFFFFF) == 0,
+ fapi2::MSS_EFF_GROUPING_SMF_256MB_OFFSET_ERROR()
+ .set_SMF_BASE_ADDR(iv_smf_bar_base),
+ "EffGroupingBaseSizeData::setSMFBaseSizeData: Secure memory regions "
+ "are required by design to be on 256MB offsets. "
+ "smfBaseAddr 0x%.16llX",
+ iv_smf_bar_base);
+
+
+
// Allocate SMF base address and size for region where SMF starts
l_smf_bases[l_index] = l_mem_bases[l_index] + l_mem_sizes[l_index];
l_smf_sizes[l_index] = (l_accMemSize - l_memSizeAfterSmf);
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
index d43001262..d64ead488 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
@@ -692,7 +692,7 @@ fapi2::ReturnCode getNonMirrorBarData(const fapi2::Target<T>& i_mcTarget,
// Alternate Memory MCFGPA
for (uint8_t ii = 0; ii < NUM_OF_ALT_MEM_REGIONS; ii++)
{
- if ( i_portInfo[0].altMemValid[ii] )
+ if ( o_mcBarData.MCFGP_valid && i_portInfo[0].altMemValid[ii] )
{
o_mcBarData.MCFGPA_HOLE_valid[ii] = 1;
o_mcBarData.MCFGPA_HOLE_LOWER_addr[ii] = i_portInfo[0].altBaseAddr[ii];
@@ -706,7 +706,7 @@ fapi2::ReturnCode getNonMirrorBarData(const fapi2::Target<T>& i_mcTarget,
o_mcBarData.MCFGPA_HOLE_UPPER_addr[ii] = 0;
}
- if ( i_portInfo[1].altMemValid[ii] )
+ if ( o_mcBarData.MCFGPM_valid && i_portInfo[1].altMemValid[ii] )
{
o_mcBarData.MCFGPMA_HOLE_valid[ii] = 1;
o_mcBarData.MCFGPMA_HOLE_LOWER_addr[ii] = i_portInfo[1].altBaseAddr[ii];
@@ -723,7 +723,7 @@ fapi2::ReturnCode getNonMirrorBarData(const fapi2::Target<T>& i_mcTarget,
}
// SMF Section of MCFGPA and MCFGPMA
- if ( i_portInfo[0].smfMemValid )
+ if ( o_mcBarData.MCFGP_valid && i_portInfo[0].smfMemValid )
{
o_mcBarData.MCFGPA_SMF_valid = 1;
o_mcBarData.MCFGPA_SMF_LOWER_addr = i_portInfo[0].smfBaseAddr;
@@ -736,7 +736,7 @@ fapi2::ReturnCode getNonMirrorBarData(const fapi2::Target<T>& i_mcTarget,
o_mcBarData.MCFGPA_SMF_UPPER_addr = 0;
}
- if ( i_portInfo[1].smfMemValid )
+ if ( o_mcBarData.MCFGPM_valid && i_portInfo[1].smfMemValid )
{
o_mcBarData.MCFGPMA_SMF_valid = 1;
o_mcBarData.MCFGPMA_SMF_LOWER_addr = i_portInfo[1].smfBaseAddr;
@@ -890,6 +890,12 @@ void displayMCBarData(const uint8_t i_mcPosition,
FAPI_INF(" MCFGPM_valid %u", i_mcBarData.MCFGPM_valid);
FAPI_INF(" MCFGPM_group_size %u", i_mcBarData.MCFGPM_group_size);
FAPI_INF(" MCFGPM_groupBaseAddr 0x%.16llX", i_mcBarData.MCFGPM_groupBaseAddr);
+ FAPI_INF(" MCFGPA_SMF_valid %u", i_mcBarData.MCFGPA_SMF_valid);
+ FAPI_INF(" MCFGPA_SMF_LOWER_addr 0x%.16llX", i_mcBarData.MCFGPA_SMF_LOWER_addr);
+ FAPI_INF(" MCFGPA_SMF_UPPER_addr 0x%.16llX", i_mcBarData.MCFGPA_SMF_UPPER_addr);
+ FAPI_INF(" MCFGPMA_SMF_valid %u", i_mcBarData.MCFGPMA_SMF_valid);
+ FAPI_INF(" MCFGPMA_SMF_LOWER_addr 0x%.16llX", i_mcBarData.MCFGPMA_SMF_LOWER_addr);
+ FAPI_INF(" MCFGPMA_SMF_UPPER_addr 0x%.16llX", i_mcBarData.MCFGPMA_SMF_UPPER_addr);
for (uint8_t jj = 0; jj < NUM_OF_ALT_MEM_REGIONS; jj++)
{
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
index 02b4bfe99..d18d7f02a 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -1241,7 +1241,7 @@
<id>ATTR_PROC_SMF_BAR_SIZE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description> The total amount of memory a user has requested to reserve for
- secure memory functions.
+ secure memory functions. Minimum requirement of 256MB.
Used by p9_mss_eff_grouping.
</description>
<valueType>uint64</valueType>
@@ -1257,10 +1257,6 @@
1_GB = 0x0000000040000000,
512_MB = 0x0000000020000000,
256_MB = 0x0000000010000000,
- 128_MB = 0x0000000008000000,
- 64_MB = 0x0000000004000000,
- 32_MB = 0x0000000002000000,
- 16_MB = 0x0000000001000000,
ZERO = 0x0000000000000000
</enum>
<initToZero/>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
index b312e010e..5147e960f 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
@@ -148,6 +148,30 @@
</hwpError>
<hwpError>
+ <rc>RC_MSS_EFF_GROUPING_SMF_256MB_MINIMUM_ERROR</rc>
+ <description>
+ Secure memory must be a minimum size of 256MB by design.
+ </description>
+ <ffdc>SMF_TOTAL_BAR_SIZE</ffdc>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>HIGH</priority>
+ </callout>
+</hwpError>
+
+<hwpError>
+ <rc>RC_MSS_EFF_GROUPING_SMF_256MB_OFFSET_ERROR</rc>
+ <description>
+ Secure memory must be allocated in offsets of 256MB by design.
+ </description>
+ <ffdc>SMF_BASE_ADDR</ffdc>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>HIGH</priority>
+ </callout>
+</hwpError>
+
+<hwpError>
<rc>RC_MSS_EFF_GROUPING_NO_SPACE_FOR_SMF_BAR</rc>
<description>
There is not enough memory available for the requested SMF bar sizes.
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