SW282769: FW820:Subsequent MPIPL test hit a B111BA24 - RC_PROC_TOD_INIT_ERROR er

CQ:SW282769
Change-Id: Ieb9062e1cec2180c9aad7e7355a0aeacd022bbca
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14123
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14173
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

4 files changed, 361 insertions, 35 deletions

diff --git a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
index 0226cc875..0647550e0 100644
--- a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
+++ b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml
@@ -22,14 +22,14 @@
 <!-- permissions and limitations under the License.                         -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: proc_chip_ec_feature.xml,v 1.55 2014/08/18 19:55:30 jmcgill Exp $ -->
+<!-- $Id: proc_chip_ec_feature.xml,v 1.59 2014/10/23 18:56:33 jklazyns Exp $ -->
 <!-- Defines the attributes that are based on EC level -->
 <attributes>
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      For Venice specific inits. Returns true if Venice.
+      For Venice specific inits. Returns true if Venice and Naples.
     </description>
     <chipEcFeature>
       <chip>
@@ -39,7 +39,7 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
-    </chipEcFeature>
+     </chipEcFeature>
   </attribute>
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_NAPLES_SPECIFIC</id>
@@ -58,6 +58,39 @@
     </chipEcFeature>
   </attribute>
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_USE_POLLING_PROT</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Returns if a chip should use wiggle-flip polling protocol. True if:
+      Murano EC 0x20 or greater
+      Venice EC 0x20 or greater
+      Naples EC 0x10 or greater
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_MURANO</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_VENICE</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW_BUG_PIBSLVRESET</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
@@ -111,7 +144,7 @@
     <id>ATTR_CHIP_EC_FEATURE_SECURE_IOVALID_PRESENT</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Returns if a chip contains secure iovalid controls for the ABUS.  True if either:
+      Returns if a chip contains secure iovalid controls for the ABUS. Intentionally not applied to Naples True if either:
         Murano EC 0x20 or greater
         Venice EC 0x10 or greater
     </description>
@@ -172,6 +205,7 @@
     <description>
       Returns if a chip contains 32 lanes of PCIE I/O.  True if:
         Venice EC 0x10 or greater
+        Naples EC 0x10 or greater
     </description>
     <chipEcFeature>
       <chip>
@@ -181,6 +215,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -190,6 +231,7 @@
       Returns if a chip contains SCOM configuration for CAPP unit PB hang recovery controls.  True if:
         Murano EC 0x20 or greater
         Venice EC 0x10 or greater
+        Naples EC 0x10 or greater
     </description>
     <chipEcFeature>
       <chip>
@@ -206,6 +248,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -215,6 +264,7 @@
       Returns if a chip contains production CAPP logic function
         Murano EC 0x20 or greater
         Venice EC 0x20 or greater
+        Naples EC 0x10 or greater
     </description>
     <chipEcFeature>
       <chip>
@@ -231,6 +281,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -240,6 +297,7 @@
       Returns if a chip contains SCOM configuration for NX unit PB hang recovery controls.  True if:
         Murano EC 0x20 or greater
         Venice EC 0x20 or greater
+        Naples EC 0x10 or greater
     </description>
     <chipEcFeature>
       <chip>
@@ -256,6 +314,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -265,6 +330,7 @@
       Returns if a chip contains separate SCOM configuration for HCA oper/data hang PB hang recovrery controls.  True if:
         Murano EC 0x20 or greater
         Venice EC 0x10 or greater
+        Naples EC 0x10 or greater
     </description>
     <chipEcFeature>
       <chip>
@@ -281,6 +347,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -290,6 +363,7 @@
       True if:
         Murano EC 0x20 or greater
         Venice EC 0x10 or greater
+        Naples EC 0x10 or greater
         Centaur EC 0x20 or greater
     </description>
     <chipEcFeature>
@@ -308,6 +382,13 @@
         </ec>
       </chip>
       <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+      <chip>
         <name>ENUM_ATTR_NAME_CENTAUR</name>
         <ec>
           <value>0x20</value>
@@ -323,6 +404,7 @@
       True if:
         Murano EC 0x20 or greater
         Venice EC 0x10 or greater
+        Naples EC 0x10 or greater
         Centaur EC 0x20 or greater
     </description>
     <chipEcFeature>
@@ -341,6 +423,13 @@
         </ec>
       </chip>
       <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+      <chip>
         <name>ENUM_ATTR_NAME_CENTAUR</name>
         <ec>
           <value>0x20</value>
@@ -356,6 +445,7 @@
       True if:
         Murano EC 0x20 or greater
         Venice EC 0x10 or greater
+        Naples EC 0x10 or greater
         Centaur EC 0x20 or greater
     </description>
     <chipEcFeature>
@@ -374,6 +464,13 @@
         </ec>
       </chip>
       <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+      <chip>
         <name>ENUM_ATTR_NAME_CENTAUR</name>
         <ec>
           <value>0x20</value>
@@ -507,6 +604,7 @@
       True if:
         Murano EC greater or equal to 0x20
         Venice EC greater or equal to 0x20
+        Naples EC greater or equal to 0x10
     </description>
     <chipEcFeature>
       <chip>
@@ -523,6 +621,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -532,6 +637,7 @@
       True if:
         Murano EC greater than or equal to 0x20
         Venice
+        Naples
     </description>
     <chipEcFeature>
       <chip>
@@ -548,6 +654,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -583,6 +696,7 @@
       True if:
         Murano EC greater than or equal to 0x20
         Venice EC greater than or equal to 0x20
+        Naples EC greater than or equal to 0x10
     </description>
     <chipEcFeature>
       <chip>
@@ -599,6 +713,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -608,6 +729,7 @@
       Specifies layout of C8 serial chain
       True if:
         Murano/Venice EC greater than or equal to 0x20
+        Naples greater than or equal to 0x10
     </description>
     <chipEcFeature>
       <chip>
@@ -624,6 +746,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -676,6 +805,7 @@
     <description>
       True if:
         Venice EC greater than or equal to 0x20
+        Naples EC greater than or equal to 0x10
       False otherwise
     </description>
     <chipEcFeature>
@@ -686,6 +816,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -694,6 +831,7 @@
     <description>
       True if:
         Venice EC greater than or equal to 0x20
+        Naples EC greater than or equal to 0x10
       False otherwise
     </description>
     <chipEcFeature>
@@ -704,6 +842,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -713,6 +858,7 @@
       Specifies layout of C10 serial chain
       True if:
         Murano/Venice EC greater than or equal to 0x20
+        Naples EC greater than or euqal to 0x10
     </description>
     <chipEcFeature>
       <chip>
@@ -729,6 +875,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -764,6 +917,7 @@
       True if:
         Murano EC 0x20 or greater
         Venice EC 0x10 or greater
+        Naples EC 0x10 or greater
     </description>
     <chipEcFeature>
       <chip>
@@ -780,6 +934,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -830,12 +991,38 @@
     </chipEcFeature>
   </attribute>
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_XBUS_RESONANT_CLK_VALID</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      True if:
+        Venice EC 0x10 or greater
+        Naples EC 0x10 or greater
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_VENICE</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_RESONANT_CLK_VALID</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
       True if:
         Murano EC 0x20 or greater
         Venice EC 0x20 or greater
+        Naples EC 0x10 or greater
     </description>
     <chipEcFeature>
       <chip>
@@ -852,6 +1039,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -862,6 +1056,7 @@
       True if:
         Murano EC 0x20 or greater
         Venice EC 0x20 or greater
+        Naples EC 0x10 or greater
     </description>
     <chipEcFeature>
       <chip>
@@ -878,6 +1073,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -904,6 +1106,7 @@
       True if:
         Murano EC greater than or equal to 0x20
         Venice
+        Naples
     </description>
     <chipEcFeature>
       <chip>
@@ -920,6 +1123,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -929,6 +1139,7 @@
       True if:
         Murano EC greater than or equal to 0x20
         Venice
+        Naples
     </description>
     <chipEcFeature>
       <chip>
@@ -945,6 +1156,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -971,6 +1189,7 @@
       True if:
         Murano EC greater than 0x20
         Venice EC greater than or equal to 0x20
+        Naples greater than or equal to 0x10
     </description>
     <chipEcFeature>
       <chip>
@@ -987,6 +1206,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -1009,6 +1235,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -1050,6 +1283,7 @@
     True if chip can support PBA prefetch as HW258436 is fixed
         Murano EC greater than or equal to 0x21
         Venice EC greater than or equal to 0x20
+        Naples EC greater than or equal to 0x10
     </description>
     <chipEcFeature>
       <chip>
@@ -1066,6 +1300,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
     <attribute>
@@ -1075,6 +1316,7 @@
     True if chip can support the enablement of L3 purge aborts during Winkle as HW276505 is fixed
         Not fixed on any Murano EC
         Venice EC 0x20 or greater
+        Naples EC 0x10 or greater
     </description>
     <chipEcFeature>
       <chip>
@@ -1084,6 +1326,13 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
   <attribute>
@@ -1154,6 +1403,7 @@
         True if chip has HCA BAR SCOM bug
         Causes HCA BAR range data read via SCOM to be shifted relative to HW state
         Venice EC greater than or equal to 0x20
+        Naples EC greater than or equal to 0x10
     </description>
     <chipEcFeature>
       <chip>
@@ -1163,6 +1413,29 @@
           <test>GREATER_THAN_OR_EQUAL</test>
         </ec>
       </chip>
+      <chip>
+        <name>ENUM_ATTR_NAME_NAPLES</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW_BUG_TOD_ERROR_MASK_NOT_WRITABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+        HW223230/HW216879 - TOD_ERROR_MASK_STATUS_REG_00040032 is not writable in Murano DD1.x
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_MURANO</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
     </chipEcFeature>
   </attribute>
 </attributes>
diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.C b/src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.C
index 7fd18d588..820863315 100644
--- a/src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.C
+++ b/src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.C
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_tod_init.C,v 1.12 2014/10/03 18:44:41 thi Exp $
+// $Id: proc_tod_init.C,v 1.15 2014/10/23 18:56:17 jklazyns Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
 // *! All Rights Reserved -- Property of IBM
@@ -56,13 +56,13 @@ extern "C"
 //------------------------------------------------------------------------------
 // function: proc_tod_init
 //
-// parameters: 
+// parameters:
 //         i_tod_node  Reference to TOD topology (FAPI targets included within)
 //
-//         i_failingTodProc, Porinter to the fapi target, the memory location
+//         i_failingTodProc, Pointer to the fapi target, the memory location
 //         addressed by this parameter will be populated with processor target
 //         which is not able to recieve proper singals from OSC.
-//         Caller needs to look at this parameter only when proc_tod_init fails 
+//         Caller needs to look at this parameter only when proc_tod_init fails
 //         and reason code indicates OSC failure. It is defaulted to NULL.
 //
 // returns: FAPI_RC_SUCCESS if TOD topology is successfully initialized
@@ -169,13 +169,13 @@ fapi::ReturnCode proc_tod_clear_error_reg(const tod_topology_node* i_tod_node)
 //------------------------------------------------------------------------------
 // function: init_tod_node
 //
-// parameters: 
+// parameters:
 //          i_tod_node  Reference to TOD topology (FAPI targets included within)
 //
-//          i_failingTodProc, Porinter to the fapi target, the memory location
+//          i_failingTodProc, Pointer to the fapi target, the memory location
 //          addressed by this parameter will be populated with processor target
 //          which is not able to recieve proper singals from OSC.
-//          Caller needs to look at this parameter only when proc_tod_init fails 
+//          Caller needs to look at this parameter only when proc_tod_init fails
 //          and reason code indicates OSC failure. It is defaulted to NULL.
 //
 // returns: FAPI_RC_SUCCESS if TOD topology is successfully initialized
@@ -190,7 +190,7 @@ fapi::ReturnCode init_tod_node(const tod_topology_node* i_tod_node,
     uint32_t tod_init_pending_count = 0; // Timeout counter for bits that are cleared by hardware
     fapi::Target* target = i_tod_node->i_target;
 
-    FAPI_INF("init_tod_node: Start: Configuring %s", target->toEcmdString());
+    FAPI_INF("init_tod_node: Start: Initializing %s", target->toEcmdString());
 
     do
     {
@@ -244,7 +244,7 @@ fapi::ReturnCode init_tod_node(const tod_topology_node* i_tod_node,
                 FAPI_ERR("init_tod_node: Master: Could not write TOD_TX_TTYPE_5_REG_00040016");
                 break;
             }
-   
+
             FAPI_INF("init_tod_node: Master: Chip TOD load value (move TB to TOD)");
             rc_ecmd |= data.flushTo0();
             rc_ecmd |= data.setWord(0,0x00000000);
@@ -299,7 +299,7 @@ fapi::ReturnCode init_tod_node(const tod_topology_node* i_tod_node,
         while (tod_init_pending_count < PROC_TOD_UTIL_TIMEOUT_COUNT)
         {
             FAPI_DBG("init_tod_node: Waiting for TOD to assert TOD_FSM_REG_TOD_IS_RUNNING...");
-   
+
             rc = fapiDelay(PROC_TOD_UTILS_HW_NS_DELAY,
                            PROC_TOD_UTILS_SIM_CYCLE_DELAY);
             if (!rc.ok())
@@ -332,10 +332,11 @@ fapi::ReturnCode init_tod_node(const tod_topology_node* i_tod_node,
                 break;
         }
 
-        FAPI_INF("init_tod_node: clear TTYPE#2 and TTYPE#4 status");
+        FAPI_INF("init_tod_node: clear TTYPE#2, TTYPE#4, and TTYPE#5 status");
         rc_ecmd |= data.flushTo0();
         rc_ecmd |= data.setBit(TOD_ERROR_REG_RX_TTYPE_2);
         rc_ecmd |= data.setBit(TOD_ERROR_REG_RX_TTYPE_4);
+        rc_ecmd |= data.setBit(TOD_ERROR_REG_RX_TTYPE_5);
         if (rc_ecmd)
         {
             FAPI_ERR("init_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_ERROR_REG_00040030.",  rc_ecmd);
@@ -380,20 +381,35 @@ fapi::ReturnCode init_tod_node(const tod_topology_node* i_tod_node,
             break;
         }
 
-        FAPI_INF("init_tod_node: set error mask to runtime configuration");
-        rc_ecmd |= data.flushTo0();
-        rc_ecmd |= data.setWord(1,0x03F00000); // Mask TTYPE received informational bits 38:43
-        if (rc_ecmd)
+        // TOD_ERROR_MASK_STATUS_REG_00040032 is not writable on some chips
+        uint8_t chipHasTodErrorMaskBug = 0;
+        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_HW_BUG_TOD_ERROR_MASK_NOT_WRITABLE, target, chipHasTodErrorMaskBug);
+        if(rc)
         {
-            FAPI_ERR("init_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_ERROR_MASK_STATUS_REG_00040032 SCOM.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
+            FAPI_ERR("init_tod_node: Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_HW_BUG_TOD_ERROR_MASK_NOT_WRITABLE");
             break;
         }
-        rc = fapiPutScom(*target, TOD_ERROR_MASK_STATUS_REG_00040032, data);
-        if (!rc.ok())
+        if(!chipHasTodErrorMaskBug)
         {
-            FAPI_ERR("init_tod_node: Could not write TOD_ERROR_MASK_STATUS_REG_00040032");
-            break;
+            FAPI_INF("init_tod_node: set error mask to runtime configuration");
+            rc_ecmd |= data.flushTo0();
+            rc_ecmd |= data.setWord(1,0x03F00000); // Mask TTYPE received informational bits 38:43
+            if (rc_ecmd)
+            {
+                FAPI_ERR("init_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_ERROR_MASK_STATUS_REG_00040032 SCOM.",  rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            rc = fapiPutScom(*target, TOD_ERROR_MASK_STATUS_REG_00040032, data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("init_tod_node: Could not write TOD_ERROR_MASK_STATUS_REG_00040032");
+                break;
+            }
+        }
+        else
+        {
+            FAPI_INF("init_tod_node: Skipping TOD error mask setup because of chip limitation.");
         }
 
         // Finish configuring downstream nodes
diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.C b/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.C
index 39f5b4a28..2fcae0881 100644
--- a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.C
+++ b/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.C
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_tod_setup.C,v 1.21 2014/09/09 16:13:20 jklazyns Exp $
+// $Id: proc_tod_setup.C,v 1.22 2014/10/22 17:11:05 jklazyns Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
 // *! All Rights Reserved -- Property of IBM
@@ -79,6 +79,7 @@ fapi::ReturnCode proc_tod_setup(tod_topology_node*           i_tod_node,
                                 const proc_tod_setup_osc_sel i_osc_sel)
 {
     fapi::ReturnCode rc;
+    fapi::ATTR_IS_MPIPL_Type is_mpipl = 0x00;
 
     // Mark HWP entry
     FAPI_INF("proc_tod_setup: Start");
@@ -112,8 +113,15 @@ fapi::ReturnCode proc_tod_setup(tod_topology_node*           i_tod_node,
         }
         display_tod_nodes(i_tod_node,0);
 
+        rc =  FAPI_ATTR_GET(ATTR_IS_MPIPL, NULL, is_mpipl);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_tod_setup: fapiGetAttribute of ATTR_IS_MPIPL failed!");
+            break;
+        }
+
         // If there is a previous topology, it needs to be cleared
-        rc = clear_tod_node(i_tod_node,i_tod_sel);
+        rc = clear_tod_node(i_tod_node, i_tod_sel, is_mpipl);
         if (!rc.ok())
         {
             FAPI_ERR("proc_tod_setup: Failure clearing previous TOD configuration!");
@@ -139,14 +147,18 @@ fapi::ReturnCode proc_tod_setup(tod_topology_node*           i_tod_node,
 //
 // parameters: i_tod_node  Reference to TOD topology (FAPI targets included within)
 //             i_tod_sel   Specifies the topology to clear
+//             i_is_mpipl  if this IPL is an MPIPL, additional setup is needed; 
+//                         determined via an attribute
 //
 // returns: FAPI_RC_SUCCESS if TOD topology is successfully cleared
 //          else FAPI or ECMD error is sent through
 //------------------------------------------------------------------------------
-fapi::ReturnCode clear_tod_node(tod_topology_node*           i_tod_node,
-                                const proc_tod_setup_tod_sel i_tod_sel)
+fapi::ReturnCode clear_tod_node(tod_topology_node*             i_tod_node,
+                                const proc_tod_setup_tod_sel   i_tod_sel,
+                                const fapi::ATTR_IS_MPIPL_Type i_is_mpipl)
 {
     fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
     ecmdDataBufferBase data(64);
     fapi::Target* target = i_tod_node->i_target;
     uint32_t port_ctrl_reg = 0;
@@ -169,7 +181,6 @@ fapi::ReturnCode clear_tod_node(tod_topology_node*           i_tod_node,
             port_ctrl_reg = TOD_SEC_PORT_1_CTRL_REG_00040004;
             port_ctrl_check_reg = TOD_PRI_PORT_1_CTRL_REG_00040002;
         }
-
         rc = fapiPutScom(*target,port_ctrl_reg,data);
         if (!rc.ok())
         {
@@ -182,14 +193,37 @@ fapi::ReturnCode clear_tod_node(tod_topology_node*           i_tod_node,
             FAPI_ERR("clear_tod_node: fapiPutScom error for port_ctrl_check_reg SCOM.");
             break;
         }
- 
+
+        if (i_is_mpipl)
+        {
+            FAPI_INF("clear_tod_node: MPIPL: switch TOD to 'Not Set' state");
+            rc_ecmd |= data.flushTo0();
+            rc_ecmd |= data.setBit(0);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("clear_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_TX_TTYPE_5_REG_00040016 SCOM.",  rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            rc = fapiPutScom(*target, TOD_TX_TTYPE_5_REG_00040016, data);
+            if (!rc.ok())
+            {
+                FAPI_ERR("clear_tod_node: Could not write TOD_TX_TTYPE_5_REG_00040016");
+                break;
+            }
+        }
+        else
+        {
+            FAPI_INF("clear_tod_node: Normal IPL: Bypass TTYPE#5");
+        }
+
         // TOD is cleared for this node; if it has children, start clearing their registers
         for (std::list<tod_topology_node*>::iterator child = (i_tod_node->i_children).begin();
              child != (i_tod_node->i_children).end();
              ++child)
         {
             tod_topology_node* tod_node = *child;
-            rc = clear_tod_node(tod_node,i_tod_sel);
+            rc = clear_tod_node(tod_node,i_tod_sel,i_is_mpipl);
             if (!rc.ok())
             {
                 FAPI_ERR("clear_tod_node: Failure clearing downstream TOD node!");
diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.H b/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.H
index 593936fca..ee553ab1d 100644
--- a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.H
+++ b/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.H
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_tod_setup.H,v 1.8 2014/05/27 16:31:03 jklazyns Exp $
+// $Id: proc_tod_setup.H,v 1.9 2014/10/22 17:11:13 jklazyns Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
 // *! All Rights Reserved -- Property of IBM
@@ -107,12 +107,15 @@ fapi::ReturnCode configure_tod_node(tod_topology_node*           i_tod_node,
  *
  * @param[in] i_tod_node  Reference to TOD topology (FAPI targets included within)
  *            i_tod_sel   Specifies the topology to clear
+ *            i_is_mpipl  if this IPL is an MPIPL, additional setup is needed; 
+ *                        determined via an attribute
  *
  * @return FAPI_RC_SUCCESS if TOD topology is successfully cleared
  *         else FAPI or ECMD error is sent through
  */
-fapi::ReturnCode clear_tod_node(tod_topology_node*           i_tod_node,
-                                const proc_tod_setup_tod_sel i_tod_sel);
+fapi::ReturnCode clear_tod_node(tod_topology_node*             i_tod_node,
+                                const proc_tod_setup_tod_sel   i_tod_sel,
+                                const fapi::ATTR_IS_MPIPL_Type i_is_mpipl);
 
 /**
  * @brief Calculates TOD_CHIP_CTRL_REG_00040010 value; will be called