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| author | Li Meng <shlimeng@cn.ibm.com> | 2018-11-06 14:32:31 -0600 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2018-12-14 10:54:22 -0600 |
| commit | 9b441810e8d7a55a8427b3303ec8c6596b8b6963 (patch) | |
| tree | 7e5298ab02da9e286ec614164c226c32ee5e6fd3 | |
| parent | c955ff685e6647abd4a540dfcfde0390cd894ed6 (diff) | |
| download | talos-hostboot-9b441810e8d7a55a8427b3303ec8c6596b8b6963.tar.gz talos-hostboot-9b441810e8d7a55a8427b3303ec8c6596b8b6963.zip | |
Adds LRDIMM MWD fine training step
Change-Id: Ib5d4a3c236ce477e6312691b49374ef74379eb16
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68465
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68912
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
3 files changed, 10 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H index ab7ad1db5..33469fe1b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H @@ -426,10 +426,10 @@ inline instruction_t<T> act_command( const fapi2::Target<fapi2::TARGET_TYPE_DIMM // Just leaving the row addresses to all 0 for now // row, bg, ba set to 0 l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ADDRESS_17>(); - l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_ADDRESS_0_13, TT::ARR0_DDR_ADDRESS_0_13_LEN>(0); + l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ADDRESS_0_13, TT::ARR0_DDR_ADDRESS_0_13_LEN>(); l_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_GROUP_1>(); l_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_GROUP_0>(); - l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_BANK_0_1, TT::ARR0_DDR_BANK_0_1_LEN>(0); + l_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_0_1, TT::ARR0_DDR_BANK_0_1_LEN>(); l_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_2>(); return instruction_t<T>(i_target, i_rank, l_boilerplate_arr0, l_boilerplate_arr1); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H index 229f9efe7..65c2a9207 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H @@ -65,7 +65,6 @@ namespace training namespace lrdimm { - /// /// @brief Issues initial pattern write to all ranks in the rank pair /// @param[in] i_target the MCA target on which to operate diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C index 5c1df9aaf..fc5629cea 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C @@ -60,6 +60,7 @@ #include <lib/phy/mss_dwl.H> #include <lib/phy/mss_mrd_fine.H> #include <lib/phy/mss_mwd_coarse.H> + #include <lib/phy/mss_mwd_fine.H> #endif namespace mss @@ -1258,6 +1259,13 @@ std::vector<std::shared_ptr<step>> steps_factory(const fapi2::buffer<uint32_t>& l_steps.push_back(std::make_shared<mss::training::lrdimm::mwd_coarse>()); } + //MWD FINE + if(i_cal_steps.getBit<mss::cal_steps::MWD_FINE>()) + { + FAPI_INF("LRDIMM: MWD FINE is enabled"); + l_steps.push_back(std::make_shared<mss::training::lrdimm::mwd_fine>()); + } + #endif // INITIAL_PAT_WR |
