Fix sim problems on awan

    Increase CCS polling limit for draminit training by factor of 2
    Add sim check around CKE controls in RCW settings (till resolved)

Change-Id: I605bdd5355f33a39988b9c5530506bafca7e6d33
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46835
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47037
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

4 files changed, 28 insertions, 8 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
index 96bd311e7..fe7e62806 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H
@@ -372,11 +372,17 @@ inline instruction_t<T> rcd_command( const fapi2::Target<fapi2::TARGET_TYPE_DIMM
     //
     mrs_rcd_helper<fapi2::TARGET_TYPE_MCBIST>(rcd_boilerplate_arr0);
 
+    uint8_t l_sim = 0;
+    mss::is_simulation(l_sim);
+
     // Not adding i_turn_on_cke in the mrs_rcd helper because we only need this
     // for RCWs and there is no need to complicate/change the MRS cmd API with
     // uneeded functionality. Little duplication, but this isolates the change.
-    const uint64_t l_cke = i_turn_on_cke ? CKE_HIGH : CKE_LOW;
-    rcd_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(l_cke);
+    if( !l_sim )
+    {
+        const uint64_t l_cke = i_turn_on_cke ? CKE_HIGH : CKE_LOW;
+        rcd_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(l_cke);
+    }
 
     //
     // RCD setup
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C
index 5a13471a2..e165b71b7 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C
@@ -61,18 +61,24 @@ fapi2::ReturnCode rcd_load<TARGET_TYPE_MCBIST>( const fapi2::Target<TARGET_TYPE_
     // A vector of CCS instructions. We'll ask the targets to fill it, and then we'll execute it
     ccs::program<TARGET_TYPE_MCBIST> l_program;
 
+    uint8_t l_sim = 0;
     // Clear the initial delays. This will force the CCS engine to recompute the delay based on the
     // instructions in the CCS instruction vector
     l_program.iv_poll.iv_initial_delay = 0;
     l_program.iv_poll.iv_initial_sim_delay = 0;
 
+    FAPI_TRY(mss::is_simulation(l_sim));
+
     for ( const auto& p : mss::find_targets<TARGET_TYPE_MCA>(i_target) )
     {
         for ( const auto& d : mss::find_targets<TARGET_TYPE_DIMM>(p) )
         {
             // CKE needs to be LOW before running the RCW sequence
             // So we use the power down entry command to achieve this
-            l_program.iv_instructions.push_back( ccs::pde_command<TARGET_TYPE_MCBIST>() );
+            if(!l_sim)
+            {
+                l_program.iv_instructions.push_back( ccs::pde_command<TARGET_TYPE_MCBIST>() );
+            }
 
             FAPI_DBG("rcd load for %s", mss::c_str(d));
             FAPI_TRY( perform_rcd_load(d, l_program.iv_instructions),
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index 315e80144..45e36dd95 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -1101,7 +1101,7 @@ fapi2::ReturnCode setup_cal_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA>&
     }
 
     FAPI_INF("cal_config for %s: 0x%04lx (steps: 0x%08x)",
-             mss::c_str(i_target), uint16_t(l_cal_config), uint32_t(i_cal_steps_enabled));
+             mss::c_str(i_target), uint16_t(l_cal_config), i_cal_steps_enabled);
     FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_INIT_CAL_CONFIG0_P0, l_cal_config) );
 
     // Sets up the workarounds
@@ -1157,7 +1157,11 @@ fapi2::ReturnCode execute_cal_steps_helper( const fapi2::Target<fapi2::TARGET_TY
         fapi2::Assert(false);
     }
 
-    FAPI_DBG("executing training CCS instruction: 0x%llx, 0x%llx", l_cal_inst.arr0, l_cal_inst.arr1);
+    FAPI_DBG("%s executing training CCS instruction: 0x%llx, 0x%llx for cal steps 0x%08x",
+             mss::c_str(i_target),
+             l_cal_inst.arr0,
+             l_cal_inst.arr1,
+             i_cal_steps_enabled);
 
     // Delays in the CCS instruction ARR1 for training are supposed to be 0xFFFF,
     // and we're supposed to poll for the done or timeout bit. But we don't want
@@ -1182,8 +1186,8 @@ fapi2::ReturnCode execute_cal_steps_helper( const fapi2::Target<fapi2::TARGET_TY
 
     // If we got a cal timeout, or another CCS error just leave now. If we got success, check the error
     // bits for a cal failure. We'll return the proper ReturnCode so all we need to do is FAPI_TRY.
-    FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target), "%s failed to execute CCS program for cal steps 0x%04lx",
-              mss::c_str(i_target), uint16_t(i_cal_steps_enabled) );
+    FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target), "%s failed to execute CCS program for cal steps 0x%08x",
+              mss::c_str(i_target), i_cal_steps_enabled );
 
 fapi_try_exit:
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml
index 1f46ce524..ca5a92623 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml
@@ -242,7 +242,7 @@
       <target>MCBIST_TARGET</target>
       <targetType>TARGET_TYPE_MCBIST</targetType>
     </collectRegisterFfdc>
-    <callout>
+   <callout>
       <target>MCBIST_TARGET</target>
       <priority>HIGH</priority>
     </callout>
@@ -252,6 +252,10 @@
     <gard>
         <target>MCBIST_TARGET</target>
     </gard>
+    <callout>
+        <procedure>CODE</procedure>
+        <priority>MEDIUM</priority>
+    </callout>
   </hwpError>
 
   <hwpError>