summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMatt Derksen <mderkse1@us.ibm.com>2019-06-03 09:29:13 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2019-06-04 14:34:31 -0500
commit7779247d5f657e04212ecf4b225e10a3da27af77 (patch)
tree4d9b5dce8e2b9635a082bb4bce3a81d3612d1857
parent20f6884ac8c615da75db885feae636ca60dc6f5a (diff)
downloadtalos-hostboot-7779247d5f657e04212ecf4b225e10a3da27af77.tar.gz
talos-hostboot-7779247d5f657e04212ecf4b225e10a3da27af77.zip
Enable calling p9_setup_evid for Axone
Simics provided an AVS bus fix so this call should now pass. Previously failed for bad CRC (computed 7, received 0) Change-Id: I74a15263244aa66158bf33e68eceddcb439edd15 RTC:209750 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78244 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Glenn Miles <milesg@ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
-rw-r--r--src/usr/isteps/istep08/call_host_set_voltages.C4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/usr/isteps/istep08/call_host_set_voltages.C b/src/usr/isteps/istep08/call_host_set_voltages.C
index dff6a6424..fe37ef21b 100644
--- a/src/usr/isteps/istep08/call_host_set_voltages.C
+++ b/src/usr/isteps/istep08/call_host_set_voltages.C
@@ -72,9 +72,6 @@ void* call_host_set_voltages(void *io_pArgs)
do
{
- // Skip p9_setup_evid on Axone, no targets exist
- #ifndef CONFIG_AXONE_BRING_UP
-
TargetHandleList l_procList;
// Get the system's procs
getAllChips( l_procList,
@@ -118,7 +115,6 @@ void* call_host_set_voltages(void *io_pArgs)
{
break;
}
- #endif
// If no error occurred and FSP is present,
// send voltage information to HWSV
OpenPOWER on IntegriCloud