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| author | CHRISTINA L. GRAVES <clgraves@us.ibm.com> | 2017-01-16 17:52:25 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-03-13 09:53:52 -0400 |
| commit | 6567fe47ef124bf760016cba5c790fdff3d3155a (patch) | |
| tree | 6928d53f1570f5a70f992c770117df5b9bd230bf | |
| parent | 0c1a9c38bba560dff6beaffe4933c609660c53bf (diff) | |
| download | talos-hostboot-6567fe47ef124bf760016cba5c790fdff3d3155a.tar.gz talos-hostboot-6567fe47ef124bf760016cba5c790fdff3d3155a.zip | |
p9_setup_bars -- support DD2 NPU SCOM address changes
Change-Id: Ief409a8a4bae838c89888abbb17f44e430ce6c3c
Original-Change-Id: I33afb42e7b29f58447aa430a07ca052c60f79cd4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34965
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55495
CI-Ready: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 1d79e79ec..ee5c8ae83 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -2435,6 +2435,24 @@ </chip> </chipEcFeature> </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + DD1 only: Use the DD1 register addresses for the PHY0 BAR registers, PHY1 BAR registers, and MMIO BAR registers + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> <id>ATTR_CHIP_EC_FEATURE_HW397129</id>> |
