Initial commit of memory subsystem

Change-Id: I45674f8c5fcc6c524750ae4b4e049dcda8665502
Original-Change-Id: I6b63d2c4eec5d77585c91d905a464962a6153a0a
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22978
Tested-by: Jenkins Server
Reviewed-by: Craig C. Hamilton <cchamilt@us.ibm.com>
Reviewed-by: Brian Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24532
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

6 files changed, 759 insertions, 0 deletions

diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml
new file mode 100644
index 000000000..be8684f9a
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml
@@ -0,0 +1,111 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: chips/p9/procedures/xml/error_info/p9_memory_mss_ddr_phy_reset.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- EKB Project                                                            -->
+<!--                                                                        -->
+<!-- COPYRIGHT 2015                                                         -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+
+<!-- -->
+<!-- @file memory_mss_ddr_phy_reset.xml -->
+<!-- @brief Error xml for ddr_phy_reset -->
+<!-- -->
+<!-- *HWP HWP Owner: Name <email address> -->
+<!-- *HWP FW Owner: Name <email address> -->
+<!-- *HWP Team: Team Name -->
+<!-- *HWP Level: 1 -->
+<!-- *HWP Consumed by: XX:XX -->
+<!-- -->
+
+<hwpErrors>
+
+<hwpError>
+  <rc>RC_MSS_DP16_PLL_FAILED_TO_LOCK</rc>
+  <description>
+    p9_mss_ddr_phy_reset: DP16 PLL failed to lock! Value in MCA_DDRPHY_PC_DP18_PLL_LOCK_STATUS not as expected
+  </description>
+  <ffdc>EXPECTED_STATUS</ffdc>
+  <ffdc>ACTUAL_STATUS</ffdc>
+  <ffdc>REGISTER</ffdc>
+  <callout>
+    <target>MCBIST_IN_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <callout>
+    <hw>
+      <hwid>MEM_REF_CLOCK</hwid>
+      <refTarget>MCBIST_IN_ERROR</refTarget>
+    </hw>
+    <priority>MEDIUM</priority>
+  </callout>
+  <deconfigure>
+    <target>MCBIST_IN_ERROR</target>
+  </deconfigure>
+  <gard>
+    <target>MCBIST_IN_ERROR</target>
+  </gard>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_AD32S_PLL_FAILED_TO_LOCK</rc>
+  <description>
+    p9_mss_ddr_phy_reset: AD32S PLL failed to lock! Value in MCA_DDRPHY_PC_AD32S_PLL_LOCK_STATUS not as expected
+  </description>
+  <ffdc>EXPECTED_STATUS</ffdc>
+  <ffdc>ACTUAL_STATUS</ffdc>
+  <ffdc>REGISTER</ffdc>
+  <callout>
+    <target>MCBIST_IN_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <callout>
+    <hw>
+      <hwid>MEM_REF_CLOCK</hwid>
+      <refTarget>MCBIST_IN_ERROR</refTarget>
+    </hw>
+    <priority>MEDIUM</priority>
+  </callout>
+  <deconfigure>
+    <target>MCBIST_IN_ERROR</target>
+  </deconfigure>
+  <gard>
+    <target>MCBIST_IN_ERROR</target>
+  </gard>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_BANG_BANG_FAILED_TO_LOCK</rc>
+  <description>
+    p9_mss_ddr_phy_reset: phy clock and sysclk failed to align.
+  </description>
+  <callout>
+    <target>MCA_IN_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <callout>
+    <hw>
+      <hwid>MEM_REF_CLOCK</hwid>
+      <refTarget>MCA_IN_ERROR</refTarget>
+    </hw>
+    <priority>MEDIUM</priority>
+  </callout>
+  <deconfigure>
+    <target>MCA_IN_ERROR</target>
+  </deconfigure>
+  <gard>
+    <target>MCA_IN_ERROR</target>
+  </gard>
+</hwpError>
+
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml
new file mode 100644
index 000000000..b9e87c118
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml
@@ -0,0 +1,54 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- EKB Project                                                            -->
+<!--                                                                        -->
+<!-- COPYRIGHT 2015                                                         -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+
+<!-- -->
+<!-- @file memory_mss_draminit.xml -->
+<!-- @brief Error xml for draminit -->
+<!-- -->
+<!-- *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -->
+<!-- *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -->
+<!-- *HWP FW Owner: Bill Hoffa <wghoffa@us.ibm.com> -->
+<!-- *HWP Team: Memory -->
+<!-- *HWP Level: 1 -->
+<!-- *HWP Consumed by: HB:FSP -->
+<!-- -->
+
+<hwpErrors>
+
+<hwpError>
+  <rc>RC_MSS_UNKNOWN_DIMM</rc>
+  <description>
+    This DIMM's type or DRAM generation are not supported by the system
+  </description>
+  <ffdc>DIMM_TYPE</ffdc>
+  <ffdc>DRAM_GEN</ffdc>
+  <callout>
+    <target>DIMM_IN_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <deconfigure>
+    <target>DIMM_IN_ERROR</target>
+  </deconfigure>
+  <gard>
+    <target>DIMM_IN_ERROR</target>
+  </gard>
+</hwpError>
+
+
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml
new file mode 100644
index 000000000..16b964e49
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml
@@ -0,0 +1,307 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- EKB Project                                                            -->
+<!--                                                                        -->
+<!-- COPYRIGHT 2015                                                         -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+
+<!-- -->
+<!-- @file memory_mss_draminit_training.xml -->
+<!-- @brief Error xml for draminit_training -->
+<!-- -->
+<!-- *HWP HWP Owner: Brian Silver <bsilver@us.ibm.com> -->
+<!-- *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -->
+<!-- *HWP FW Owner: Bill Hoffa <wghoffa@us.ibm.com> -->
+<!-- *HWP Team: Memory -->
+<!-- *HWP Level: 1 -->
+<!-- *HWP Consumed by: HB:FSP -->
+<!-- -->
+
+<hwpErrors>
+
+<registerFfdc>
+  <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_0</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_1</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_2</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_3</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P0_4</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_0</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_1</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_2</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_3</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P0_4</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_0</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_1</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_2</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_3</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P0_4</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_0</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_1</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_2</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_3</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P0_4</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_0</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_1</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_2</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_3</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP0_P1_4</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_0</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_1</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_2</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_3</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP1_P1_4</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_0</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_1</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_2</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_3</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP2_P1_4</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_0</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_1</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_2</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_3</scomRegister>
+  <scomRegister>MCA_DDRPHY_DP16_DATA_BIT_DISABLE0_RP3_P1_4</scomRegister>
+</registerFfdc>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_MULTIPLE_ERRORS</rc>
+  <description>Multiple training stesp failed for a given position within this calibration.</description>
+  <ffdc>FAILED_STEPS</ffdc>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_WR_LVL_ERROR</rc>
+  <description>Write Leveling has returned a fail for a given position within this calibration.</description>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_INITIAL_PAT_WRITE_ERROR</rc>
+  <description>Initial pattern write has returned a fail for a given position within this calibration.</description>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR</rc>
+  <description>DQS Alignment has returned a fail for a given position within this calibration.</description>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_RD_CLK_SYS_CLK_ALIGNMENT_ERROR</rc>
+  <description>Read CLK to SYS CLK Alignment has returned a fail for a given position within this calibration.</description>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_RD_CENTERING_ERROR</rc>
+  <description>Read Centering has returned a fail for a given position within this calibration.</description>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_WR_CENTERING_ERROR</rc>
+  <description>Write centering has returned a fail for a given position within this calibration.</description>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_INITIAL_COARSE_WR_ERROR</rc>
+  <description>Initial coarse write has returned a fail for a given position within this calibration.</description>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_COARSE_RD_ERROR</rc>
+  <description>Coarse read has returned a fail for a given position within this calibration.</description>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_RD_ERROR</rc>
+  <description>Custom Pattern Read has returned a fail for a given position within this calibration.</description>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_WR_ERROR</rc>
+  <description>Custom Pattern Write has returned a fail for a given position within this calibration.</description>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_DIGITAL_EYE_ERROR</rc>
+  <description>Digital Eye has returned a fail for a given position within this calibration.</description>
+  <ffdc>PORT_POSITION</ffdc>
+  <ffdc>RANKGROUP_POSITION</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_DRAMINIT_TRAINING_FAILURE_DISABLE_REGS</id>
+    <target>TARGET_IN_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_IN_ERROR</target>
+    <priority>LOW</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>HIGH</priority>
+  </callout>
+</hwpError>
+
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml
new file mode 100644
index 000000000..f2ca82047
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml
@@ -0,0 +1,137 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml $   -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- EKB Project                                                            -->
+<!--                                                                        -->
+<!-- COPYRIGHT 2015                                                         -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+
+<!-- $Id: memory_mss_freq.xml,v 1.2 2014/03/06 00:11:49 jdsloat Exp $ -->
+<!-- For file ../../ipl/fapi/mss_freq.C -->
+<!-- // *! OWNER NAME :   Jacob Sloat (jdsloat@us.ibm.com) -->
+<!-- // *! BACKUP NAME :   -->
+
+<!-- Original Source for RC_MSS_UNSUPPORTED_SPD_DATA_DDR4 memory_errors.xml -->
+  <hwpError>
+    <rc>RC_MSS_UNSUPPORTED_SPD_DATA_DDR4</rc>
+    <description>Invalid SPD data returned.</description>
+    <ffdc>MTB_DDR4</ffdc>
+    <ffdc>FTB_DDR4</ffdc>
+    <callout>
+      <target>DIMM_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>DIMM_TARGET</target>
+    </deconfigure>
+</hwpError>
+
+<!-- Original Source for RC_MSS_UNSUPPORTED_SPD_DATA_DDR3 memory_errors.xml -->
+  <hwpError>
+    <rc>RC_MSS_UNSUPPORTED_SPD_DATA_DDR3</rc>
+    <description>Invalid SPD data returned.</description>
+    <ffdc>MTB_DIVIDEND</ffdc>
+    <ffdc>MTB_DIVISOR</ffdc>
+    <ffdc>FTB_DIVIDEND</ffdc>
+    <ffdc>FTB_DIVISOR</ffdc>
+    <callout>
+      <target>DIMM_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>DIMM_TARGET</target>
+    </deconfigure>
+</hwpError>
+
+<!-- Original Source for RC_MSS_UNSUPPORTED_SPD_DATA_COMMON memory_errors.xml -->
+  <hwpError>
+    <rc>RC_MSS_UNSUPPORTED_SPD_DATA_COMMON</rc>
+    <description>Invalid SPD data returned.</description>
+    <ffdc>MIN_TCK</ffdc>
+    <ffdc>MIN_TAA</ffdc>
+    <callout>
+      <target>TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>DIMM_TARGET</target>
+    </deconfigure>
+</hwpError>
+
+<!-- Original Source for RC_MSS_MODULE_TYPE_MIX memory_errors.xml -->
+  <hwpError>
+    <rc>RC_MSS_MODULE_TYPE_MIX</rc>
+    <description>Differing DIMM types in the same configuration.</description>
+    <ffdc>MODULE_TYPE</ffdc>
+    <callout>
+      <target>DIMM_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>DIMM_TARGET</target>
+    </deconfigure>
+</hwpError>
+
+<!-- Original Source for RC_MSS_NO_COMMON_SUPPORTED_CL memory_errors.xml -->
+  <hwpError>
+    <rc>RC_MSS_NO_COMMON_SUPPORTED_CL</rc>
+    <description>Current Configuration has no common supported CL Values.</description>
+    <ffdc>CL_SUPPORTED</ffdc>
+    <callout>
+      <target>DIMM_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>DIMM_TARGET</target>
+    </deconfigure>
+</hwpError>
+
+<!-- Original Source for RC_MSS_EXCEED_TAA_MAX_NO_CL memory_errors.xml -->
+  <hwpError>
+    <rc>RC_MSS_EXCEED_TAA_MAX_NO_CL</rc>
+    <description>Exceeded TAA MAX with Lowest frequency.  No compatable CL.</description>
+    <ffdc>CL_SUPPORTED</ffdc>
+    <callout>
+      <target>DIMM_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>DIMM_TARGET</target>
+    </deconfigure>
+</hwpError>
+
+<!-- Original Source for RC_MSS_UNSUPPORTED_FREQ_CALCULATED memory_errors.xml -->
+  <hwpError>
+    <rc>RC_MSS_UNSUPPORTED_FREQ_CALCULATED</rc>
+    <description>The frequency calculated with spd data is not supported by the jedec standards.</description>
+    <ffdc>DIMM_MIN_FREQ</ffdc>
+</hwpError>
+
+<!-- Original Source for RC_MSS_UNSUPPORTED_DEV_TYPE  memory_errors.xml -->
+  <hwpError>
+      <rc>RC_MSS_UNSUPPORTED_DEV_TYPE</rc>
+      <description>Device type is not DDR4.</description>
+      <ffdc>DEV_TYPE</ffdc>
+      <callout>
+        <target>DIMM_TARGET</target>
+        <priority>HIGH</priority>
+      </callout>
+      <deconfigure>
+        <target>DIMM_TARGET</target>
+      </deconfigure>
+
+ </hwpError>
+
+</hwpErrors>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml
new file mode 100644
index 000000000..f3fd22fb3
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml
@@ -0,0 +1,111 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml $    -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- EKB Project                                                            -->
+<!--                                                                        -->
+<!-- COPYRIGHT 2015                                                         -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+
+<!-- -->
+<!-- @file memory_mss_lib.xml -->
+<!-- @brief Error xml for MSS library routines -->
+<!-- -->
+<!-- *HWP HWP Owner:  Andre Marin <aamarin@us.ibm.com> -->
+<!-- *HWP FW Owner: Brian Silver <bsilver@us.ibm.com> -->
+<!-- *HWP Team: Memory -->
+<!-- *HWP Level: 1 -->
+<!-- *HWP Consumed by: HB:FSP -->
+<!-- -->
+
+
+
+<hwpErrors>
+
+  <registerFfdc>
+    <id>REG_FFDC_MSS_CCS_FAILURE</id>
+    <scomRegister>MCBIST_CCS_MODEQ</scomRegister>
+    <scomRegister>MCBIST_CCS_STATQ</scomRegister>
+    <scomRegister>MCBIST_CCS_CNTLQ</scomRegister>
+  </registerFfdc>
+
+  <hwpError>
+    <rc>RC_MSS_CCS_READ_MISCOMPARE</rc>
+    <description>CCS reports a read miscompare.</description>
+    <ffdc>REG_CONTENTS</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_MSS_CCS_FAILURE</id>
+      <target>TARGET_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>TARGET_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>TARGET_IN_ERROR</target>
+    </deconfigure>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_CCS_UE_SUE</rc>
+    <description>CCS reports a UE or SUE</description>
+    <ffdc>REG_CONTENTS</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_MSS_CCS_FAILURE</id>
+      <target>TARGET_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>TARGET_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>TARGET_IN_ERROR</target>
+    </deconfigure>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_CCS_CAL_TIMEOUT</rc>
+    <description>CCS reports a calibration operation timeout</description>
+    <ffdc>REG_CONTENTS</ffdc>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_MSS_CCS_FAILURE</id>
+      <target>TARGET_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>TARGET_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>TARGET_IN_ERROR</target>
+    </deconfigure>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_CCS_HUNG</rc>
+    <description>CCS failed to return from in_progress status and failed to describe an error further.</description>
+    <collectRegisterFfdc>
+      <id>REG_FFDC_MSS_CCS_FAILURE</id>
+      <target>TARGET_IN_ERROR</target>
+    </collectRegisterFfdc>
+    <callout>
+      <target>TARGET_IN_ERROR</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>TARGET_IN_ERROR</target>
+    </deconfigure>
+  </hwpError>
+  
+</hwpErrors>
+
+
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml
new file mode 100644
index 000000000..e052d888f
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml
@@ -0,0 +1,39 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml $ -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- EKB Project                                                            -->
+<!--                                                                        -->
+<!-- COPYRIGHT 2015                                                         -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+<!-- $Id: memory_spd_decode.xml,v 1.2 2014/03/06 00:11:49 jdsloat Exp $ -->
+<!-- For file ../../ipl/fapi/mss_freq.C -->
+<!-- // *! OWNER NAME :   Jacob Sloat (jdsloat@us.ibm.com) -->
+<!-- // *! BACKUP NAME :   -->
+
+   <hwpError>
+    <rc>RC_MSS_VALID_VALUE</rc>
+    <description>Invalid data returned.</description>
+    <ffdc>VALUE</ffdc>
+    <ffdc>BYTE</ffdc>
+    <callout>
+      <target>DIMM_TARGET</target>
+      <priority>HIGH</priority>
+    </callout>
+    <deconfigure>
+      <target>DIMM_TARGET</target>
+    </deconfigure>
+    </hwpError>
+
+</hwpErrors>