diff options
| author | CHRISTINA L. GRAVES <clgraves@us.ibm.com> | 2016-12-20 10:19:40 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-01-27 16:18:10 -0500 |
| commit | 5140f2dce0196d4f519e60adaf8946d68dca3db0 (patch) | |
| tree | 731a77864de94310d943ae200aab481cefa44ac4 | |
| parent | 79dd17bc9347600eeeddacc4e19efafbb5f1fe29 (diff) | |
| download | talos-hostboot-5140f2dce0196d4f519e60adaf8946d68dca3db0.tar.gz talos-hostboot-5140f2dce0196d4f519e60adaf8946d68dca3db0.zip | |
Adding in a comment to p9_tod_move_tod_to_tb to explain that 0x20 is
the base chiplet number for all cores
Change-Id: Ibe42b3418724a129ca3bc87b7ececce302e2f17d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34095
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34098
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_tod_move_tod_to_tb.C | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_tod_move_tod_to_tb.C b/src/import/chips/p9/procedures/hwp/nest/p9_tod_move_tod_to_tb.C index 47382db15..85cb3aa69 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_tod_move_tod_to_tb.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_tod_move_tod_to_tb.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -169,6 +169,7 @@ extern "C" //Write TOD_MOVE_TOD_TO_TB_REG(@0x17)[00]=b'1'(move TOD to Timebase). The TOD transfers the TOD value to the Timebase after a SYNC boundary occurred. Note that TOD_TX_TTYPE_CTRL_REG(@0x27)[24:31] needs to be configured before issuing a TOD transfer to Timebase.The address of the PIB slave targeted by the TOD PIB master is configured as 0xNN0126a1 where NN is the configurable slave address specified in TOD_TX_TTYPE_CTRL_REG(@0x27)[24:31]. data.flush<0>(); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, coreTarget, l_core_id)); + //0x20 is the "base" chiplet number for all the cores that's why we add it to the core id l_core_id = l_core_id + 0x20; data.insertFromRight(l_core_id, 0, 8); |
