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authorPrem Shanker Jha <premjha2@in.ibm.com>2017-01-19 13:04:27 -0600
committerDaniel M. Crowell <dcrowell@us.ibm.com>2017-01-24 11:11:53 -0500
commit3b706854fe31421bbfc4a0e952e5b7a8ca2ad390 (patch)
treeb66813a37d1bb59590c1ec7b413c6ca2b509272f
parent61ea8ae1317ea182e90caf72605604924e822c8f (diff)
downloadtalos-hostboot-3b706854fe31421bbfc4a0e952e5b7a8ca2ad390.tar.gz
talos-hostboot-3b706854fe31421bbfc4a0e952e5b7a8ca2ad390.zip
PM: Bug Fix pertaining to SCOM Restore Entry for NCU_DARN_RNG_BAR
Commit addresses following issue reported: HOMER is not written with SCOM restore entry for NCU_DARN_RNG_BAR register for all EX of all EQ. HOMER had SCOM restore entry only for EX0. Change-Id: I6afd2309eea2a5664361857867ebc0125f6c8bee Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35113 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: CHRISTOPHER M. RIEDL <cmriedl@us.ibm.com> Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35120 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
-rw-r--r--src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C34
1 files changed, 21 insertions, 13 deletions
diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
index 1bf79981b..e8b617da1 100644
--- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
+++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C
@@ -2315,6 +2315,7 @@ extern "C"
uint64_t baseAddressNm0 = 0;
uint64_t baseAddressNm1 = 0;
uint64_t baseAddressMirror = 0;
+ uint32_t ncuBarRegisterAddr = 0;
const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NX_RNG_BAR_ENABLE,
@@ -2343,21 +2344,28 @@ extern "C"
regNcuRngBarData += nxRangeBarAddrOffset;
- FAPI_DBG("Restore value for EQ_NCU_DARN_BAR_REG 0x%016lx",
- regNcuRngBarData );
+ for( uint32_t exIndex = 0; exIndex < MAX_CME_PER_CHIP; exIndex++ )
+ {
+ ncuBarRegisterAddr = EX_0_NCU_DARN_BAR_REG;
+ ncuBarRegisterAddr |= (( exIndex >> 1) << 24 );
+ ncuBarRegisterAddr |= ( exIndex & 0x01 ) ? 0x0400 : 0x0000;
- StopReturnCode_t stopRc =
- stopImageSection::p9_stop_save_scom( i_pChipHomer,
- EQ_NCU_DARN_BAR_REG,
- regNcuRngBarData ,
- stopImageSection::P9_STOP_SCOM_REPLACE,
- stopImageSection::P9_STOP_SECTION_EQ_SCOM );
+ FAPI_DBG("CME%d NCU_DARN_BAR Addr 0x%08x Data 0x%016lx ",
+ exIndex, ncuBarRegisterAddr, regNcuRngBarData );
- if( stopRc )
- {
- FAPI_ERR("Failed to update EQ_NCU_DARN_BAR_REG in Self Restore Image 0x%08x",
- stopRc );
- break;
+ StopReturnCode_t stopRc =
+ stopImageSection::p9_stop_save_scom( i_pChipHomer,
+ ncuBarRegisterAddr,
+ regNcuRngBarData ,
+ stopImageSection::P9_STOP_SCOM_REPLACE,
+ stopImageSection::P9_STOP_SECTION_EQ_SCOM );
+
+ if( stopRc )
+ {
+ FAPI_ERR("Failed to update CME%d NCU_DARN_RNG_BAR Reg RC: 0x%08x",
+ exIndex, stopRc );
+ break;
+ }
}
}
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