HWP: Merge updated mss_volt into Hostboot

This version fixes a 1.5V bug. The code has already been reviewed in
the hwp_review_centaur Gerrit project so no review needs to be done.
It works in Simics. This can just be submitted.

Change-Id: I95b5827af562d67a6d0d14d34df2f05901784ea7
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1028
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

2 files changed, 255 insertions, 38 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/memory_errors.xml b/src/usr/hwpf/hwp/dram_training/memory_errors.xml
index ea80ddeef..2ff29fd61 100644
--- a/src/usr/hwpf/hwp/dram_training/memory_errors.xml
+++ b/src/usr/hwpf/hwp/dram_training/memory_errors.xml
@@ -1,7 +1,7 @@
 <!--  IBM_PROLOG_BEGIN_TAG
      This is an automatically generated prolog.
    
-     $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/memory_errors.xml $
+     $Source: src/usr/hwpf/hwp/dram_training/memory_errors.xml $
    
      IBM CONFIDENTIAL
    
@@ -83,4 +83,215 @@
     <description>A read of the nest clock status register returned an unexpected value.    </description>
   </hwpError>
 
+  <hwpError>
+    <rc>RC_MSS_INIT1_OPCG_DONE_ERROR</rc>
+    <description>Timed out waiting for OPCG done bit(15).    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_INIT1_FSISTATUS_FAIL</rc>
+    <description>Failed VDD status check on FSI2PIB Status Reg bit(16).    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_PLL_LOCK_TIMEOUT</rc>
+    <description>Timed out waiting for PLL locks in FSI2PIB Status Reg bits(24,25).     </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_THOLD_ERROR</rc>
+    <description>THOLDS after Clock Start cmd do NOT match to the expected value.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_CCREG_MISMATCH</rc>
+    <description>Clock Control Register does not match the expected value.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_ARRAY_REPAIR_BUSY</rc>
+    <description>Array repair loader is busy now. 0x00050003 bit(0)=1     </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_ARRAY_REPAIR_NOT_DONE</rc>
+    <description>Array repair loader did NOT report repair done.     </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_ECC_TRAP_ERROR</rc>
+    <description>ECC trap register reported error. 0x00050004 bit(0-7) != 0x00    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_DP18_0_PLL_FAILED_TO_LOCK</rc>
+    <description>DP18  0x0C000 PLL failed to lock!  See lock status register at address: 0x8000C0000301143F    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_DP18_1_PLL_FAILED_TO_LOCK</rc>
+    <description>DP18  0x1C000 PLL failed to lock!  See lock status register at address: 0x8001C0000301143F    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_AD32S_0_PLL_FAILED_TO_LOCK</rc>
+    <description>AD32S 0x0C001 PLL failed to lock!  See lock status register at address: 0x8000C0010301143F    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_AD32S_1_PLL_FAILED_TO_LOCK</rc>
+    <description>AD32S 0x1C001 PLL failed to lock!  See lock status register at address: 0x8001C0010301143F    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_GENERAL_PUTSCOM_ERROR</rc>
+    <description>PutScom failed!   See previous error message for details.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_GENERAL_GETSCOM_ERROR</rc>
+    <description>GetScom failed!   See previous error message for details.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_UNEXPECTED_CLOCK_STATUS</rc>
+    <description>Unexpected clock status!  See previous error message for details.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_UNEXPECTED_FIR_STATUS</rc>
+    <description>Unexpected FIR status!  See previous error message for details.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_INIT_CAL_FAILED</rc>
+    <description>Inital Calibration failed.  Check init cal error register at address: 0x8001C0180301143F     </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE</rc>
+    <description>Unsupported DIMM type found.  All dimms must be DDR3 or DDR4    </description>
+    <ffdc>DEVICE_TYPE</ffdc>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED</rc>
+    <description>Mixing of DDR3 and DDR4 not supported.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE</rc>
+    <description>One or more DIMMs do not support required voltage for DDR type.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_GENERAL_SIMSTKFAC_ERROR</rc>
+    <description>simSTKFAC failed!   See previous error message for details    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_GET_FAPI_ATTRIBUTE_ERROR</rc>
+    <description>Failed to get FAPI attribute!   See previous error message for details.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_GET_SIM_HIERARCHY_ERROR</rc>
+    <description>Failed to get simulation hierarchy from eCmd target.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_UNSUPPORTED_FREQ_CALCULATED</rc>
+    <description>The frequency calculated with spd data is not supported by the jedec standards.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_START_NOT_RESET</rc>
+    <description>MCMCCQ[0]: maint_cmd_start not reset by hw.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_STOP_NOT_RESET</rc>
+    <description>MCMCCQ[1]: maint_cmd_stop not reset by hw.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_CMD_IN_PROGRESS</rc>
+    <description>MBMSRQ[0]: Can't start new cmd if previous cmd still in progress.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_NO_MEM_CNFG</rc>
+    <description>MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE</rc>
+    <description>CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_ECC_DISABLED</rc>
+    <description>MBSECC[0] non zero, meaning ECC check/correct disabled.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_INVALID_CMD</rc>
+    <description>MBAFIRQ[0], invalid_maint_cmd.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_INVALID_ADDR</rc>
+    <description>MBAFIRQ[1], cmd started with invalid_maint_address.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_CMD_TIMEOUT</rc>
+    <description>Maint cmd timeout.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH</rc>
+    <description>Invalid dramSize or dramWidth in MBAXCRn.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_INVALID_DIMM_CNFG</rc>
+    <description>MBAXCRn configured with invalid combination of configType, configSubType, slotConfig.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_NO_X4_SYMBOL</rc>
+    <description>Symbol mark not allowed in x4 mode.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_INVALID_MARKSTORE</rc>
+    <description>Invalid galois field in markstore.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_INVALID_SYMBOL_INDEX</rc>
+    <description>Symbol index out of range.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_INVALID_CHIP_INDEX</rc>
+    <description>Not first symbol index of a chip.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED</rc>
+    <description>Markstore write may have been blocked due to MPE FIR set.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER</rc>
+    <description>Trying to steer invalid symbol.    </description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MAINT_NO_X8_ECC_SPARE</rc>
+    <description>Invalid to use ECC spare in x8 mode.    </description>
+  </hwpError>
+
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C b/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C
index bb21ab975..4c48419d1 100644
--- a/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C
+++ b/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C
@@ -46,8 +46,8 @@
 //  1.1    | jsabrow  | 12/13/11 | This version compiles. Attributes dont work yet.
 //  1.3    | bellows  | 12/21/11 | fapiGetAssociatedDimms funciton does not work, added quick exit
 //  1.4    | jsabrow  | 02/13/12 | Updates for code review
-
-//  ???    | mww    | remove internal target vector
+//  1.5    | jsabrow  | 03/26/12 | Updates for code review
+//  1.5    | jdsloat  | 04/26/12 | fixed 1.5V issue
 
 // This procedure takes a vector of Centaurs behind a voltage domain,
 // reads in supported DIMM voltages from SPD and determines optimal
@@ -61,93 +61,99 @@
 #include <fapi.H>
 #include <mss_volt.H>
 
-fapi::ReturnCode mss_volt(std::vector<fapi::Target> & l_targets_memb)
+fapi::ReturnCode mss_volt(std::vector<fapi::Target> & i_targets_memb)
 {
 
   fapi::ReturnCode l_rc;
-  // $$ std::vector<fapi::Target> l_targets_memb;
-  std::vector<fapi::Target> l_mbaChiplets;
-  std::vector<fapi::Target> l_dimm_targets;
   uint8_t l_spd_dramtype=0;
   uint8_t l_spd_volts=0;
-  uint8_t l_spd_volts_all_dimms=0x07;  //start assuming all voltages supported
+  uint8_t l_spd_volts_all_dimms=0x06;  //start assuming all voltages supported
   uint8_t l_dram_ddr3_found_flag=0;
   uint8_t l_dram_ddr4_found_flag=0;
 
   uint32_t l_selected_dram_voltage=0;  //this gets written into all centaurs when done.
 
   // Iterate through the list of centaurs
-  for (uint32_t i=0; i < l_targets_memb.size(); i++)
+  for (uint32_t i=0; i < i_targets_memb.size(); i++)
     {
+      std::vector<fapi::Target> l_mbaChiplets;
       // Get associated MBA's on this centaur
-      l_rc=fapiGetChildChiplets(l_targets_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets);
+      l_rc=fapiGetChildChiplets(i_targets_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets);
+      if (l_rc) return l_rc;
       // Loop through the 2 MBA's
       for (uint32_t j=0; j < l_mbaChiplets.size(); j++)
 	{
+      std::vector<fapi::Target> l_dimm_targets;
 	  // Get a vector of DIMM targets
 	  l_rc = fapiGetAssociatedDimms(l_mbaChiplets[j], l_dimm_targets);
+	  if (l_rc) return l_rc;
 	  for (uint32_t k=0; k < l_dimm_targets.size(); k++)
 	    {
-
 	      l_rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_DEVICE_TYPE, &l_dimm_targets[k], l_spd_dramtype);
-	      // TODO: need to verify l_rc is 'good'
-	      // can I do: 	  if (l_rc) { FAPI_ERR("..."); break; }
+	      if (l_rc) return l_rc;
 	      l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE, &l_dimm_targets[k], l_spd_volts);
-	      // TODO: need to verify l_rc is 'good'
-	      // spd_volts:  bit0=1.5V bit1=1.35V bit2=1.25V, assume a 1.20V in future.
+	      if (l_rc) return l_rc;
+
+	      // spd_volts:  bit0= NOT 1.5V bit1=1.35V bit2=1.25V, assume a 1.20V in future for DDR4
 	      // check for supported voltage/dram type combo  DDR3=12, DDR4=13
-	      if (l_spd_dramtype == 0x0b)
+	      if (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3)
 		{
 		  l_dram_ddr3_found_flag=1;
 		}
-	      else if (l_spd_dramtype == 0x0c)
+	      else if (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4)
 		{
 		  l_dram_ddr4_found_flag=1;
 		}
-	      else
+	      else 
 		{
-		  //FAPI_ERR("Dimm not DDR3 or DDR4");
+		  uint8_t &DEVICE_TYPE = l_spd_dramtype;
+		  FAPI_ERR("Unknown DRAM Device Type 0x%x", l_spd_dramtype);
+		  FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE);
+		  return l_rc;
 		}
-
-	      //AND of voltages support by all dimms in this domain (bit 0 is negative logic)
-	      l_spd_volts = l_spd_volts ^ 0x01;
+	      //AND dimm voltage capabilities together to find aggregate voltage support on all dimms
 	      l_spd_volts_all_dimms = l_spd_volts_all_dimms & l_spd_volts;
-
 	    }
 	}
-    }
+    }      
 
   // now we figure out if we have a supported ddr type and voltage
+  // note: only support DDR3=1.35V and DDR4=1.2xV
+
+  FAPI_INF( "dram type, ddr3 enum, ddr4 enum: 0x%02X 0x%02X 0x%02X", l_spd_dramtype, fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3, fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4);
+
   if (l_dram_ddr3_found_flag && l_dram_ddr4_found_flag)
     {
-      //FAPI_ERR("DDR3 and DDR4 mixing not allowed");
+      FAPI_ERR("mss_volt: DDR3 and DDR4 mixing not allowed");
+      FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED);
+      return l_rc;
     }
-
-
-  if (l_dram_ddr3_found_flag && (l_spd_volts_all_dimms & 0x01) == 0x01)
+  if (l_dram_ddr3_found_flag && ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_35) == fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_35))
     {
       l_selected_dram_voltage=1350;
     }
-  else if (l_dram_ddr4_found_flag && (l_spd_volts_all_dimms & 0x02) == 0x02)
+  else if (l_dram_ddr4_found_flag && ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2X) == fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2X))
     {
       l_selected_dram_voltage=1200;
     }
+  else if ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5) != fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5)
+    {
+      l_selected_dram_voltage=1500;
+    }
   else
     {
-      //FAPI_ERR("Dimms do not all support 1.35 or 1.2x");
+      FAPI_ERR("One or more DIMMs do not support required voltage for DIMM type");
+      FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE);
+      return l_rc;
     }
 
   // Iterate through the list of centaurs again, to update ATTR
-  for (uint32_t i=0; i < l_targets_memb.size(); i++)
+  for (uint32_t i=0; i < i_targets_memb.size(); i++)
     {
-      l_rc = FAPI_ATTR_SET(ATTR_MSS_VOLT, &l_targets_memb[i], l_selected_dram_voltage);
-      if (l_rc)
-	{
-	  //FAPI_ERR("Dimms do not all support 1.35 or 1.2x");
-	  break;
-	}
+      l_rc = FAPI_ATTR_SET(ATTR_MSS_VOLT, &i_targets_memb[i], l_selected_dram_voltage);
+      FAPI_INF( "mss_volt calculation complete.  MSS_VOLT: %d", l_selected_dram_voltage);
+      if (l_rc) return l_rc;
     }
-
   return l_rc;
 }