Add HCDB Support for eeprom cache process

While parsing the EEPROMs of the system as part of the EECACHE process
if we detect a part has been replaced, removed, or added then we must
call markTargetChanged to notify hwas to take appropriate actions.
This commit also introduces the new preloaded EECACHE section for simics.

Change-Id: I9f2a8a62d5c6f9a6c66a0c0c7ed5ed86f7d94aec
RTC: 211109
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78762
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

13 files changed, 345 insertions, 89 deletions

diff --git a/src/build/buildpnor/pnorLayoutAxone.xml b/src/build/buildpnor/pnorLayoutAxone.xml
index c0a8bbcc0..2fe5a1788 100644
--- a/src/build/buildpnor/pnorLayoutAxone.xml
+++ b/src/build/buildpnor/pnorLayoutAxone.xml
@@ -299,6 +299,7 @@ Layout Description
         <ecc/>
     </section>
     <section>
+        <!-- NOTE must update standalone.simics if EECACHE offset changes-->
         <description>Eeprom Cache(512K)</description>
         <eyeCatch>EECACHE</eyeCatch>
         <physicalOffset>0x3E33000</physicalOffset>
diff --git a/src/build/citest/create-sandbox b/src/build/citest/create-sandbox
index 0018e4422..b07158f02 100755
--- a/src/build/citest/create-sandbox
+++ b/src/build/citest/create-sandbox
@@ -78,11 +78,15 @@ if [ "$MACHINE" != "NIMBUS" ] && [ "$MACHINE" != "CUMULUS" ] && \
    [ "$MACHINE" != "CUMULUS_CDIMM" ] && [ "$MACHINE" != "FSPBUILD" ];
 then
     SIMICS_LEVEL=`cat ${PROJECT_ROOT}/src/build/citest/etc/simbuild`
+    EECACHE_PREBUILT=`cat ${PROJECT_ROOT}/src/build/citest/etc/eecache_prebuilt`
     echo "mkdir -p ${SANDBOXBASE}/simics"
     execute_in_sandbox "mkdir -p ${SANDBOXBASE}/simics" "ppc"
     echo "tar ${SIMICS_LEVEL}  -C ${SANDBOXBASE}/simics/"
     execute_in_sandbox "tar -xf ${SIMICS_LEVEL} -C ${SANDBOXBASE}/simics/" "ppc"
+    echo "cd ${SANDBOXBASE}/simics/ && ./INSTALL.sh"
     execute_in_sandbox "cd ${SANDBOXBASE}/simics/ && ./INSTALL.sh" "ppc"
+    echo "cp ${EECACHE_PREBUILT} ${SANDBOXBASE}/simics/eecache_prebuilt.bin.ecc"
+    execute_in_sandbox "cp ${EECACHE_PREBUILT} ${SANDBOXBASE}/simics/eecache_prebuilt.bin.ecc" "ppc"
 else
     execute_in_sandbox "start_simics -no_start -machine $MACHINE -batch_mode" \
                       "ppc" || exit -1
diff --git a/src/build/citest/etc/eecache_prebuilt b/src/build/citest/etc/eecache_prebuilt
new file mode 100644
index 000000000..d0ac7a63b
--- /dev/null
+++ b/src/build/citest/etc/eecache_prebuilt
@@ -0,0 +1 @@
+/gsa/ausgsa/projects/h/hostboot/eecache_prebuilt/06_19_19_eecache_prebuilt.bin.ecc
\ No newline at end of file
diff --git a/src/build/simics/standalone.simics b/src/build/simics/standalone.simics
index 0548c1b0e..b67d0a660 100755
--- a/src/build/simics/standalone.simics
+++ b/src/build/simics/standalone.simics
@@ -54,6 +54,13 @@ if ($hb_skip_vpd_preload == 0) {
     } except { echo "ERROR: Failed to preload VPD into PNOR." }
 }
 
+if ($hb_mode == 0) {
+    $eccPreload = (lookup-file "%simics%/eecache_prebuilt.bin.ecc")
+    # NOTE must change offset if PNOR layout changes EECACHE offsets
+    echo "    - Loading prebuilt EECACHE "+$eccPreload+" at 0x3E33000 in PNOR"
+    ($hb_pnor).load-file $eccPreload 0x3E33000
+}
+
 
 # Turn on all processor cec-chips
 if ($hb_mode == 1) {
diff --git a/src/include/usr/i2c/eeprom_const.H b/src/include/usr/i2c/eeprom_const.H
index ea09c4330..055aa2172 100644
--- a/src/include/usr/i2c/eeprom_const.H
+++ b/src/include/usr/i2c/eeprom_const.H
@@ -124,7 +124,10 @@ union eepromRecordHeader
         uint32_t cache_copy_size;   // Size of data saved in cache (in KB)
         uint32_t internal_offset;   // offset from start of EECACHE section where cached
                                     // data exists
-        uint8_t  cached_copy_valid; // if == 0 , cached data is invalid
+        uint8_t  cached_copy_valid : 1,   // This bit is set when we think the contents of the
+                                          // cache is valid.
+                 unused            : 7;
+
     } PACKED completeRecord;
 
     struct uniqueRecord
@@ -238,16 +241,24 @@ struct EepromInfo_t
 /**
  * @brief Define a set of information that describes the
           different virtual addresses associated with a given
-          cache entry
+          cache entry along with a byte telling us if there has been
+          an update detected on the eeprom this boot
  */
-struct RecordAddresses_t
+struct EeepromEntryMetaData_t
 {
     uint64_t header_entry_address;
     uint64_t cache_entry_address;
+    uint8_t  mark_target_changed;  // This byte is set after we detect a target has changed.
+                                   // Either removed, replaced, or added we don't care. But
+                                   // we need to use this bits so future targets associated
+                                   // with this eeprom can know they need to notify HWAS that
+                                   // they have been changed. This bit should get cleared after
+                                   // all eeproms have been cached.
 
-    RecordAddresses_t()
+    EeepromEntryMetaData_t()
       : header_entry_address(0),
-        cache_entry_address(0)
+        cache_entry_address(0),
+        mark_target_changed(0)
     {
     }
 };
diff --git a/src/include/usr/i2c/eepromddreasoncodes.H b/src/include/usr/i2c/eepromddreasoncodes.H
index df71e4be4..c08935ab4 100644
--- a/src/include/usr/i2c/eepromddreasoncodes.H
+++ b/src/include/usr/i2c/eepromddreasoncodes.H
@@ -90,7 +90,7 @@ enum eepromReasonCode
                                                                        // been installed on the system.
     EEPROM_CACHE_NOT_FOUND_IN_MAP           = EEPROM_COMP_ID | 0x0F,   // An entry we thought would be in the global map that keeps track of
                                                                        // what eeproms have been cached was not found
-    EEPROM_CACHE_NOT_FOUND_IN_PNOR           = EEPROM_COMP_ID | 0x10,  // An entry we thought would be in the the EECACHE section of PNOR seems
+    EEPROM_CACHE_NOT_FOUND_IN_PNOR          = EEPROM_COMP_ID | 0x10,   // An entry we thought would be in the the EECACHE section of PNOR seems
                                                                        // to be missing
 };
 
diff --git a/src/usr/i2c/eepromCache.C b/src/usr/i2c/eepromCache.C
index 35aced423..6993f35ee 100644
--- a/src/usr/i2c/eepromCache.C
+++ b/src/usr/i2c/eepromCache.C
@@ -30,6 +30,7 @@
 #include <devicefw/driverif.H>
 #include <errl/errlmanager.H>
 #include <fsi/fsiif.H>
+#include <hwas/hwasPlat.H>
 #include "i2c.H"
 #include "eepromCache.H"
 #include <i2c/i2cif.H>
@@ -64,9 +65,10 @@ uint64_t g_eecachePnorSize  = 0;
 // Global map which is used as a way to quickly look up the virtual address
 // of a given eeprom's cached data in EECACHE section
 // Key   = eepromRecordHeader with unique info filled out
-// Value = A struct of 2 virtual addresses , one points to header address
-//         and other points to the location of the cache
-std::map<eepromRecordHeader, RecordAddresses_t> g_cachedEeproms;
+// Value = A struct of 2 uint64_t virtual addresses ,one points to header address
+//         and other points to the location of the cache, and a byte indicating
+//         if this eeprom's hardware has changed this IPL
+std::map<eepromRecordHeader, EeepromEntryMetaData_t> g_cachedEeproms;
 
 // Any time we access either any of the global variables defined above we want
 // to wrap the call in this mutex to avoid multi-threading issues
@@ -75,7 +77,7 @@ mutex_t g_eecacheMutex = MUTEX_INITIALIZER;
 uint64_t lookupEepromCacheAddr(const eepromRecordHeader& i_eepromRecordHeader)
 {
     uint64_t l_vaddr = 0;
-    std::map<eepromRecordHeader, RecordAddresses_t>::iterator l_it;
+    std::map<eepromRecordHeader, EeepromEntryMetaData_t>::iterator l_it;
 
     // Wrap lookup in mutex because reads are not thread safe
     mutex_lock(&g_eecacheMutex);
@@ -86,29 +88,13 @@ uint64_t lookupEepromCacheAddr(const eepromRecordHeader& i_eepromRecordHeader)
     {
         l_vaddr = l_it->second.cache_entry_address;
     }
-
-    if(l_vaddr == 0)
-    {
-        TRACFCOMP( g_trac_eeprom,
-                   "lookupEepromCacheAddr() failed to find"
-                    " I2CM Huid: 0x%.08X, Port: 0x%.02X,"
-                    " Engine: 0x%.02X, Dev Addr: 0x%.02X,"
-                    " Mux Select: 0x%.02X, Size: 0x%.08X"
-                    " in g_cachedEeproms",
-                    i_eepromRecordHeader.completeRecord.i2c_master_huid,
-                    i_eepromRecordHeader.completeRecord.port,
-                    i_eepromRecordHeader.completeRecord.engine,
-                    i_eepromRecordHeader.completeRecord.devAddr,
-                    i_eepromRecordHeader.completeRecord.mux_select,
-                    i_eepromRecordHeader.completeRecord.cache_copy_size);
-    }
     return l_vaddr;
 }
 
 uint64_t lookupEepromHeaderAddr(const eepromRecordHeader& i_eepromRecordHeader)
 {
     uint64_t l_vaddr = 0;
-    std::map<eepromRecordHeader, RecordAddresses_t>::iterator l_it;
+    std::map<eepromRecordHeader, EeepromEntryMetaData_t>::iterator l_it;
 
     // Wrap lookup in mutex because reads are not thread safe
     mutex_lock(&g_eecacheMutex);
@@ -278,6 +264,58 @@ void printTableOfContents(void)
 
 }
 
+/**
+*
+* @brief Lookup a given i_eepromRecordHeader in the global map of eeprom
+*        caches and check if the eeprom has changed this IPL or not
+*
+* @param[in] i_eepromRecordHeader we want to look up
+*
+* @return bool Return TRUE if eeprom is found in map AND mark_target_changed
+               was set to true for the eeprom entry. Return FALSE otherwise.
+*
+*/
+bool hasEeepromChanged(const eepromRecordHeader & i_eepromRecordHeader)
+{
+    bool l_eepromHasChanged = false;
+
+    // Map accesses are not thread safe, make sure this is always wrapped in mutex
+    mutex_lock(&g_eecacheMutex);
+
+    if(g_cachedEeproms.find(i_eepromRecordHeader) != g_cachedEeproms.end())
+    {
+        l_eepromHasChanged = g_cachedEeproms[i_eepromRecordHeader].mark_target_changed;
+    }
+
+    mutex_unlock(&g_eecacheMutex);
+
+    return l_eepromHasChanged;
+}
+
+/**
+*
+* @brief Lookup a given i_eepromRecordHeader in the global map of eeprom
+*        caches and mark that it has changed this IPL
+*
+* @param[in] i_eepromRecordHeader we want to mark as changed
+*
+* @return void
+*/
+void setEeepromChanged(const eepromRecordHeader & i_eepromRecordHeader)
+{
+
+    // Map accesses are not thread safe, make sure this is always wrapped in mutex
+    mutex_lock(&g_eecacheMutex);
+
+    if(g_cachedEeproms.find(i_eepromRecordHeader) != g_cachedEeproms.end())
+    {
+        g_cachedEeproms[i_eepromRecordHeader].mark_target_changed = true;
+    }
+
+    mutex_unlock(&g_eecacheMutex);
+
+}
+
 bool addEepromToCachedList(const eepromRecordHeader & i_eepromRecordHeader,
                            const uint64_t i_recordHeaderVaddr)
 {
@@ -347,7 +385,10 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
         l_eepromInfo.eepromRole = i_eepromType;
 
         // if the target is present, then this record is valid
-        l_eepromRecordHeader.completeRecord.cached_copy_valid = i_present;
+        if(i_present)
+        {
+            l_eepromRecordHeader.completeRecord.cached_copy_valid = 1;
+        }
 
         // buildEepromRecordHeader will call eepromReadAttributes to fill in l_eepromInfo
         // with info looked up in attributes and also fill in l_eepromRecordHeader
@@ -502,7 +543,8 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
 
                     #ifdef CONFIG_CONSOLE
                         CONSOLE::displayf(EEPROM_COMP_NAME,
-                              "New EEPROM size detected for an existing part, clearing EEPROM cache and performing reconfig loop");
+                              "New EEPROM size detected for an existing part,"
+                              "clearing EEPROM cache and performing reconfig loop");
                     #endif
 
                     INITSERVICE::doShutdown(INITSERVICE::SHUTDOWN_DO_RECONFIG_LOOP);
@@ -514,7 +556,8 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
                         l_recordHeaderToUpdate->completeRecord.internal_offset;
 
                 TRACSSCOMP(g_trac_eeprom,
-                          "cacheEeprom() already found copy for eeprom role %d for target w/ HUID 0x.%08X",
+                          "cacheEeprom() already found copy for eeprom role %d "
+                          "for target w/ HUID 0x.%08X in EECACHE table of contents",
                           i_eepromType , TARGETING::get_huid(i_target));
                 break;
             }
@@ -527,14 +570,24 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
                                   reinterpret_cast<uint64_t>(l_recordHeaderToUpdate)))
         {
             TRACSSCOMP( g_trac_eeprom,
-                      "cacheEeprom() Eeprom w/ Role %d, HUID 0x.%08X added to cached list",
-                      i_eepromType , TARGETING::get_huid(i_target));
+                        "cacheEeprom() Eeprom w/ Role %d, HUID 0x.%08X added to the global map of cached eeproms",
+                        i_eepromType , TARGETING::get_huid(i_target));
         }
         else
         {
+            // If this target's eeprom has already been cached in PNOR and our global map
+            // indicates the cache entry was updated this boot, then  we must also
+            // mark this target associated with the cached eeprom as changed for hwas
+            if( hasEeepromChanged( l_eepromRecordHeader ) )
+            {
+                HWAS::markTargetChanged(i_target);
+            }
             TRACSSCOMP( g_trac_eeprom,
-                      "cacheEeprom() Eeprom w/ Role %d, HUID 0x.%08X already in cached list",
+                      "cacheEeprom() Eeprom w/ Role %d, HUID 0x.%08X already in global map of cached eeproms",
                       i_eepromType , TARGETING::get_huid(i_target));
+
+            // Cache entry has already been updated via another target, just break out
+            break;
         }
 
         // Only check if the cache is in sync with HARDWARE if there is an
@@ -574,11 +627,6 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
                            l_eepromVpd.eepromContentType);
             }
 
-            TRACSSCOMP(g_trac_eeprom,
-                       "cacheEeprom() Target 0x%.8X "
-                       "EEPROM_CONTENT_TYPE 0x%X",
-                       T::get_huid(i_target),
-                       l_eepromContentType);
 
             bool l_isInSync = false;
 
@@ -610,10 +658,27 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
                     reinterpret_cast<uint8_t *>(l_eecacheSectionHeaderPtr) +
                     l_eepromRecordHeader.completeRecord.internal_offset;
 
-                 memset( l_internalSectionAddr, 0xFF ,
+                memset( l_internalSectionAddr, 0xFF ,
                         (l_recordHeaderToUpdate->completeRecord.cache_copy_size * KILOBYTE));
 
-                 l_updateContents = false;
+                l_updateContents = false;
+
+                setIsValidCacheEntry(l_eepromRecordHeader, false);
+
+                TRACFCOMP( g_trac_eeprom, "Detected Master 0x%.08X"
+                           " Engine 0x%.02X Port 0x%.02X"
+                           " MuxSelect 0x%.02X DevAddr 0x%.02X"
+                           " no longer present, clearing cache and marking cache as invalid",
+                           l_recordHeaderToUpdate->completeRecord.i2c_master_huid,
+                           l_recordHeaderToUpdate->completeRecord.engine,
+                           l_recordHeaderToUpdate->completeRecord.port,
+                           l_recordHeaderToUpdate->completeRecord.mux_select,
+                           l_recordHeaderToUpdate->completeRecord.devAddr);
+
+                setEeepromChanged(l_eepromRecordHeader);
+                // We have cleared the cache entry, this indicates we have found a part has been removed.
+                // Mark that the target is changed in hwas.
+                HWAS::markTargetChanged(i_target);
             }
 
             // If target is present there is nothing in the
@@ -630,15 +695,34 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
             l_updateContents = false;
             l_updateHeader = false;
         }
+        // The check below makes sure that is isnt a new entry, because
+        // new entries do not have internal_offset set in header.
+        // If there is a matching header entry in PNOR marked 'invalid'
+        // but we now see the target as present, this indicates a replacement
+        // part has been added where a part was removed
+        else if(l_recordHeaderToUpdate->completeRecord.internal_offset != UNSET_INTERNAL_OFFSET_VALUE)
+        {
+            TRACFCOMP(g_trac_eeprom, "cacheEeprom() Detected replacement of a part"
+                      " Master 0x%.08X Engine 0x%.02X"
+                      " Port 0x%.02X MuxSelect 0x%.02X DevAddr 0x%.02X"
+                      " that was previously removed, we will update the cache with new part's eeproms contents",
+                      l_recordHeaderToUpdate->completeRecord.i2c_master_huid,
+                      l_recordHeaderToUpdate->completeRecord.engine,
+                      l_recordHeaderToUpdate->completeRecord.port,
+                      l_recordHeaderToUpdate->completeRecord.mux_select,
+                      l_recordHeaderToUpdate->completeRecord.devAddr);
+        }
 
         // Above we have determined whether the contents of the eeprom at
         // hand need to have their contents updated. Only do the following
         // steps that update the eeprom's cached data if we were told to do so.
-        if(l_updateContents )
+        if( l_updateContents )
         {
             assert(l_recordHeaderToUpdateIndex != INVALID_EEPROM_INDEX,
                     "More than MAX_EEPROMS_VERSION_1 in system XML");
 
+            TRACFCOMP( g_trac_eeprom, "cacheEeprom() updating cache entry");
+
             void * l_tmpBuffer;
 
             l_tmpBuffer = malloc(l_eepromLen);
@@ -704,13 +788,18 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
                 break;
             }
 
-            // If cache copy was not valid before, it is now valid, we must update the header
-            if (!l_recordHeaderToUpdate->completeRecord.cached_copy_valid)
-            {
-                  l_eepromRecordHeader.completeRecord.cached_copy_valid = 0x01;
-                  l_updateHeader = true;
-            }
-
+            // Set mark_target_changed and cached_copy_valid and update set updateHeader
+            // Since we have copied stuff in the cache is valid, and been updated.
+            // Even if this is a replacement ( cached_copy_valid was already 1) we
+            // must set mark_target_changed so just always update the header
+            setEeepromChanged(l_eepromRecordHeader);
+            // We will update header in PNOR below so no need to call
+            // setIsValidCacheEntry right here
+            l_eepromRecordHeader.completeRecord.cached_copy_valid = 1;
+            l_updateHeader = true;
+            // We have updated the cache entry, this indicates we have found a "new" part.
+            // Mark that the target is changed in hwas.
+            HWAS::markTargetChanged(i_target);
         }
 
         // Above we have determined whether the header entry for the eeprom at
@@ -718,6 +807,7 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
         // the eeprom's header entry if we were told to do so.
         if(l_updateHeader)
         {
+            TRACFCOMP( g_trac_eeprom, "cacheEeprom() updating header entry");
             TRACDBIN( g_trac_eeprom, "cacheEeprom: l_eecacheSectionHeaderPtr currently ",
                       l_eecacheSectionHeaderPtr,
                       sizeof(eecacheSectionHeader));
@@ -832,31 +922,43 @@ errlHndl_t setIsValidCacheEntry(const TARGETING::Target * i_target,
 {
     errlHndl_t l_errl = nullptr;
     eepromRecordHeader l_eepromRecordHeader;
-    eepromRecordHeader * l_eepromRecordHeaderToUpdate;
-    std::map<eepromRecordHeader, RecordAddresses_t>::iterator l_headerMapIterator;
-
     eeprom_addr_t l_eepromInfo;
-    l_eepromInfo.eepromRole = i_eepromRole;
 
     do{
 
-        TRACFCOMP( g_trac_eeprom, ENTER_MRK"setIsValidCacheEntry() "
+        TRACDCOMP( g_trac_eeprom, ENTER_MRK"setIsValidCacheEntry() "
                     "Target HUID 0x%.08X  Eeprom Role = %d  Enter",
                     TARGETING::get_huid(i_target), l_eepromInfo.eepromRole);
 
-        // Take the input paramters and use them to build a eeprom record header we can search with
-        l_errl = buildEepromRecordHeader(const_cast<TARGETING::Target *>(i_target),
-                                         l_eepromInfo,
-                                         l_eepromRecordHeader);
+        l_eepromInfo.eepromRole = i_eepromRole;
+        l_errl = buildEepromRecordHeader(const_cast<TARGETING::Target *>(i_target), l_eepromInfo, l_eepromRecordHeader);
 
         if(l_errl)
         {
             break;
         }
 
+        l_errl = setIsValidCacheEntry(l_eepromRecordHeader, i_isValid);
+
+    }while(0);
+
+    return l_errl;
+}
+
+errlHndl_t setIsValidCacheEntry(const eepromRecordHeader& i_eepromRecordHeader, bool i_isValid)
+{
+    errlHndl_t l_errl = nullptr;
+    eepromRecordHeader * l_eepromRecordHeaderToUpdate;
+    std::map<eepromRecordHeader, EeepromEntryMetaData_t>::iterator l_headerMapIterator;
+
+    do{
+
+        TRACDCOMP( g_trac_eeprom, ENTER_MRK"setIsValidCacheEntry() ");
+
+
         // Find the address of the header entry in the table of contents of the EECACHE pnor section
         l_eepromRecordHeaderToUpdate =
-            reinterpret_cast<eepromRecordHeader *>(lookupEepromHeaderAddr(l_eepromRecordHeader));
+            reinterpret_cast<eepromRecordHeader *>(lookupEepromHeaderAddr(i_eepromRecordHeader));
 
         if(l_eepromRecordHeaderToUpdate == 0)
         {
@@ -880,22 +982,22 @@ errlHndl_t setIsValidCacheEntry(const TARGETING::Target * i_target,
                               EEPROM_INVALIDATE_CACHE,
                               EEPROM_CACHE_NOT_FOUND_IN_MAP,
                               TWO_UINT32_TO_UINT64(
-                                  l_eepromRecordHeader.completeRecord.i2c_master_huid,
+                                  i_eepromRecordHeader.completeRecord.i2c_master_huid,
                                   TWO_UINT16_TO_UINT32(
                                       TWO_UINT8_TO_UINT16(
-                                          l_eepromRecordHeader.completeRecord.port,
-                                          l_eepromRecordHeader.completeRecord.engine),
+                                          i_eepromRecordHeader.completeRecord.port,
+                                          i_eepromRecordHeader.completeRecord.engine),
                                       TWO_UINT8_TO_UINT16(
-                                          l_eepromRecordHeader.completeRecord.devAddr,
-                                          l_eepromRecordHeader.completeRecord.mux_select))),
-                              l_eepromRecordHeader.completeRecord.cache_copy_size,
+                                          i_eepromRecordHeader.completeRecord.devAddr,
+                                          i_eepromRecordHeader.completeRecord.mux_select))),
+                              i_eepromRecordHeader.completeRecord.cache_copy_size,
                               ERRORLOG::ErrlEntry::ADD_SW_CALLOUT);
               break;
         }
 
         // Ensure that information at the address we just looked up matches the record we built up
         if( memcmp(&l_eepromRecordHeaderToUpdate->uniqueRecord.uniqueID,
-                   &l_eepromRecordHeader.uniqueRecord.uniqueID,
+                   &i_eepromRecordHeader.uniqueRecord.uniqueID,
                    NUM_BYTE_UNIQUE_ID ) != 0 )
         {
               TRACFCOMP(g_trac_eeprom,ERR_MRK"setIsValidCacheEntry:  Attempting to invalidate cache for an"
@@ -917,15 +1019,15 @@ errlHndl_t setIsValidCacheEntry(const TARGETING::Target * i_target,
                               EEPROM_INVALIDATE_CACHE,
                               EEPROM_CACHE_NOT_FOUND_IN_PNOR,
                               TWO_UINT32_TO_UINT64(
-                                  l_eepromRecordHeader.completeRecord.i2c_master_huid,
+                                  i_eepromRecordHeader.completeRecord.i2c_master_huid,
                                   TWO_UINT16_TO_UINT32(
                                       TWO_UINT8_TO_UINT16(
-                                          l_eepromRecordHeader.completeRecord.port,
-                                          l_eepromRecordHeader.completeRecord.engine),
+                                          i_eepromRecordHeader.completeRecord.port,
+                                          i_eepromRecordHeader.completeRecord.engine),
                                       TWO_UINT8_TO_UINT16(
-                                          l_eepromRecordHeader.completeRecord.devAddr,
-                                          l_eepromRecordHeader.completeRecord.mux_select))),
-                              l_eepromRecordHeader.completeRecord.cache_copy_size,
+                                          i_eepromRecordHeader.completeRecord.devAddr,
+                                          i_eepromRecordHeader.completeRecord.mux_select))),
+                              i_eepromRecordHeader.completeRecord.cache_copy_size,
                               ERRORLOG::ErrlEntry::ADD_SW_CALLOUT);
               break;
         }
diff --git a/src/usr/i2c/eepromCache.H b/src/usr/i2c/eepromCache.H
index fa0c340bd..9e0e140d8 100644
--- a/src/usr/i2c/eepromCache.H
+++ b/src/usr/i2c/eepromCache.H
@@ -151,6 +151,21 @@ errlHndl_t setIsValidCacheEntry(const TARGETING::Target * i_target,
 
 /**
 *
+* @brief Update the record entry in the Table of Contents of the EECACHE
+*        section of pnor to either mark the contents of the cache to be
+*        valid or invalid
+*
+* @param[in] i_eepromRecordHeader eepromRecord oject already filled in (including eepromRole)
+*
+* @param[in] i_isValid    Mark eeprom cache valid or invalid ? 
+*
+* @return errlHndl_t - nullptr if successful, otherwise a pointer to the
+*       error log.
+*
+*/
+errlHndl_t setIsValidCacheEntry(const eepromRecordHeader& i_eepromRecordHeader, bool i_isValid);
+/**
+*
 * @brief Print the info found in the Table of Contents of the EECACHE
 *        section of pnor to trace buffer
 *
diff --git a/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml b/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml
index 91b6d25a1..d47924115 100644
--- a/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_AXONE.system.xml
@@ -8498,6 +8498,9 @@
             <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field>
         </default>
     </attribute>
+    <!--The eeprom associated w/ this target is marked as invalid in the prebuilt
+    EECACHE pnor section. It is expected that we detect this target as a
+    replacement to a part thathad been previously removed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -8565,6 +8568,10 @@
             <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field>
         </default>
     </attribute>
+    <!--The eeprom associated w/ this target is marked as in the prebuilt
+        EECACHE pnor section but the contents of the cache entry are emtpy.
+        It is expected that we detect this target a mismatched PN/SN and
+        force a update of the eeprom's cache entry -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -8632,6 +8639,9 @@
             <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field>
         </default>
     </attribute>
+    <!--The eeprom associated w/ this target will not have an entry in the EECACHE
+         that we preload in standalone simics. It should look like a newly detected
+         eeprom entry-->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -8699,6 +8709,9 @@
             <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field>
         </default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics that has corrupted PN/SN keywords.
+         We should interpret the PN/SN mismatch and treat it as a replacment -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -8766,6 +8779,8 @@
             <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field>
         </default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics. No cache updates should be needed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -8833,6 +8848,8 @@
             <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field>
         </default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics. No cache updates should be needed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -8900,6 +8917,8 @@
             <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field>
         </default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics. No cache updates should be needed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -8967,6 +8986,8 @@
             <field><id>i2cMuxPath</id><value>physical:sys-0/node-0/i2c_mux-0</value></field>
         </default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics. No cache updates should be needed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -9034,6 +9055,8 @@
             <field><id>i2cMuxPath</id><value>physical:sys-0</value></field>
         </default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics. No cache updates should be needed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -10705,7 +10728,7 @@
 <!-- ===================================================================== -->
 <targetInstance>
     <id>sys0node0dimm0</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x00030000</default></attribute>
     <attribute><id>POSITION</id><default>0</default></attribute>
     <attribute>
@@ -10735,6 +10758,9 @@
         <id>VPD_REC_NUM</id>
         <default>0</default>
     </attribute>
+    <!--The eeprom associated w/ this target is marked as invalid in the prebuilt
+        EECACHE pnor section. It is expected that we detect this target as a
+        replacement to a part thathad been previously removed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -10757,7 +10783,7 @@
 
 <targetInstance>
     <id>sys0node0dimm1</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x00030001</default></attribute>
     <attribute><id>POSITION</id><default>1</default></attribute>
     <attribute>
@@ -10787,6 +10813,10 @@
         <id>VPD_REC_NUM</id>
         <default>1</default>
     </attribute>
+    <!--The eeprom associated w/ this target is marked as in the prebuilt
+        EECACHE pnor section but the contents of the cache entry are emtpy.
+        It is expected that we detect this target a mismatched PN/SN and
+        force a update of the eeprom's cache entry -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -10809,7 +10839,7 @@
 
 <targetInstance>
     <id>sys0node0dimm2</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x00030002</default></attribute>
     <attribute><id>POSITION</id><default>2</default></attribute>
     <attribute>
@@ -10839,6 +10869,9 @@
         <id>VPD_REC_NUM</id>
         <default>2</default>
     </attribute>
+    <!--The eeprom associated w/ this target will not have an entry in the EECACHE
+         that we preload in standalone simics. It should look like a newly detected
+         eeprom entry-->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -10861,7 +10894,7 @@
 
 <targetInstance>
     <id>sys0node0dimm3</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x00030003</default></attribute>
     <attribute><id>POSITION</id><default>3</default></attribute>
     <attribute>
@@ -10891,6 +10924,9 @@
         <id>VPD_REC_NUM</id>
         <default>3</default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics that has corrupted PN/SN keywords.
+         We should interpret the PN/SN mismatch and treat it as a replacment -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -10913,7 +10949,7 @@
 
 <targetInstance>
     <id>sys0node0dimm4</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x00030004</default></attribute>
     <attribute><id>POSITION</id><default>4</default></attribute>
     <attribute>
@@ -10943,6 +10979,8 @@
         <id>VPD_REC_NUM</id>
         <default>4</default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics. No cache updates should be needed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -10965,7 +11003,7 @@
 
 <targetInstance>
     <id>sys0node0dimm5</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x00030005</default></attribute>
     <attribute><id>POSITION</id><default>5</default></attribute>
     <attribute>
@@ -10995,6 +11033,8 @@
         <id>VPD_REC_NUM</id>
         <default>5</default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics. No cache updates should be needed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -11017,7 +11057,7 @@
 
 <targetInstance>
     <id>sys0node0dimm6</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x00030006</default></attribute>
     <attribute><id>POSITION</id><default>6</default></attribute>
     <attribute>
@@ -11047,6 +11087,8 @@
         <id>REL_POS</id>
         <default>0</default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics. No cache updates should be needed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -11069,7 +11111,7 @@
 
 <targetInstance>
     <id>sys0node0dimm7</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x00030007</default></attribute>
     <attribute><id>POSITION</id><default>7</default></attribute>
     <attribute>
@@ -11099,6 +11141,8 @@
         <id>VPD_REC_NUM</id>
         <default>7</default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics. No cache updates should be needed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -11121,7 +11165,7 @@
 
 <targetInstance>
     <id>sys0node0dimm8</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x00030008</default></attribute>
     <attribute><id>POSITION</id><default>8</default></attribute>
     <attribute>
@@ -11151,6 +11195,8 @@
         <id>VPD_REC_NUM</id>
         <default>8</default>
     </attribute>
+    <!--The eeprom associated w/ this target will have a valid entry in the EECACHE
+         that we preload in standalone simics. No cache updates should be needed -->
     <attribute>
         <id>EEPROM_VPD_PRIMARY_INFO</id>
         <default>
@@ -11172,7 +11218,7 @@
 
 <targetInstance>
     <id>sys0node0dimm9</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x00030009</default></attribute>
     <attribute><id>POSITION</id><default>9</default></attribute>
     <attribute>
@@ -11225,7 +11271,7 @@
 
 <targetInstance>
     <id>sys0node0dimm10</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x0003000A</default></attribute>
     <attribute><id>POSITION</id><default>10</default></attribute>
     <attribute>
@@ -11278,7 +11324,7 @@
 
 <targetInstance>
     <id>sys0node0dimm11</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x0003000B</default></attribute>
     <attribute><id>POSITION</id><default>11</default></attribute>
     <attribute>
@@ -11329,7 +11375,7 @@
 
 <targetInstance>
     <id>sys0node0dimm12</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x0003000C</default></attribute>
     <attribute><id>POSITION</id><default>12</default></attribute>
     <attribute>
@@ -11380,7 +11426,7 @@
 
 <targetInstance>
     <id>sys0node0dimm13</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x0003000D</default></attribute>
     <attribute><id>POSITION</id><default>13</default></attribute>
     <attribute>
@@ -11431,7 +11477,7 @@
 
 <targetInstance>
     <id>sys0node0dimm14</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x0003000E</default></attribute>
     <attribute><id>POSITION</id><default>14</default></attribute>
     <attribute>
@@ -11482,7 +11528,7 @@
 
 <targetInstance>
     <id>sys0node0dimm15</id>
-    <type>lcard-dimm-jedec</type>
+    <type>lcard-dimm-ddimm</type>
     <attribute><id>HUID</id><default>0x0003000F</default></attribute>
     <attribute><id>POSITION</id><default>15</default></attribute>
     <attribute>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 0b46660ff..fe2219b53 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1547,6 +1547,63 @@
   <targetType>
     <id>lcard-dimm-ddimm</id>
     <parent>lcard-dimm</parent>
+    <attribute>
+      <default>
+        <field>
+          <value>0xFF</value>
+          <id>byteAddrOffset</id>
+        </field>
+        <field>
+          <value>0xFF</value>
+          <id>chipCount</id>
+        </field>
+        <field>
+          <value>0xFF</value>
+          <id>devAddr</id>
+        </field>
+        <field>
+          <!--Since enum values cannot be used as default values in
+                  a complexType, this is a workaround to set the value to the
+                  corresponding enum value.-->
+          <!--value>DDIMM</value-->
+          <value>0x4</value>
+          <id>eepromContentType</id>
+        </field>
+        <field>
+          <value>0xFF</value>
+          <id>engine</id>
+        </field>
+        <field>
+          <value>physical:sys-0</value>
+          <id>i2cMasterPath</id>
+        </field>
+        <field>
+          <value>0xFF</value>
+          <id>i2cMuxBusSelector</id>
+        </field>
+        <field>
+          <value>physical:sys-0</value>
+          <id>i2cMuxPath</id>
+        </field>
+        <field>
+          <value>0xFFFFFFFFFFFFFFFF</value>
+          <id>maxMemorySizeKB</id>
+        </field>
+        <field>
+          <value>0xFF</value>
+          <id>port</id>
+        </field>
+        <field>
+          <value>0xFFFFFFFFFFFFFFFF</value>
+          <id>writeCycleTime</id>
+        </field>
+        <field>
+          <value>0xFFFFFFFFFFFFFFFF</value>
+          <id>writePageSize</id>
+        </field>
+      </default>
+      <id>EEPROM_VPD_PRIMARY_INFO</id>
+    </attribute>
   </targetType>
 
   <targetType>
diff --git a/src/usr/vpd/ocmb_spd.C b/src/usr/vpd/ocmb_spd.C
index 567ab43b1..442eb3672 100644
--- a/src/usr/vpd/ocmb_spd.C
+++ b/src/usr/vpd/ocmb_spd.C
@@ -209,7 +209,9 @@ errlHndl_t ocmbFetchData(T::TargetHandle_t    i_target,
     errlHndl_t err = nullptr;
 
     TRACSSCOMP(g_trac_spd,
-               ENTER_MRK"ocmbFetchData()" );
+               ENTER_MRK"ocmbFetchData()"
+               " i_byteAddr = 0x%x i_numBytes = %d i_location = 0x%x",
+               i_byteAddr, i_numBytes, i_location);
 
     do
     {
diff --git a/src/usr/vpd/spd.C b/src/usr/vpd/spd.C
index 52f603310..692af5828 100644
--- a/src/usr/vpd/spd.C
+++ b/src/usr/vpd/spd.C
@@ -2317,6 +2317,10 @@ errlHndl_t readFromEepromSource(TARGETING::Target*          i_target,
 {
     errlHndl_t err = nullptr;
 
+    TRACSSCOMP(g_trac_spd, ENTER_MRK
+               "readFromEepromSource: i_eepromSource %d , i_memType %d, i_eepromType %d",
+               i_eepromSource, i_memType, i_eepromType);
+
 // @TODO RTC 204341 Implement for runtime
 #ifndef __HOSTBOOT_RUNTIME
     if (i_eepromType == TARGETING::EEPROM_CONTENT_TYPE_ISDIMM)
@@ -2485,6 +2489,9 @@ errlHndl_t cmpEecacheToEeprom(TARGETING::Target * i_target,
 
     } while(0);
 
+    TRACDBIN(g_trac_spd, "Hardware data : ", dataHardware, sizeHardware);
+    TRACDBIN(g_trac_spd, "Cache data : ", dataCache, sizeCache);
+
     TRACSSCOMP( g_trac_spd, EXIT_MRK"cmpEecacheToEeprom(): returning %s errors. o_match = 0x%X ",
                 (err ? "with" : "with no"), o_match );
 
diff --git a/src/usr/vpd/vpd.C b/src/usr/vpd/vpd.C
index a749ff9ec..bae60f483 100755
--- a/src/usr/vpd/vpd.C
+++ b/src/usr/vpd/vpd.C
@@ -786,9 +786,12 @@ errlHndl_t ensureEepromCacheIsInSync(TARGETING::Target           * i_target,
             TRACFCOMP(g_trac_vpd,
                       "VPD::ensureEepromCacheIsInSync: CACHE_PN/SN != HARDWARE_PN/SN,CACHE must be loaded from HARDWARE for target %.8X",
                       TARGETING::get_huid(i_target));
-
+#ifndef CONFIG_SUPPORT_EEPROM_CACHING
             //Set the targets as changed since the p/n's don't match
             HWAS::markTargetChanged(i_target);
+#else
+            //No need to mark target changed here, it will be handled by eecache code
+#endif
         }
 
     } while(0);