Change ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING name

Change to ATTR_MRW_HW_MIRRORING_ENABLE and invert its meaning to
make it more straight forward.

Change-Id: I0e63d52285a10bb1e8c75d4ff2598f0c50eab6de
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28536
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28538
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Tested-by: Stephen M. Cprek <smcprek@us.ibm.com>

7 files changed, 30 insertions, 31 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
index 92e729793..1dc4e9c78 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C
@@ -106,7 +106,7 @@ struct EffGroupingSysAttrs
 
     // Public data
     uint8_t iv_selectiveMode = 0;        // ATTR_MEM_MIRROR_PLACEMENT_POLICY
-    uint8_t iv_enhancedNoMirrorMode = 0; // ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING
+    uint8_t iv_hwMirrorEnabled = 0;      // ATTR_MRW_HW_MIRRORING_ENABLE
     uint8_t iv_fabricAddrBarMode = 0;    // ATTR_PROC_FABRIC_ADDR_BAR_MODE
     uint8_t iv_groupsAllowed = 0;        // ATTR_MSS_INTERLEAVE_ENABLE
 };
@@ -125,10 +125,10 @@ fapi2::ReturnCode EffGroupingSysAttrs::getAttrs()
              "Error getting ATTR_MEM_MIRROR_PLACEMENT_POLICY, l_rc 0x%.8X",
              (uint64_t)fapi2::current_err);
 
-    // Get enhanced grouping option
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING,
-                           FAPI_SYSTEM, iv_enhancedNoMirrorMode),
-             "Error getting ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING, l_rc 0x%.8X",
+    // Get mirror option
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MRW_HW_MIRRORING_ENABLE,
+                           FAPI_SYSTEM, iv_hwMirrorEnabled),
+             "Error getting ATTR_MRW_HW_MIRRORING_ENABLE, l_rc 0x%.8X",
              (uint64_t)fapi2::current_err);
 
     // Get Fabric address BAR mode
@@ -146,7 +146,7 @@ fapi2::ReturnCode EffGroupingSysAttrs::getAttrs()
     // Display attribute values
     FAPI_INF("EffGroupingSysAttrs: ");
     FAPI_INF("   ATTR_MEM_MIRROR_PLACEMENT_POLICY 0x%.8X", iv_selectiveMode);
-    FAPI_INF("   ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING 0x%.8X", iv_enhancedNoMirrorMode);
+    FAPI_INF("   ATTR_MRW_HW_MIRRORING_ENABLE 0x%.8X", iv_hwMirrorEnabled);
     FAPI_INF("   ATTR_PROC_FABRIC_ADDR_BAR_MODE 0x%.8X", iv_fabricAddrBarMode);
     FAPI_INF("   ATTR_MSS_INTERLEAVE_ENABLE 0x%.8X", iv_groupsAllowed);
 
@@ -773,7 +773,7 @@ void EffGroupingBaseSizeData::setBaseSizeData(
     }
 
     // Process mirrored ranges
-    if (!i_sysAttrs.iv_enhancedNoMirrorMode)
+    if (i_sysAttrs.iv_hwMirrorEnabled)
     {
         for (uint8_t ii = 0; ii < NUM_MIRROR_REGIONS; ii++)
         {
@@ -1145,7 +1145,7 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setBaseSizeAttr(
              (uint64_t)fapi2::current_err);
 
     // Mirror mode attribute setting
-    if (!i_sysAttrs.iv_enhancedNoMirrorMode)
+    if (i_sysAttrs.iv_hwMirrorEnabled)
     {
 
         // Set ATTR_PROC_MIRROR_BASES
@@ -1195,7 +1195,7 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setBaseSizeAttr(
     FAPI_INF("ATTR_PROC_OCC_SANDBOX_BASE_ADDR: 0x%.16llX", iv_occ_sandbox_base);
 
     // Display mirror mode attribute values
-    if (!i_sysAttrs.iv_enhancedNoMirrorMode)
+    if (i_sysAttrs.iv_hwMirrorEnabled)
     {
         for (uint8_t ii = 0; ii < NUM_MIRROR_REGIONS; ii++)
         {
@@ -1261,13 +1261,12 @@ fapi2::ReturnCode grouping_checkValidAttributes(
     fapi2::ReturnCode l_rc;
 
     // If mirror is disabled, then can not be in FLIPPED mode
-    if (i_sysAttrs.iv_enhancedNoMirrorMode)
+    if (!i_sysAttrs.iv_hwMirrorEnabled)
     {
         FAPI_ASSERT(i_sysAttrs.iv_selectiveMode !=
                     fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED,
                     fapi2::MSS_EFF_CONFIG_MIRROR_DISABLED()
-                    .set_MRW_ENHANCED_GROUPING_NO_MIRRORING(
-                        i_sysAttrs.iv_enhancedNoMirrorMode)
+                    .set_MRW_HW_MIRRORING_ENABLE(i_sysAttrs.iv_hwMirrorEnabled)
                     .set_MIRROR_PLACEMENT_POLICY(i_sysAttrs.iv_selectiveMode),
                     "grouping_checkValidAttributes: Error: Mirroring disabled "
                     "but ATTR_MEM_MIRROR_PLACEMENT_POLICY is in FLIPPED mode");
@@ -2442,7 +2441,7 @@ void grouping_traceData(const EffGroupingSysAttrs& i_sysAttrs,
     }
 
     // Display mirror groups
-    if (!i_sysAttrs.iv_enhancedNoMirrorMode)
+    if (i_sysAttrs.iv_hwMirrorEnabled)
     {
         for (uint8_t ii = 0; ii < i_groupData.iv_numGroups; ii++)
         {
@@ -2590,7 +2589,7 @@ fapi2::ReturnCode p9_mss_eff_grouping(
 
     FAPI_INF("Total non-mirrored size %u GB", l_groupData.iv_totalSizeNonMirr);
 
-    if (!l_sysAttrs.iv_enhancedNoMirrorMode)
+    if (l_sysAttrs.iv_hwMirrorEnabled)
     {
         // Calculate base and alt-base addresses
         FAPI_TRY(grouping_calcMirrorMemory(i_target, l_procAttrs, l_groupData),
@@ -2599,7 +2598,7 @@ fapi2::ReturnCode p9_mss_eff_grouping(
     }
     else
     {
-        // ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING is true
+        // ATTR_MRW_HW_MIRRORING_ENABLE is false
         // Calculate base and alt-base addresses
         grouping_calcNonMirrorMemory(l_procAttrs, l_groupData);
     }
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
index 5361fb520..cfb2772bc 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C
@@ -1062,7 +1062,7 @@ fapi2::ReturnCode p9_mss_setup_bars(
 {
     FAPI_DBG("Entering");
     fapi2::ReturnCode l_rc;
-    uint8_t l_enhancedNoMirrorMode = 0;
+    uint8_t l_hwMirrorEnabled = 0;
     uint8_t l_mem_ipl_complete = 1;
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
 
@@ -1099,9 +1099,9 @@ fapi2::ReturnCode p9_mss_setup_bars(
              (uint64_t)fapi2::current_err);
 
     // Get mirror policy
-    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING,
-                           FAPI_SYSTEM, l_enhancedNoMirrorMode),
-             "Error getting ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING, "
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MRW_HW_MIRRORING_ENABLE,
+                           FAPI_SYSTEM, l_hwMirrorEnabled),
+             "Error getting ATTR_MRW_HW_MIRRORING_ENABLE, "
              "l_rc 0x%.8X", (uint64_t)fapi2::current_err);
 
     // Setup BAR for Nimbus
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
index d941e4a6f..136f370b5 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml
@@ -927,13 +927,12 @@
 </attribute>
 <!-- ********************************************************************** -->
 <attribute>
-    <id>ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING</id>
+    <id>ATTR_MRW_HW_MIRRORING_ENABLE</id>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>
-       If this attribute sets to TRUE, supports MCS grouping  with out mirroring.
-       If this attribute to FALSE, IBM Power system Mirroring support enabled.
-       This instructs the grouping code to group contiguous memory controllers
-       of the same size together. Provided by the MRW.
+       TRUE : HW mirroring is enabled.
+       FALSE : HW mirroring is disabled.
+       Provided by the MRW.
     </description>
     <valueType>uint8</valueType>
     <platInit/>
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
index fed8d83c7..e0577b94b 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml
@@ -32,10 +32,10 @@
     <description>
         Mirroring is disabled but Mirror placement policy is flipped.
         Firmware error.
-        - ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING is true
+        - ATTR_MRW_HW_MIRRORING_ENABLE is true
         - ATTR_MEM_MIRROR_PLACEMENT_POLICY is FLIPPED
     </description>
-    <ffdc>MRW_ENHANCED_GROUPING_NO_MIRRORING</ffdc>
+    <ffdc>MRW_HW_MIRRORING_ENABLE</ffdc>
     <ffdc>MIRROR_PLACEMENT_POLICY</ffdc>
     <callout>
       <procedure>CODE</procedure>
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index b0c65fa66..0b5836224 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -289,7 +289,6 @@ push @systemAttr,
         $reqPol->{'vmem_regulator_memory_power_limit_per_dimm'},
     "PM_SYSTEM_IVRMS_ENABLED", $reqPol->{'pm_system_ivrms_enabled'},
     "PM_SYSTEM_IVRM_VPD_MIN_LEVEL", $reqPol->{'pm_system_ivrm_vpd_min_level'},
-    "MRW_ENHANCED_GROUPING_NO_MIRRORING", $reqPol->{'mcs_enhanced_grouping_no_mirroring'},
     "MRW_STRICT_MBA_PLUG_RULE_CHECKING", $reqPol->{'strict_mba_plug_rule_checking'},
     "MNFG_DMI_MIN_EYE_WIDTH", $reqPol->{'mnfg-dmi-min-eye-width'},
     "MNFG_DMI_MIN_EYE_HEIGHT", $reqPol->{'mnfg-dmi-min-eye-height'},
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 88504d8d5..e78024f3a 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -15919,9 +15919,11 @@ DEPRECATED!!!!
 </attribute>
 
 <attribute>
-    <id>MRW_ENHANCED_GROUPING_NO_MIRRORING</id>
+    <id>MRW_HW_MIRRORING_ENABLE</id>
     <description>
-       The MRW for a system should set this to TRUE for systems that do not want to suport MCS groupings larget than 2.  Mirroring  also must be disabled and is unusable. IBM systems, such as Tuleta, should set this attribute to FALSE.  Stradale based systems should set this to TRUE.  This instructs the grouping code to group contiguous memory controllers of the same size together.
+       0 : HW mirroring is disabled.
+       1 : HW mirroring is enabled.
+       Provided by the MRW.
     </description>
     <simpleType>
         <uint8_t></uint8_t>
@@ -15929,7 +15931,7 @@ DEPRECATED!!!!
     <persistency>non-volatile</persistency>
     <readable/>
     <hwpfToHbAttrMap>
-        <id>ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING</id>
+        <id>ATTR_MRW_HW_MIRRORING_ENABLE</id>
         <macro>DIRECT</macro>
     </hwpfToHbAttrMap>
 </attribute>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index e9a4debcc..9babc1df1 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -644,7 +644,7 @@
     <attribute><id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id></attribute>
     <attribute><id>PM_SYSTEM_IVRMS_ENABLED</id></attribute>
     <attribute><id>PM_SYSTEM_IVRM_VPD_MIN_LEVEL</id></attribute>
-    <attribute><id>MRW_ENHANCED_GROUPING_NO_MIRRORING</id></attribute>
+    <attribute><id>MRW_HW_MIRRORING_ENABLE</id></attribute>
     <attribute><id>MRW_STRICT_MBA_PLUG_RULE_CHECKING</id></attribute>
     <attribute><id>MNFG_DMI_MIN_EYE_WIDTH</id></attribute>
     <attribute><id>MNFG_DMI_MIN_EYE_HEIGHT</id></attribute>