diff options
| author | Joe Dery <dery@us.ibm.com> | 2016-06-30 10:58:36 -0400 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-02-23 14:48:56 -0500 |
| commit | 2b9f7628eed5f602c104fde6a2459d06add71794 (patch) | |
| tree | bfcbc887b9b8df31fd908a02f5054c2054d4cd78 | |
| parent | 8c7b26e89a59333b6e823ccafe07495f6ab6cd40 (diff) | |
| download | talos-hostboot-2b9f7628eed5f602c104fde6a2459d06add71794.tar.gz talos-hostboot-2b9f7628eed5f602c104fde6a2459d06add71794.zip | |
p9_sbe_chiplet_reset Level 2 update: set EC/core multicast reg3=group3
replace MCGR[0..3]_CNFG_SETTINGS and MCGR[234]_CACHE_CNFG_SETTINGS
with complete set MCGR_CNFG_SETTING_GROUP[0..6] for human readability
likewise comments now reflect that REGISTERs are being set to those SETTINGS
ideally the PERV_MULTICAST_GROUP_[1..4] would be changed to better clarify,
but these exist in a global header based on the vhdl/figtree descriptions
Change-Id: If89768eb8a49566762fce1fc188e1f03a10c5f53
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26466
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36941
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H index 3d20cedbc..731cf1a90 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -53,10 +53,13 @@ namespace p9SbeChipletReset { enum P9_SBE_CHIPLET_RESET_Public_Constants { - MCGR0_CNFG_SETTINGS = 0xE0001C0000000000ull, - MCGR1_CNFG_SETTINGS = 0xE4001C0000000000ull, - MCGR2_CNFG_SETTINGS = 0xE8001C0000000000ull, - MCGR3_CNFG_SETTINGS = 0xEC001C0000000000ull, + MCGR_CNFG_SETTING_GROUP0 = 0xE0001C0000000000ull, + MCGR_CNFG_SETTING_GROUP1 = 0xE4001C0000000000ull, + MCGR_CNFG_SETTING_GROUP2 = 0xE8001C0000000000ull, + MCGR_CNFG_SETTING_GROUP3 = 0xEC001C0000000000ull, + MCGR_CNFG_SETTING_GROUP4 = 0xF0001C0000000000ull, + MCGR_CNFG_SETTING_GROUP5 = 0xF4001C0000000000ull, + MCGR_CNFG_SETTING_GROUP6 = 0xF8001C0000000000ull, NET_CNTL0_HW_INIT_VALUE = 0x7C16222000000000ull, HANG_PULSE_0X10 = 0x10, HANG_PULSE_0X0F = 0x0F, @@ -77,9 +80,6 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants HANG_PULSE_0X04 = 0x04, HANG_PULSE_0X1A = 0x1A, NET_CNTL1_HW_INIT_VALUE = 0x7200000000000000ull, - MCGR2_CACHE_CNFG_SETTINGS = 0xF0001C0000000000ull, - MCGR3_CACHE_CNFG_SETTINGS = 0xF4001C0000000000ull, - MCGR4_CACHE_CNFG_SETTINGS = 0xF8001C0000000000ull, REGIONS_EXCEPT_VITAL = 0x7FF, SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCE, SCAN_TYPES_TIME_GPTR_REPR = 0x230, |
