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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2016-08-26 15:08:52 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-06-08 12:26:35 -0400 |
| commit | 25f2352f182e610d1f3097484133167f623926fa (patch) | |
| tree | d5706ee4b5229d213bea212f251e2bc682ecf1ea | |
| parent | 3e223a4466e9ab93d6fe271c108b101b05b22bcf (diff) | |
| download | talos-hostboot-25f2352f182e610d1f3097484133167f623926fa.tar.gz talos-hostboot-25f2352f182e610d1f3097484133167f623926fa.zip | |
Modifying ATTRs for memory power thermal
Added MSS_MRW_ATTRs to base_hwp_file, implemented bulk_pwr and
utils_to_throttle APIs for the OCC team. Added simple structural changes
Change-Id: I3290a9dacfcd3ab8345cfeb859eda35b52b8c28f
Original-Change-Id: I9483be7f06c95c8c4dfe4823443052efde6fa776
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28916
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41507
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.H | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.H index ab8d051e9..761b1d3e6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.H @@ -30,28 +30,30 @@ /// allowed within a window of M DRAM clocks given the minimum dram data bus utilization. /// -// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> // *HWP HWP Backup: Brian Silver <bsilver@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 2 +// *HWP Level: 1 // *HWP Consumed by: FSP:HB #ifndef __P9_MSS_UTILS_TO_THROTTLE__ #define __P9_MSS_UTILS_TO_THROTTLE__ #include <fapi2.H> +#include <vector> -typedef fapi2::ReturnCode (*p9_mss_utils_to_throttle_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MCS>&); +typedef fapi2::ReturnCode (*p9_mss_utils_to_throttle_FP_t) (const + std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCS> >&); extern "C" { /// /// @brief Set the N throttle attributes for a given dram data bus utilization. -/// @param[in] i_target the controller target +/// @param[in] i_targets vector of MCS on the same VDDR domain /// @return FAPI2_RC_SUCCESS iff ok -/// - fapi2::ReturnCode p9_mss_utils_to_throttle( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target ); +/// @note throttle_per_slot will be equalized so all throttles coming out will be equal to worst case + fapi2::ReturnCode p9_mss_utils_to_throttle( const std::vector <fapi2::Target<fapi2::TARGET_TYPE_MCS> >& i_targets ); } #endif |
