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authorMatt Derksen <mderkse1@us.ibm.com>2019-04-02 16:59:58 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2019-04-19 10:17:42 -0500
commit2431563fb687e2cafeb2bd4739302542c4fe8430 (patch)
treed8e973c5bb5e1c1ea2d65ecbad724b0fb6f86808
parent8112a619ebf4861f3f85226de3e8dfd79cc43a5f (diff)
downloadtalos-hostboot-2431563fb687e2cafeb2bd4739302542c4fe8430.zip
talos-hostboot-2431563fb687e2cafeb2bd4739302542c4fe8430.tar.gz
Remove DJVPD and CVPD sections from axone pnor layout
Remove unneeded Centaur VPD and DIMM JEDEC VPD sections to help reduce axone pnor memory space. Hit a simics issue where sysmvpd.data.ecc size was overwriting the first four 4-byte words of HBB, so procmvpd_p9a.dat size was corrected to 64KB. procmvpd_p9c.dat had same issue, but the overwrite was being corrected by a following CVPD write. Change-Id: I70eb12709be0ac7b73609fb080d956ee2faa39a2 RTC:207995 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75896 Reviewed-by: Glenn Miles <milesg@ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
-rw-r--r--src/build/buildpnor/pnorLayoutAxone.xml66
-rwxr-xr-xsrc/build/mkrules/hbfw/img/makefile16
-rwxr-xr-xsrc/build/simics/standalone.simics29
-rw-r--r--src/usr/pnor/test/pnorrptest.H10
-rw-r--r--src/usr/vpd/makefile4
5 files changed, 61 insertions, 64 deletions
diff --git a/src/build/buildpnor/pnorLayoutAxone.xml b/src/build/buildpnor/pnorLayoutAxone.xml
index 4420b8c..150bab1 100644
--- a/src/build/buildpnor/pnorLayoutAxone.xml
+++ b/src/build/buildpnor/pnorLayoutAxone.xml
@@ -94,36 +94,18 @@ Layout Description
<ecc/>
</section>
<section>
- <description>DIMM JEDEC (288K)</description>
- <eyeCatch>DJVPD</eyeCatch>
- <!--NOTE: MUST update standalone.simics if offset changes -->
- <physicalOffset>0x31000</physicalOffset>
- <physicalRegionSize>0x48000</physicalRegionSize>
- <side>sideless</side>
- <ecc/>
- </section>
- <section>
<description>Module VPD (576K)</description>
<eyeCatch>MVPD</eyeCatch>
<!--NOTE: MUST update standalone.simics if offset changes -->
- <physicalOffset>0x79000</physicalOffset>
+ <physicalOffset>0x31000</physicalOffset>
<physicalRegionSize>0x90000</physicalRegionSize>
<side>sideless</side>
<ecc/>
</section>
<section>
- <description>Centaur VPD (288K)</description>
- <eyeCatch>CVPD</eyeCatch>
- <!--NOTE: MUST update standalone.simics if offset changes -->
- <physicalOffset>0x109000</physicalOffset>
- <physicalRegionSize>0x48000</physicalRegionSize>
- <side>sideless</side>
- <ecc/>
- </section>
- <section>
<description>Hostboot Base (1MB)</description>
<eyeCatch>HBB</eyeCatch>
- <physicalOffset>0x151000</physicalOffset>
+ <physicalOffset>0xC1000</physicalOffset>
<physicalRegionSize>0x100000</physicalRegionSize>
<side>sideless</side>
<sha512Version/>
@@ -132,7 +114,7 @@ Layout Description
<section>
<description>Hostboot Data (2MB)</description>
<eyeCatch>HBD</eyeCatch>
- <physicalOffset>0x251000</physicalOffset>
+ <physicalOffset>0x1C1000</physicalOffset>
<physicalRegionSize>0x200000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
@@ -141,7 +123,7 @@ Layout Description
<section>
<description>Hostboot Extended image (14.22MB w/o ECC)</description>
<eyeCatch>HBI</eyeCatch>
- <physicalOffset>0x451000</physicalOffset>
+ <physicalOffset>0x3C1000</physicalOffset>
<physicalRegionSize>0x1000000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
@@ -150,7 +132,7 @@ Layout Description
<section>
<description>SBE-IPL (Staging Area) (752K)</description>
<eyeCatch>SBE</eyeCatch>
- <physicalOffset>0x1451000</physicalOffset>
+ <physicalOffset>0x13C1000</physicalOffset>
<physicalRegionSize>0xBC000</physicalRegionSize>
<sha512perEC/>
<sha512Version/>
@@ -160,7 +142,7 @@ Layout Description
<section>
<description>HCODE Ref Image (1.125MB)</description>
<eyeCatch>HCODE</eyeCatch>
- <physicalOffset>0x150D000</physicalOffset>
+ <physicalOffset>0x147D000</physicalOffset>
<physicalRegionSize>0x120000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
@@ -169,7 +151,7 @@ Layout Description
<section>
<description>Hostboot Runtime Services for Sapphire (7.0MB)</description>
<eyeCatch>HBRT</eyeCatch>
- <physicalOffset>0x162D000</physicalOffset>
+ <physicalOffset>0x159D000</physicalOffset>
<physicalRegionSize>0x700000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
@@ -178,7 +160,7 @@ Layout Description
<section>
<description>Payload (19.875MB)</description>
<eyeCatch>PAYLOAD</eyeCatch>
- <physicalOffset>0x1D2D000</physicalOffset>
+ <physicalOffset>0x1C9D000</physicalOffset>
<physicalRegionSize>0x13E0000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
@@ -187,7 +169,7 @@ Layout Description
<section>
<description>Special PNOR Test Space (36K)</description>
<eyeCatch>TEST</eyeCatch>
- <physicalOffset>0x310D000</physicalOffset>
+ <physicalOffset>0x307D000</physicalOffset>
<physicalRegionSize>0x9000</physicalRegionSize>
<testonly/>
<side>sideless</side>
@@ -198,7 +180,7 @@ Layout Description
from skipping header. Signing is forced in build pnor phase -->
<description>Special PNOR Test Space with Header (36K)</description>
<eyeCatch>TESTRO</eyeCatch>
- <physicalOffset>0x3116000</physicalOffset>
+ <physicalOffset>0x3086000</physicalOffset>
<physicalRegionSize>0x9000</physicalRegionSize>
<side>sideless</side>
<testonly/>
@@ -209,7 +191,7 @@ Layout Description
<section>
<description>Hostboot Bootloader (28K)</description>
<eyeCatch>HBBL</eyeCatch>
- <physicalOffset>0x311F000</physicalOffset>
+ <physicalOffset>0x308F000</physicalOffset>
<!-- Physical Size includes Header rounded to ECC valid size -->
<!-- Max size of actual HBBL content is 20K and 22.5K with ECC -->
<physicalRegionSize>0x7000</physicalRegionSize>
@@ -220,7 +202,7 @@ Layout Description
<section>
<description>Global Data (36K)</description>
<eyeCatch>GLOBAL</eyeCatch>
- <physicalOffset>0x3126000</physicalOffset>
+ <physicalOffset>0x3096000</physicalOffset>
<physicalRegionSize>0x9000</physicalRegionSize>
<side>sideless</side>
<ecc/>
@@ -228,7 +210,7 @@ Layout Description
<section>
<description>Ref Image Ring Overrides (20K)</description>
<eyeCatch>RINGOVD</eyeCatch>
- <physicalOffset>0x312F000</physicalOffset>
+ <physicalOffset>0x309F000</physicalOffset>
<physicalRegionSize>0x5000</physicalRegionSize>
<side>sideless</side>
<ecc/>
@@ -236,7 +218,7 @@ Layout Description
<section>
<description>SecureBoot Key Transition Partition (16K)</description>
<eyeCatch>SBKT</eyeCatch>
- <physicalOffset>0x3134000</physicalOffset>
+ <physicalOffset>0x30A4000</physicalOffset>
<physicalRegionSize>0x4000</physicalRegionSize>
<side>sideless</side>
<ecc/>
@@ -244,7 +226,7 @@ Layout Description
<section>
<description>OCC Lid (1.125M)</description>
<eyeCatch>OCC</eyeCatch>
- <physicalOffset>0x3138000</physicalOffset>
+ <physicalOffset>0x30A8000</physicalOffset>
<physicalRegionSize>0x120000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
@@ -255,7 +237,7 @@ Layout Description
<!-- We need 266KB per module sort, going to support
40 tables by default, plus ECC -->
<eyeCatch>WOFDATA</eyeCatch>
- <physicalOffset>0x3258000</physicalOffset>
+ <physicalOffset>0x31C8000</physicalOffset>
<physicalRegionSize>0x600000</physicalRegionSize>
<side>sideless</side>
<sha512Version/>
@@ -264,7 +246,7 @@ Layout Description
<section>
<description>FIRDATA (12K)</description>
<eyeCatch>FIRDATA</eyeCatch>
- <physicalOffset>0x3858000</physicalOffset>
+ <physicalOffset>0x37C8000</physicalOffset>
<physicalRegionSize>0x3000</physicalRegionSize>
<side>sideless</side>
<ecc/>
@@ -272,7 +254,7 @@ Layout Description
<section>
<description>Memory Data (128K)</description>
<eyeCatch>MEMD</eyeCatch>
- <physicalOffset>0x385B000</physicalOffset>
+ <physicalOffset>0x37CB000</physicalOffset>
<physicalRegionSize>0x20000</physicalRegionSize>
<side>sideless</side>
<sha512Version/>
@@ -281,7 +263,7 @@ Layout Description
<section>
<description>Secureboot Test Load (12K)</description>
<eyeCatch>TESTLOAD</eyeCatch>
- <physicalOffset>0x387B000</physicalOffset>
+ <physicalOffset>0x37EB000</physicalOffset>
<physicalRegionSize>0x3000</physicalRegionSize>
<side>sideless</side>
<sha512Version/>
@@ -290,7 +272,7 @@ Layout Description
<section>
<description>Centaur Hw Ref Image (12K)</description>
<eyeCatch>CENHWIMG</eyeCatch>
- <physicalOffset>0x387E000</physicalOffset>
+ <physicalOffset>0x37EE000</physicalOffset>
<physicalRegionSize>0x3000</physicalRegionSize>
<sha512Version/>
<side>sideless</side>
@@ -299,7 +281,7 @@ Layout Description
<section>
<description>Secure Boot (144K)</description>
<eyeCatch>SECBOOT</eyeCatch>
- <physicalOffset>0x3881000</physicalOffset>
+ <physicalOffset>0x37F1000</physicalOffset>
<physicalRegionSize>0x24000</physicalRegionSize>
<side>sideless</side>
<ecc/>
@@ -308,7 +290,7 @@ Layout Description
<section>
<description>Open CAPI Memory Buffer (OCMB) Firmware (300K)</description>
<eyeCatch>OCMBFW</eyeCatch>
- <physicalOffset>0x38A5000</physicalOffset>
+ <physicalOffset>0x3815000</physicalOffset>
<physicalRegionSize>0x4B000</physicalRegionSize>
<side>sideless</side>
<sha512Version/>
@@ -318,7 +300,7 @@ Layout Description
<section>
<description>HDAT Data (16K)</description>
<eyeCatch>HDAT</eyeCatch>
- <physicalOffset>0x38F0000</physicalOffset>
+ <physicalOffset>0x3860000</physicalOffset>
<physicalRegionSize>0x4000</physicalRegionSize>
<side>sideless</side>
<sha512Version/>
@@ -327,7 +309,7 @@ Layout Description
<section>
<description>Eeprom Cache(512K)</description>
<eyeCatch>EECACHE</eyeCatch>
- <physicalOffset>0x38F4000</physicalOffset>
+ <physicalOffset>0x3864000</physicalOffset>
<physicalRegionSize>0x80000</physicalRegionSize>
<side>sideless</side>
<ecc/>
diff --git a/src/build/mkrules/hbfw/img/makefile b/src/build/mkrules/hbfw/img/makefile
index 5212150..269a52c 100755
--- a/src/build/mkrules/hbfw/img/makefile
+++ b/src/build/mkrules/hbfw/img/makefile
@@ -214,16 +214,16 @@ BUILD_TYPE_PARAMS = --build-type fspbuild
.endif
# Decide which images to use for each PNOR layout
-GEN_COMMON_BIN_FILES = HBBL=${HBBL_IMG},HBB=${HBB_IMG},HBI=${HBI_IMG},HBRT=${HBRT_IMG},HBEL=EMPTY,GUARD=EMPTY,GLOBAL=EMPTY,CVPD=EMPTY,MVPD=EMPTY,DJVPD=EMPTY,RINGOVD=EMPTY,SBKT=EMPTY
+GEN_COMMON_BIN_FILES = HBBL=${HBBL_IMG},HBB=${HBB_IMG},HBI=${HBI_IMG},HBRT=${HBRT_IMG},HBEL=EMPTY,GUARD=EMPTY,GLOBAL=EMPTY,MVPD=EMPTY,RINGOVD=EMPTY,SBKT=EMPTY
GEN_STANDALONE_BIN_FILES = ${GEN_COMMON_BIN_FILES},TEST=EMPTY,TESTRO=EMPTY,TESTLOAD=EMPTY,PAYLOAD=EMPTY,FIRDATA=EMPTY
.if (${FAKEPNOR} == "")
# Parameters passed into GEN_PNOR_IMAGE_SCRIPT.
.if (${PNOR_LAYOUT_SELECTED} == "STANDALONE")
- GEN_DEFAULT_BIN_FILES = ${GEN_STANDALONE_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P}
+ GEN_DEFAULT_BIN_FILES = ${GEN_STANDALONE_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P},CVPD=EMPTY,DJVPD=EMPTY
.elif(${PNOR_LAYOUT_SELECTED} == "AXONE")
GEN_DEFAULT_BIN_FILES = ${GEN_STANDALONE_BIN_FILES},EECACHE=EMPTY,MEMD=${${ZZ_MEMD_IMG}:P},OCMBFW=${${OCMBFW_IMG}:P}
.else
- GEN_DEFAULT_BIN_FILES = ${GEN_COMMON_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P}
+ GEN_DEFAULT_BIN_FILES = ${GEN_COMMON_BIN_FILES},MEMD=${${ZZ_MEMD_IMG}:P},CVPD=EMPTY,DJVPD=EMPTY
.endif
DEFAULT_PARAMS = --build-all --emit-eccless ${TARGET_TEST:b--test} ${HB_STANDALONE:b--hb-standalone} \
${CONFIG_SECUREBOOT:b--secureboot} --systemBinFiles ${GEN_DEFAULT_BIN_FILES} \
@@ -493,13 +493,13 @@ gen_system_specific_images: build_sbe_partitions .PMAKE
.if (${PNOR_LAYOUT_SELECTED} == "FSP")
- HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},GLOBAL=${GLOBAL_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG}
+ HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},GLOBAL=${GLOBAL_FINAL_IMG},MVPD=${MVPD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG}
.else
- HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},TEST=${TEST_FINAL_IMG},TESTRO=${TESTRO_FINAL_IMG},TESTLOAD=${TESTLOAD_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},GLOBAL=${GLOBAL_FINAL_IMG},PAYLOAD=${PAYLOAD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG},FIRDATA=${FIRDATA_FINAL_IMG}
+ HOSTBOOT_DEFAULT_SECTIONS = HBBL=${HBBL_FINAL_IMG},HBB=${HBB_FINAL_IMG},HBI=${HBI_FINAL_IMG},HBRT=${HBRT_FINAL_IMG},TEST=${TEST_FINAL_IMG},TESTRO=${TESTRO_FINAL_IMG},TESTLOAD=${TESTLOAD_FINAL_IMG},HBEL=${HBEL_FINAL_IMG},GUARD=${GUARD_FINAL_IMG},GLOBAL=${GLOBAL_FINAL_IMG},PAYLOAD=${PAYLOAD_FINAL_IMG},MVPD=${MVPD_FINAL_IMG},RINGOVD=${RINGOVD_FINAL_IMG},SBKT=${SBKT_FINAL_IMG},FIRDATA=${FIRDATA_FINAL_IMG}
.endif
-NIMBUS_SECT = HBD=${NIMBUS_HBD_FINAL_IMG},SBE=${NIMBUS_SBE_FINAL_IMG},HCODE=${NIMBUS_HCODE_FINAL_IMG},OCC=${NIMBUS_OCC_FINAL_IMG},WOFDATA=${ZZ_WOFDATA_FINAL_IMG},CENHWIMG=${NIMBUS_CENHWIMG_FINAL_IMG},MEMD=${ZZ_MEMD_FINAL_IMG}
-CUMULUS_SECT = HBD=${CUMULUS_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${ZEPPELIN_MEMD_FINAL_IMG}
-CUMULUS_CDIMM_SECT = HBD=${CUMULUS_CDIMM_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${MEMD_FINAL_IMG}
+NIMBUS_SECT = HBD=${NIMBUS_HBD_FINAL_IMG},SBE=${NIMBUS_SBE_FINAL_IMG},HCODE=${NIMBUS_HCODE_FINAL_IMG},OCC=${NIMBUS_OCC_FINAL_IMG},WOFDATA=${ZZ_WOFDATA_FINAL_IMG},CENHWIMG=${NIMBUS_CENHWIMG_FINAL_IMG},MEMD=${ZZ_MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG}
+CUMULUS_SECT = HBD=${CUMULUS_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${ZEPPELIN_MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG}
+CUMULUS_CDIMM_SECT = HBD=${CUMULUS_CDIMM_HBD_FINAL_IMG},SBE=${CUMULUS_SBE_FINAL_IMG},HCODE=${CUMULUS_HCODE_FINAL_IMG},OCC=${CUMULUS_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${CUMULUS_CENHWIMG_FINAL_IMG},MEMD=${MEMD_FINAL_IMG},CVPD=${CVPD_FINAL_IMG},DJVPD=${DJVPD_FINAL_IMG}
AXONE_SECT = HBD=${AXONE_HBD_FINAL_IMG},SBE=${AXONE_SBE_FINAL_IMG},HCODE=${AXONE_HCODE_FINAL_IMG},OCC=${AXONE_OCC_FINAL_IMG},WOFDATA=${ZEPPELIN_WOFDATA_FINAL_IMG},CENHWIMG=${AXONE_CENHWIMG_FINAL_IMG},EECACHE=${EECACHE_FINAL_IMG},FIRDATA=${FIRDATA_FINAL_IMG},MEMD=${MEMD_FINAL_IMG},OCMBFW=${OCMBFW_FINAL_IMG}
diff --git a/src/build/simics/standalone.simics b/src/build/simics/standalone.simics
index 58821b2..39a3823 100755
--- a/src/build/simics/standalone.simics
+++ b/src/build/simics/standalone.simics
@@ -8,7 +8,7 @@
if not defined hb_skip_vpd_preload {$hb_skip_vpd_preload = 0}
-if ($hb_mode == 0) {
+if ($hb_mode == 0) { # Axone and beyond
# this number is no longer provided we have to look it up
$num_dimms = (dec (list-length((get-master-procs)[0].get-dimms)))
}
@@ -33,17 +33,24 @@ if ($hb_skip_vpd_preload == 0) {
run-python-file (lookup-file hbfw/hb-pnor-vpd-preload.py)
# Must match pnor layout used (see eyecatch in layout)
echo "PNOR layout offset for VPD:"
- # PNOR eyecatch MVPD
- echo " - MVPD at 0x79000"
- ($hb_pnor).load-file ./sysmvpd.dat.ecc 0x79000
- if ($hb_mode == 1){
- # PNOR eyecatch DJVPD
- echo " - DJVPD at 0x31000"
- ($hb_pnor).load-file ./sysspd.dat.ecc 0x31000
+
+ if ($hb_mode == 1) { # Nimbus/Cumulus
+ # PNOR eyecatch MVPD
+ echo " - MVPD at 0x79000"
+ ($hb_pnor).load-file ./sysmvpd.dat.ecc 0x79000
+
+ # PNOR eyecatch DJVPD
+ echo " - DJVPD at 0x31000"
+ ($hb_pnor).load-file ./sysspd.dat.ecc 0x31000
+
+ # PNOR eyecatch CVPD
+ echo " - CVPD at 0x109000"
+ ($hb_pnor).load-file ./sysmemvpd.dat.ecc 0x109000
+ } else { # Axone and beyond
+ # PNOR eyecatch MVPD
+ echo " - MVPD at 0x31000"
+ ($hb_pnor).load-file ./sysmvpd.dat.ecc 0x31000
}
- # PNOR eyecatch CVPD
- echo " - CVPD at 0x109000"
- ($hb_pnor).load-file ./sysmemvpd.dat.ecc 0x109000
} except { echo "ERROR: Failed to preload VPD into PNOR." }
}
diff --git a/src/usr/pnor/test/pnorrptest.H b/src/usr/pnor/test/pnorrptest.H
index 5108840..9d9dd95 100644
--- a/src/usr/pnor/test/pnorrptest.H
+++ b/src/usr/pnor/test/pnorrptest.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2011,2018 */
+/* Contributors Listed Below - COPYRIGHT 2011,2019 */
/* [+] Google Inc. */
/* [+] International Business Machines Corp. */
/* */
@@ -90,6 +90,14 @@ class PnorRpTest : public CxxTest::TestSuite
continue;
}
+ if(( testSections[idx] == PNOR::DIMM_JEDEC_VPD ) &&
+ ( TARGETING::MODEL_AXONE ==
+ TARGETING::targetService().getProcessorModel() ))
+ {
+ TRACFCOMP(g_trac_pnor, "PnorRpTest::test_sectionInfo> Skipping non-existent DIMM_JEDEC_VPD section for Axone");
+ continue;
+ }
+
total++;
errhdl = PNOR::getSectionInfo( testSections[idx], info );
diff --git a/src/usr/vpd/makefile b/src/usr/vpd/makefile
index ad231ee..728750f 100644
--- a/src/usr/vpd/makefile
+++ b/src/usr/vpd/makefile
@@ -46,8 +46,8 @@ BINARY_FILES += $(IMGDIR)/vpo_djvpd.dat:eb4dce98f19ebfe77243be1c56d3d0eaa1889d90
# P9 (and P9 Prime) Module VPD
BINARY_FILES += $(IMGDIR)/procmvpd_p9n.dat:a351f3cd5ba8a81a50c3e5a0dea5fea03e55769d
-BINARY_FILES += $(IMGDIR)/procmvpd_p9c.dat:939f91a9359b917c525dd7cd4ea80a03b1c08714
-BINARY_FILES += $(IMGDIR)/procmvpd_p9a.dat:939f91a9359b917c525dd7cd4ea80a03b1c08714
+BINARY_FILES += $(IMGDIR)/procmvpd_p9c.dat:04dccd5f633f07fc36dd35515d49277c0cd26a91
+BINARY_FILES += $(IMGDIR)/procmvpd_p9a.dat:04dccd5f633f07fc36dd35515d49277c0cd26a91
# CDIMM Format - download 4k cvpd file
BINARY_FILES += $(IMGDIR)/cvpd_cdimm.dat:b12431fbc14304edd31e74405cdcb27560a8e00b
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