diff options
author | Thi Tran <thi@us.ibm.com> | 2014-03-31 12:36:29 -0500 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-04-03 07:59:56 -0500 |
commit | 21441f5be604ac27ffe33f97aa076566a1bffffc (patch) | |
tree | 5be6f841e091bd391d96250f2e1db4cdeef82497 | |
parent | 93ea00ea95501ae482474390b5ac10ccacfcdeea (diff) | |
download | talos-hostboot-21441f5be604ac27ffe33f97aa076566a1bffffc.tar.gz talos-hostboot-21441f5be604ac27ffe33f97aa076566a1bffffc.zip |
INITPROC: Hostboot SW253861 DRAM init training & initfile updates
Change-Id: I18808c52f5ec4245f29b2f234437d42cf354d997
CQ:SW253861
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10010
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
-rw-r--r-- | src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C | 61 | ||||
-rwxr-xr-x | src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile | 30 |
2 files changed, 75 insertions, 16 deletions
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C index 71a15ed90..bddb1c01f 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training.C,v 1.73 2014/02/25 22:23:13 mwuu Exp $ +// $Id: mss_draminit_training.C,v 1.77 2014/03/28 19:48:10 jdsloat Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -28,6 +28,10 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|------------------------------------------------ +// 1.77 | jdsloat |28-MAR-14| Added ifdef around #include for mss_lrdimm_ddr4_funcs.H +// 1.76 | mwuu |14-MAR-14| Fixed CDIMM full spare case in getC4dq2reg (bbm) +// 1.75 | kcook |14-MAR-14| Fixed mss_mxd_training stub function definition +// 1.74 | kcook |14-MAR-14| Added calls to DDR4 LRDIMM training functions // 1.73 | mwuu |25-FEB-14| Fixed ISDIMM spare case for bad bitmap // 1.72 | mwuu |14-FEB-14| Fixed x4 spare case when mss_c4_phy returns bad // | | | data with workaround @@ -154,6 +158,9 @@ #include <mss_lrdimm_funcs.H> #include "mss_access_delay_reg.H" +#ifdef FAPI_LRDIMM +#include <mss_lrdimm_ddr4_funcs.H> +#endif #ifndef FAPI_LRDIMM using namespace fapi; @@ -166,6 +173,33 @@ fapi::ReturnCode mss_execute_lrdimm_mb_dram_training(Target& i_target) return rc; } +fapi::ReturnCode mss_mrep_training(Target& i_target, uint32_t port) +{ + ReturnCode rc; + + FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + +} +fapi::ReturnCode mss_mxd_training(Target& i_target, uint8_t port, uint8_t i_type) +{ + ReturnCode rc; + + FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + +} +fapi::ReturnCode mss_dram_write_leveling(Target& i_target, uint32_t port) +{ + ReturnCode rc; + + FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + +} #endif @@ -430,9 +464,18 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) { rc = mss_execute_zq_cal(i_target, port); if(rc) return rc; + + // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs + if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) && + (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) + { + rc = mss_mrep_training(i_target, port); + rc = mss_mxd_training(i_target,port,0); + } } - if ( dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) + if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) && + (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) { FAPI_INF("Performing LRDIMM MB-DRAM training"); @@ -659,7 +702,14 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) if(rc) return rc; } } - + // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs + else if ( (group == 0) && (cur_cal_step == 1) + && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) + && (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) + { + rc = mss_dram_write_leveling(i_target, port); + if(rc) return rc; + } //Set the config register if(port == 0) @@ -3420,6 +3470,7 @@ fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target) return rc; } } + // does disabling read clocks for unused bytes cause problems? else { uint64_t rdclk_addr = @@ -3772,7 +3823,7 @@ ReturnCode getC4dq2reg(const Target & i_mba, const uint8_t i_port, switch (dimm_spare[i_port][i_dimm][i_rank]) { - case ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE: + case ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE: // 0xFF continue; // ignore bbm data for nonexistent spare break; case ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE: @@ -3782,7 +3833,7 @@ ReturnCode getC4dq2reg(const Target & i_mba, const uint8_t i_port, spare_bitmap = 0xF0; break; case ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE: - spare_bitmap = 0xFF; + spare_bitmap = 0x00; break; default: FAPI_ERR("ATTR_VPD_DIMM_SPARE is invalid %u", diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile index 86fdfbb2c..f619acbfc 100755 --- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile @@ -1,4 +1,4 @@ -#-- $Id: cen_ddrphy.initfile,v 1.30 2014/01/23 01:33:13 mwuu Exp $ +#-- $Id: cen_ddrphy.initfile,v 1.31 2014/03/11 16:13:37 mwuu Exp $ #-- $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ #-- centaur/working/procedures/ec_ind/scoms/cen_ddrphy.initfile,v $ # @@ -6,6 +6,9 @@ #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +# 1.31|mwuu |03/11/14|Changed DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0 +# | | |VCO bits 60:63 to match the DP18 PLL of 700MHz, +# | | |Changed LRDIMM settings GPO, WLO to use attributes # 1.30|mwuu |01/22/14|Changed DIMM_TYPE fix for DDR4 CDIMM # 1.29|mwuu |01/14/14|Added VPD attributes for TSYS_ADR, TSYS_DP18, # | | |changed DIMM_TYPE for obsolete CDIMM enum @@ -432,7 +435,7 @@ scom 0x8000C00D0301143F { # 0:47 , 0x000000000000, any ; # reserved # # WLO is normally 0 except for RDIMM (RCD) configurations in which case it's set to 1 # DD0 = PORT_BUFFER_LATENCY - 48:51 , 0xF , (def_is_lrdimm) ; # LRDIMM set WLO=-1 +# 48:51 , 0xF , (def_is_lrdimm) ; # LRDIMM set WLO=-1 48:51 , (ATTR_VPD_WLO[0]), any ; # based on attribute now.. # 48:51 , 0x1 , (def_is_rdimm) ; # RDIMM # 48:51 , 0x0 , any ; # WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7) @@ -440,6 +443,7 @@ scom 0x8000C00D0301143F { # 52:55 , 0x1 , (def_is_rdimm) ; # RDIMM # 52:55 , 0x0 , any ; # CDIMM/UDIMM # 52:55 , 0x6 , (def_is_lrdimm) ; # LRDIMM # !! need to review LR settings !! +# 52:55 , (ATTR_VPD_RLO[0] + 1), (def_2N_mode) ; # based on attribute now.. 52:55 , (ATTR_VPD_RLO[0]), any ; # based on attribute now.. 56 , 0b0 , any ; # MEMCTL_CIC_FAST 57 , 0b0 , any ; # MEMCTL_CTRN_IGNORE @@ -470,12 +474,13 @@ scom 0x8001C00D0301143F { # 0:47 , 0x000000000000, any ; # reserved # # WLO is normally 0 except for RDIMM (RCD) configurations in which case it's set to 1 # DD0 = PORT_BUFFER_LATENCY - 48:51 , 0xF , (def_is_lrdimm) ; # LRDIMM set WLO=-1 +# 48:51 , 0xF , (def_is_lrdimm) ; # LRDIMM set WLO=-1 48:51 , (ATTR_VPD_WLO[1]), any ; # based on attribute now.. # 48:51 , 0x1 , (def_is_rdimm) ; # RDIMM # 48:51 , 0x0 , any ; # WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7) # # 9.4.12.2 RLO = READ_LATENCY_OFFSET (2's complement -8 to 7) {0=CDIMM, 1=RDIMM, 2=LRDIMM} - 52:55 , 0x6 , (def_is_lrdimm) ; # LRDIMM +# 52:55 , 0x6 , (def_is_lrdimm) ; # LRDIMM +# 52:55 , (ATTR_VPD_RLO[1] + 1), (def_2N_mode) ; # based on attribute now.. 52:55 , (ATTR_VPD_RLO[1]), any ; # based on attribute now.. # 52:55 , 0x1 , (def_is_rdimm) ; # RDIMM # 52:55 , 0x0 , any ; # CDIMM/UDIMM @@ -548,9 +553,11 @@ scom 0x800(0,1)BC300301143F { # PHY01 Port[0:1] broadcast ADR32S[0:1] # # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) 48:59 , 0x6A9 , (CEN.ATTR_MSS_FREQ > 1459) ; # >= 730 MHz, >=1460 MT/s - 60:63 , 0x4 , (def_is_ddr4) ; # VCO = high for DDR4 - 60:63 , 0x0 , any ; # VCO = low for DDR3 - +# 60:63 , 0x4 , (def_is_ddr4) ; # VCO = high for DDR4 +# 60:63 , 0x0 , any ; # VCO = low for DDR3 +# changed from SWyatt review... + 60:63 , 0x4 , (CEN.ATTR_MSS_FREQ > 1400) ; # VCO = high for >= 700MHz or 1400 MT/s + 60:63 , 0x0 , any ; # VCO = low for < 700MHz } # --------------------------------------------------------------------------------------- @@ -639,9 +646,10 @@ scom 0x800(0,1)3C760301143F { # CONFIG0_P[0:1] broadcast [0:4] # # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) 48:59 , 0x6A9 , (CEN.ATTR_MSS_FREQ > 1459) ; # >= 730 MHz, >=1460 MT/s +# Changed to 700MHz per Swyatt # 60:63 , 0x0 , (def_is_sim) ; # for SIM - 60:63 , 0x4 , (CEN.ATTR_MSS_FREQ > 1459) ; # VCO = high for >= 730MHz or 1460 MT/s - 60:63 , 0x0 , any ; # VCO = low for < 730MHz + 60:63 , 0x4 , (CEN.ATTR_MSS_FREQ > 1400) ; # VCO = high for >= 700MHz or 1400 MT/s + 60:63 , 0x0 , any ; # VCO = low for < 700MHz } # --------------------------------------------------------------------------------------- @@ -3795,7 +3803,7 @@ scom 0x8001C8000301143F { # _P1 # # min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN # max GPO = 11 if in 2:1, 13 if in 4:1 - 48:51 , 0b0111 , (def_is_lrdimm) ; # GLOBAL_PHY_OFFSET LRDIMM set to 7 +# 48:51 , 0b0111 , (def_is_lrdimm) ; # GLOBAL_PHY_OFFSET LRDIMM set to 7 48:51 , (ATTR_VPD_GPO[1]), any ; # GLOBAL_PHY_OFFSET (GPO), based on attribute now # 48:51 , 0b0101 , any ; # GLOBAL_PHY_OFFSET (GPO), ideally 2:1 max=11, 4:1 max=13 52 , 0b0 , any ; # ADVANCE_RD_VALID ask Yuen @@ -4167,7 +4175,7 @@ scom 0x800(0,1)CC020301143F { # _P[0:1] } # --------------------------------------------------------------------------------------- -# Write control logic configuration 3 default=0x01F8 +# Write control logic configuration 3 default=0x01F8 DDR4 PDA register # # DPHY01_DDRPHY_WC_CONFIG3_P0 0x005 0x8000cc050301143f # PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG3_L2 |