L3 Update - p9_perst_phb HWP

Change-Id: If0d53a0b3c2083836ce72fcf81d6229949a48fff
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43163
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44216
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 183 insertions, 193 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_perst_phb.C b/src/import/chips/p9/procedures/hwp/nest/p9_perst_phb.C
index 97f599391..a4e091501 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_perst_phb.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_perst_phb.C
@@ -29,191 +29,189 @@
 // *HWP HWP Owner: Ricardo Mata Jr. ricmata@us.ibm.com
 // *HWP FW Owner: Thi Tran thi@us.ibm.com
 // *HWP Team: Nest
-// *HWP Level: 2
-// *HWP Consumed by: HB
+// *HWP Level: 3
+// *HWP Consumed by: FSP
 
 //-----------------------------------------------------------------------------------
 // Includes
 //-----------------------------------------------------------------------------------
 #include <p9_perst_phb.H>
 #include <p9_phb_hv_access.H>
-#include "p9_misc_scom_addresses.H"
-#include "p9_misc_scom_addresses_fld.H"
+#include <p9_misc_scom_addresses.H>
+#include <p9_misc_scom_addresses_fld.H>
 
-extern "C"
+//-----------------------------------------------------------------------------------
+// Constant definitions
+//-----------------------------------------------------------------------------------
+// PCI Nest FIR Register bit26 for SW Freeze enablement
+const uint8_t PHB_NFIR_REG_SW_DEFINED_FREEZE = 26;
+//Maximum number of iterations (So, 20ms * 100 = 2s before timeout)
+const uint32_t MAX_NUM_POLLS = 100;
+//(40000000 ns = 20 ms) to wait for PBCQ inbound/outbound to become inactive
+const uint64_t NANO_SEC_DELAY = 256;
+//400,000 simulation cycles to wait for PBCQ inbound/outbound to become inactive
+const uint64_t SIM_CYC_DELAY = 512;
+
+/// See doxygen in header file
+fapi2::ReturnCode p9_perst_phb(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target,
+                               const PERST_ACTION i_perst_action)
 {
-    //---------------------------//
-    // Function definitions      //
-    //---------------------------//
-    //------------------------------------------------------------------------------
-    // name: p9_perst_phb
-    //------------------------------------------------------------------------------
-    // purpose:
-    // Procedure to asser/deassert PERST signal from PHB.
-    //
-    // parameters:
-    // 'i_target' is reference to phb target
-    // 'i_perst_action' is reference to the ACTIVATE or DEACTIVATE PERST.
-    //
-    // returns:
-    // FAPI_RC_SUCCESS (success, forced PERST assert/deassert from PHBs)
-    // (Note: refer to file eclipz/chips/p9/working/procedures/xml/error_info/p9_perst_phb_errors.xml)
-    // getscom/putscom fapi errors
-    // fapi error assigned from eCMD function failure
-    //
-    //------------------------------------------------------------------------------
-    fapi2::ReturnCode p9_perst_phb(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target, const PERST_ACTION i_perst_action)
+    fapi2::buffer<uint64_t> l_buf = 0;
+    fapi2::buffer<uint64_t> l_buf2 = 0;
+    fapi2::buffer<uint64_t> l_buf3 = 0;
+    uint8_t l_phb_id = 0;
+    uint32_t l_poll_counter; // # of iterations while polling for inbound_active and outbound_active
+
+    //Get the PHB id
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, l_phb_id),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)");
+    FAPI_DBG("PHB%i: Start PERST PHB Procedure", l_phb_id);
+
+    //Make sure that the perst action input is valid
+    FAPI_ASSERT(i_perst_action == ACTIVATE_PERST ||
+                i_perst_action == DEACTIVATE_PERST,
+                fapi2::P9_PHB_PERST_ACTION_INVALID_ARGS_ERR()
+                .set_TARGET(i_target)
+                .set_PERSTACTION(i_perst_action),
+                "PHB%i: invalid requested PERST action (%u)",
+                l_phb_id, i_perst_action);
+
+    //Read state of ETU Reset Register
+    FAPI_TRY(fapi2::getScom(i_target, PHB_PHBRESET_REG, l_buf),
+             "Error from getScom (0x%.16llX), PHB_PHBRESET_REG");
+    FAPI_DBG("  ETU Reset Register %016lX", l_buf());
+
+    if(l_buf.getBit(PHB_PHBRESET_REG_PE_ETU_RESET))
     {
-        fapi2::buffer<uint64_t> l_buf = 0;
-        fapi2::buffer<uint64_t> l_buf2 = 0;
-        fapi2::buffer<uint64_t> l_buf3 = 0;
-        uint8_t l_phb_id = 0;
-        uint32_t l_poll_counter; // # of iterations while polling for inbound_active and outbound_active
-
-
-        //Get the PHB id
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, l_phb_id));
-
-        FAPI_DBG("PHB%i: Start PERST PHB Procedure", l_phb_id);
-
-        //Make sure that the perst action input is valid
-        FAPI_ASSERT(!((i_perst_action != ACTIVATE_PERST) && (i_perst_action != DEACTIVATE_PERST)),
-                    fapi2::P9_PHB_PERST_ACTION_INVALID_ARGS_ERR()
-                    .set_TARGET(i_target)
-                    .set_PERSTACTION(i_perst_action),
-                    "PHB%i: i_perst_action is not valid", l_phb_id);
-
-
-        //Read state of ETU Reset Register
-        FAPI_TRY(fapi2::getScom(i_target, PHB_PHBRESET_REG, l_buf));
+        //Take ETU out of reset to acess PHB PCI - Core Reset Register
+        FAPI_DBG("  ETU is in reset. Taking it out of reset");
+        l_buf.clearBit<PHB_PHBRESET_REG_PE_ETU_RESET>();
         FAPI_DBG("  ETU Reset Register %016lX", l_buf());
+        FAPI_TRY(fapi2::putScom(i_target, PHB_PHBRESET_REG, l_buf),
+                 "Error from putScom (0x%.16llX), PHB_PHBRESET_REG");
+        FAPI_TRY(fapi2::delay(NANO_SEC_DELAY, SIM_CYC_DELAY),
+                 "fapiDelay error.");
+    }
 
-        if(l_buf.getBit(PHB_PHBRESET_REG_PE_ETU_RESET))
-        {
-            //Take ETU out of reset to acess PHB PCI - Core Reset Register
-            FAPI_DBG("  ETU is in reset. Taking it out of reset");
-            l_buf.clearBit<PHB_PHBRESET_REG_PE_ETU_RESET>();
-            FAPI_DBG("  ETU Reset Register %016lX", l_buf());
-            FAPI_TRY(fapi2::putScom(i_target, PHB_PHBRESET_REG, l_buf));
+    //Perform PERST action requested
+    if(i_perst_action == DEACTIVATE_PERST) //Deactive PERST
+    {
+        //Deassert the PERST signal from the PHB
+        FAPI_DBG("  Deassert PERST signal.");
 
-            FAPI_TRY(fapi2::delay(NANO_SEC_DELAY, SIM_CYC_DELAY), "fapiDelay error.");
-        }
+        //RMW PHB Core Reset Register
+        FAPI_TRY(p9_phb_hv_access(i_target, PHB_CORE_RESET_REGISTER, true, false, l_buf),
+                 "Error from p9_phb_hv_access: Deactivate PHB_CORE_RESET_REGISTER (Read)");
 
+        l_buf.setBit<PHB_HP_PERST_BIT>();
+        FAPI_DBG("  Value to be written to %016lX -  %016lX", PHB_CORE_RESET_REGISTER, l_buf());
+        FAPI_TRY(p9_phb_hv_access(i_target, PHB_CORE_RESET_REGISTER, false, false, l_buf),
+                 "Error from p9_phb_hv_access: Deactivate PHB_CORE_RESET_REGISTER (Write)");
+    }
+    else //Activate PERST
+    {
 
-        //Perform PERST action requested
-        if(i_perst_action == DEACTIVATE_PERST) //Deactive PERST
-        {
+        //Assert the PERST signal from the PHB
+        FAPI_DBG("  Assert PERST signal.");
+
+        //RMW PHB Core Reset Register
+        FAPI_TRY(p9_phb_hv_access(i_target, PHB_CORE_RESET_REGISTER, true, false, l_buf),
+                 "Error from p9_phb_hv_access: Activate PHB_CORE_RESET_REGISTER (Read)");
+
+        l_buf.clearBit<PHB_HP_PERST_BIT>();
+        FAPI_DBG("  Value to be written to %016lX - %016lX", PHB_CORE_RESET_REGISTER, l_buf());
+        FAPI_TRY(p9_phb_hv_access(i_target, PHB_CORE_RESET_REGISTER, false, false, l_buf),
+                 "Error from p9_phb_hv_access: Activate PHB_CORE_RESET_REGISTER (Write)");
+
+        //Force PEC freeze by setting SW Freeze bit in PCI Nest FIR Register
+        l_buf = 0;
+        l_buf.setBit<PHB_NFIR_REG_SW_DEFINED_FREEZE>();
+        FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf());
+        FAPI_TRY(fapi2::putScom(i_target, PHB_NFIR_REG_OR, l_buf),
+                 "Error from putScom (0x%.16llX)", PHB_NFIR_REG_OR);
+
+        //Put ETU into reset
+        FAPI_DBG("  Put ETU into reset.");
+        l_buf = 0;
+        l_buf.setBit<PHB_PHBRESET_REG_PE_ETU_RESET>();
+        FAPI_DBG("  ETU Reset Register %016lX", l_buf());
+        FAPI_TRY(fapi2::putScom(i_target, PHB_PHBRESET_REG, l_buf),
+                 "Error from putScom (0x%.16llX)", PHB_PHBRESET_REG);
 
-            //Deassert the PERST signal from the PHB
-            FAPI_DBG("  Deassert PERST signal.");
+        //Check CQ Status
+        l_poll_counter = 0; //Reset poll counter
 
-            //RMW PHB Core Reset Register
-            FAPI_TRY(p9_phb_hv_access(i_target, PHB_CORE_RESET_REGISTER, true, false, l_buf));
-            l_buf.setBit<PHB_HP_PERST_BIT>();
-            FAPI_DBG("  Value to be written to %016lX -  %016lX", PHB_CORE_RESET_REGISTER, l_buf());
-            FAPI_TRY(p9_phb_hv_access(i_target, PHB_CORE_RESET_REGISTER, false, false, l_buf));
-        }
-        else //Activate PERST
+        while (l_poll_counter < MAX_NUM_POLLS)
         {
-
-            //Assert the PERST signal from the PHB
-            FAPI_DBG("  Assert PERST signal.");
-
-            //RMW PHB Core Reset Register
-            FAPI_TRY(p9_phb_hv_access(i_target, PHB_CORE_RESET_REGISTER, true, false, l_buf));
-            l_buf.clearBit<PHB_HP_PERST_BIT>();
-            FAPI_DBG("  Value to be written to %016lX - %016lX", PHB_CORE_RESET_REGISTER, l_buf());
-            FAPI_TRY(p9_phb_hv_access(i_target, PHB_CORE_RESET_REGISTER, false, false, l_buf));
-
-            //Force PEC freeze by setting SW Freeze bit in PCI Nest FIR Register
-            l_buf = 0;
-            l_buf.setBit<PHB_NFIR_REG_SW_DEFINED_FREEZE>();
-            FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf());
-            FAPI_TRY(fapi2::putScom(i_target, PHB_NFIR_REG_OR, l_buf), "Error from putScom (0x%.16llX)", PHB_NFIR_REG_OR);
-
-            //Put ETU into reset
-            FAPI_DBG("  Put ETU into reset.");
-            l_buf = 0;
-            l_buf.setBit<PHB_PHBRESET_REG_PE_ETU_RESET>();
-            FAPI_DBG("  ETU Reset Register %016lX", l_buf());
-            FAPI_TRY(fapi2::putScom(i_target, PHB_PHBRESET_REG, l_buf));
-
-            //Check CQ Status
-            l_poll_counter = 0; //Reset poll counter
-
-            while (l_poll_counter < MAX_NUM_POLLS)
+            l_poll_counter++;
+            FAPI_TRY(fapi2::delay(NANO_SEC_DELAY, SIM_CYC_DELAY),
+                     "fapiDelay error.");
+
+            //Read PBCQ General Status Register and put contents into l_buf
+            FAPI_TRY(fapi2::getScom(i_target, PHB_CQSTAT_REG, l_buf),
+                     "Error from getScom (0x%.16llX)", PHB_CQSTAT_REG);
+            FAPI_DBG("PHB%i: PBCQ General Status Register %#lx", l_phb_id, l_buf());
+
+            //Check for bits 0 (inbound_active) and 1 (outbound_active) to become deasserted
+            if (!(l_buf.getBit(PEC_STACK0_CQSTAT_REG_PE_INBOUND_ACTIVE) ||
+                  l_buf.getBit(PEC_STACK0_CQSTAT_REG_PE_OUTBOUND_ACTIVE)))
             {
-                l_poll_counter++;
-                FAPI_TRY(fapi2::delay(NANO_SEC_DELAY, SIM_CYC_DELAY), "fapiDelay error.");
-
-                //Read PBCQ General Status Register and put contents into l_buf
-                FAPI_TRY(fapi2::getScom(i_target, PHB_CQSTAT_REG, l_buf), "Error from getScom (0x%.16llX)", PHB_CQSTAT_REG);
-                FAPI_DBG("PHB%i: PBCQ General Status Register %#lx", l_phb_id, l_buf());
 
-                //Check for bits 0 (inbound_active) and 1 (outbound_active) to become deasserted
-                if (!(l_buf.getBit(PEC_STACK0_CQSTAT_REG_PE_INBOUND_ACTIVE) || l_buf.getBit(PEC_STACK0_CQSTAT_REG_PE_OUTBOUND_ACTIVE)))
-                {
-
-                    FAPI_DBG("PHB%i: PBCQ CQ status is idle.", l_phb_id);
-                    FAPI_DBG("PHB%i: End polling for inbound_active and outbound_active state machines to become idle.", l_phb_id);
-                    break;
-                }
+                FAPI_DBG("PHB%i: PBCQ CQ status is idle.", l_phb_id);
+                break;
             }
+        }
 
-            FAPI_DBG("PHB%i: inbound_active and outbound_active status (poll counter = %d).", l_phb_id, l_poll_counter);
-
-            FAPI_TRY(fapi2::getScom(i_target, PHB_NFIR_REG, l_buf2), "Error from getScom (0x%.16llX)", PHB_NFIR_REG);
-
-            FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf2());
-
-            FAPI_TRY(fapi2::getScom(i_target, PHB_PHBRESET_REG, l_buf3), "Error from getScom (0x%.16llX)", PHB_PHBRESET_REG);
-
-            FAPI_DBG("PHB%i: PHB Reset Register %#lx", l_phb_id, l_buf3());
-
-            FAPI_ASSERT(l_poll_counter < MAX_NUM_POLLS,
-                        fapi2::P9_PHB_PERST_PBCQ_CQ_NOT_IDLE()
-                        .set_TARGET(i_target)
-                        .set_NFIR_ADDR(PHB_NFIR_REG)
-                        .set_NFIR_DATA(l_buf2)
-                        .set_PHB_RESET_ADDR(PHB_PHBRESET_REG)
-                        .set_PHB_RESET_DATA(l_buf3)
-                        .set_CQ_STAT_ADDR(PHB_CQSTAT_REG)
-                        .set_CQ_STAT_DATA(l_buf),
-                        "PHB%i: PBCQ CQ Status did not clear.", l_phb_id);
-
-            //Clear FIR bits of PCI Nest FIR register
-            FAPI_TRY(fapi2::getScom(i_target, PHB_NFIR_REG, l_buf), "Error from getScom (0x%.16llX)", PHB_NFIR_REG);
-            FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf());
-            l_buf.invert();
-            FAPI_DBG("PHB%i: PCI Nest FIR Register Clear %#lx", l_phb_id, l_buf());
-
-            FAPI_TRY(fapi2::putScom(i_target, PHB_NFIR_REG_AND, l_buf), "Error from putScom (0x%.16llX)", PHB_NFIR_REG_AND);
-
-            //Confirm FIR bits have been cleared
-            FAPI_TRY(fapi2::getScom(i_target, PHB_NFIR_REG, l_buf), "Error from getScom (0x%.16llX)", PHB_NFIR_REG);
-            FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf());
+        FAPI_DBG("PHB%i: inbound_active and outbound_active status (poll counter = %d).",
+                 l_phb_id, l_poll_counter);
 
-            FAPI_TRY(fapi2::getScom(i_target, PHB_PFIR_REG, l_buf2), "Error from getScom (0x%.16llX)", PHB_PFIR_REG);
-            FAPI_DBG("PHB%i: PCI FIR Register %#lx", l_phb_id, l_buf2());
+        FAPI_TRY(fapi2::getScom(i_target, PHB_NFIR_REG, l_buf2),
+                 "Error from getScom (0x%.16llX)", PHB_NFIR_REG);
+        FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf2());
 
-            if (l_buf.getBit<PHB_NFIR_REG_NFIRNFIR, PHB_NFIR_REG_NFIRNFIR_LEN>())
-            {
-                FAPI_ASSERT(false,
-                            fapi2::P9_PHB_PERST_NFIR_NOT_CLEARED()
-                            .set_TARGET(i_target)
-                            .set_NFIR_ADDR(PHB_NFIR_REG)
-                            .set_NFIR_DATA(l_buf)
-                            .set_PFIR_ADDR(PHB_PFIR_REG)
-                            .set_PFIR_DATA(l_buf2),
-                            "PHB%i: PCI Nest FIR Register did not clear.", l_phb_id);
-            }
+        FAPI_TRY(fapi2::getScom(i_target, PHB_PHBRESET_REG, l_buf3),
+                 "Error from getScom (0x%.16llX)", PHB_PHBRESET_REG);
+        FAPI_DBG("PHB%i: PHB Reset Register %#lx", l_phb_id, l_buf3());
 
-            FAPI_DBG("PHB%i: Succesfully cleared PCI Nest FIR.", l_phb_id);
-        }
+        FAPI_ASSERT(l_poll_counter < MAX_NUM_POLLS,
+                    fapi2::P9_PHB_PERST_PBCQ_CQ_NOT_IDLE()
+                    .set_TARGET(i_target)
+                    .set_NFIR_ADDR(PHB_NFIR_REG)
+                    .set_NFIR_DATA(l_buf2)
+                    .set_PHB_RESET_ADDR(PHB_PHBRESET_REG)
+                    .set_PHB_RESET_DATA(l_buf3)
+                    .set_CQ_STAT_ADDR(PHB_CQSTAT_REG)
+                    .set_CQ_STAT_DATA(l_buf),
+                    "PHB%i: PBCQ CQ Status did not clear.", l_phb_id);
+
+        //Clear FIR bits of PCI Nest FIR register
+        l_buf.flush<0>();
+        FAPI_DBG("PHB%i: PCI Nest FIR Register Clear %#lx", l_phb_id, l_buf());
+        FAPI_TRY(fapi2::putScom(i_target, PHB_NFIR_REG_AND, l_buf),
+                 "Error from putScom (0x%.16llX)", PHB_NFIR_REG_AND);
+
+        //Confirm FIR bits have been cleared
+        FAPI_TRY(fapi2::getScom(i_target, PHB_NFIR_REG, l_buf),
+                 "Error from getScom (0x%.16llX)", PHB_NFIR_REG);
+        FAPI_DBG("PHB%i: PCI Nest FIR Register %#lx", l_phb_id, l_buf());
+
+        FAPI_TRY(fapi2::getScom(i_target, PHB_PFIR_REG, l_buf2),
+                 "Error from getScom (0x%.16llX)", PHB_PFIR_REG);
+        FAPI_DBG("PHB%i: PCI FIR Register %#lx", l_phb_id, l_buf2());
+
+        FAPI_ASSERT(!(l_buf.getBit<PHB_NFIR_REG_NFIRNFIR, PHB_NFIR_REG_NFIRNFIR_LEN>()),
+                    fapi2::P9_PHB_PERST_NFIR_NOT_CLEARED()
+                    .set_TARGET(i_target)
+                    .set_NFIR_ADDR(PHB_NFIR_REG)
+                    .set_NFIR_DATA(l_buf)
+                    .set_PFIR_ADDR(PHB_PFIR_REG)
+                    .set_PFIR_DATA(l_buf2),
+                    "PHB%i: PCI Nest FIR Register did not clear.", l_phb_id);
 
-    fapi_try_exit:
-        FAPI_DBG("PHB%i: End PERST PHB Procedure", l_phb_id);
-        return fapi2::current_err;
+        FAPI_DBG("PHB%i: Succesfully cleared PCI Nest FIR.", l_phb_id);
     }
 
-} // extern "C
+fapi_try_exit:
+    FAPI_DBG("PHB%i: End PERST PHB Procedure", l_phb_id);
+    return fapi2::current_err;
+}
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_perst_phb.H b/src/import/chips/p9/procedures/hwp/nest/p9_perst_phb.H
index 3b63a57f0..94d168ba0 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_perst_phb.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_perst_phb.H
@@ -29,8 +29,8 @@
 // *HWP HWP Owner: Ricardo Mata Jr. ricmata@us.ibm.com
 // *HWP FW Owner: Thi Tran thi@us.ibm.com
 // *HWP Team: Nest
-// *HWP Level: 2
-// *HWP Consumed by: HB
+// *HWP Level: 3
+// *HWP Consumed by: FSP
 
 #ifndef _P9_PERST_PHB_H_
 #define _P9_PERST_PHB_H_
@@ -44,7 +44,7 @@
 enum PERST_ACTION
 {
     ACTIVATE_PERST,     //Drive PERST signal active from the PHB. Put in to Reset.
-    DEACTIVATE_PERST        //Drive PERST signal inactive from the PHB. Take out of Reset.
+    DEACTIVATE_PERST    //Drive PERST signal inactive from the PHB. Take out of Reset.
 };
 #endif
 
@@ -61,30 +61,21 @@ enum PERST_ACTION
 //function pointer typedef definition for HWP call support
 typedef fapi2::ReturnCode (*p9_perst_phb_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PHB>&, const PERST_ACTION);
 
-//-----------------------------------------------------------------------------------
-// Constant definitions
-//-----------------------------------------------------------------------------------
-
-// PCI Nest FIR Register bit26 for SW Freeze enablement
-const uint8_t PHB_NFIR_REG_SW_DEFINED_FREEZE = 26;
-//Maximum number of iterations (So, 20ms * 100 = 2s before timeout)
-const uint32_t MAX_NUM_POLLS = 100;
-//(40000000 ns = 20 ms) to wait for PBCQ inbound/outbound to become inactive
-const uint64_t NANO_SEC_DELAY = 256;
-//400,000 simulation cycles to wait for PBCQ inbound/outbound to become inactive
-const uint64_t SIM_CYC_DELAY = 512;
-
-
 extern "C" {
 
 //-----------------------------------------------------------------------------------
 // Function prototype
 //-----------------------------------------------------------------------------------
-/// @briefF perform read/write to PHB HV register space
-/// @param[in] i_target         => phb target
-/// @param[in] i_perst_action   => input ACTIVATE or DEACTIVATE to control PERST signal from PHB>
 ///
-/// @return FAPI_RC_SUCCESS if the PERST action completes successfully.
+/// @brief Assert/deassert PERST signal from PHB.
+///
+/// @param[in] i_target         => PHB target
+/// @param[in] i_perst_action   => Input ACTIVATE or DEACTIVATE
+///                                to control PERST signal from PHB.
+///
+/// @return FAPI_RC_SUCCESS if the PERST action completes successfully, else
+///         FAPI2 error code.
+///
     fapi2::ReturnCode p9_perst_phb(const fapi2::Target<fapi2::TARGET_TYPE_PHB>& i_target,
                                    const PERST_ACTION i_perst_action);
 
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_perst_phb.xml b/src/import/chips/p9/procedures/xml/error_info/p9_perst_phb.xml
index 6e17a0c38..631f2fd17 100755
--- a/src/import/chips/p9/procedures/xml/error_info/p9_perst_phb.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_perst_phb.xml
@@ -23,6 +23,7 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- Error definitions for p9_perst_phb procedure -->
+
 <hwpErrors>
   <!-- ********************************************************************* -->
   <hwpError>
@@ -35,7 +36,7 @@
     <!-- Add procedure callout -->
     <callout>
       <procedure>CODE</procedure>
-      <priority>LOW</priority>
+      <priority>HIGH</priority>
     </callout>
   </hwpError>
   <!-- ********************************************************************* -->
@@ -51,16 +52,16 @@
     <ffdc>PHB_RESET_DATA</ffdc>
     <ffdc>CQ_STAT_ADDR</ffdc>
     <ffdc>CQ_STAT_DATA</ffdc>
-    <!-- Add procedure callout -->
-    <callout>
-      <procedure>CODE</procedure>
-      <priority>LOW</priority>
-    </callout>
     <!-- Add hw callout -->
     <callout>
       <target>TARGET</target>
       <priority>HIGH</priority>
     </callout>
+    <!-- Add procedure callout -->
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
@@ -73,16 +74,16 @@
     <ffdc>NFIR_DATA</ffdc>
     <ffdc>PFIR_ADDR</ffdc>
     <ffdc>PFIR_DATA</ffdc>
-    <!-- Add procedure callout -->
-    <callout>
-      <procedure>CODE</procedure>
-      <priority>LOW</priority>
-    </callout>
     <!-- Add hw callout -->
     <callout>
       <target>TARGET</target>
       <priority>HIGH</priority>
     </callout>
+    <!-- Add procedure callout -->
+    <callout>
+      <procedure>CODE</procedure>
+      <priority>LOW</priority>
+    </callout>
   </hwpError>
   <!-- ********************************************************************* -->
 </hwpErrors>