diff options
| author | crgeddes <crgeddes@us.ibm.com> | 2017-06-14 16:53:11 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-08-11 09:57:05 -0400 |
| commit | 18c1910fe597158178380a0cfb74504736b4fb3b (patch) | |
| tree | 45d0c6163bd0ef0aa02f26b4ba890ac84cba18e0 | |
| parent | eb8df8822f732c47e0ea3326da1691596206f90d (diff) | |
| download | talos-hostboot-18c1910fe597158178380a0cfb74504736b4fb3b.tar.gz talos-hostboot-18c1910fe597158178380a0cfb74504736b4fb3b.zip | |
Autogenerate targeting xmls for ekb attributes
CMVC-Prereq: 1028808
Change-Id: I3d50cf242fd4cf23358c553a1b5395950616637e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41860
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
27 files changed, 11438 insertions, 34274 deletions
diff --git a/src/build/mkrules/dist.targets.mk b/src/build/mkrules/dist.targets.mk index 6ab21b039..a4375eaa6 100755 --- a/src/build/mkrules/dist.targets.mk +++ b/src/build/mkrules/dist.targets.mk @@ -69,9 +69,10 @@ COPY_FILES = \ obj/genfiles/attrInfo.csv:vpo \ obj/genfiles/attrEnumInfo.csv:vpo \ obj/genfiles/targAttrInfo.csv:vpo \ - obj/genfiles/target_types_merged.xml:openpower \ obj/genfiles/fapiattrs.xml:openpower \ obj/genfiles/config.h:openpower \ + obj/genfiles/attribute_types_full.xml:openpower \ + obj/genfiles/target_types_full.xml:openpower \ src/usr/targeting/attroverride/README.attr_override:tools,openpower \ src/build/hwpf/prcd_compile.tcl:tools \ src/build/buildpnor/buildSbePart.pl:openpower \ @@ -115,7 +116,15 @@ COPY_FILES += $(if $(CONFIG_INCLUDE_XML_OPPOWERVM),src/usr/targeting/common/xmlt # Format is <dest file>:<source file>:<comma separated targets> # COPY_RENAME_FILES = \ - makefile:src/build/mkrules/hbfw/makefile:fsp\ + attribute_types.xml:obj/genfiles/attribute_types_full.xml:openpower \ + target_types_merged.xml:obj/genfiles/target_types_full.xml:openpower \ + attribute_types_hb.xml:src/usr/targeting/common/xmltohb/target_types_empty.xml:openpower \ + target_types_hb.xml:src/usr/targeting/common/xmltohb/target_types_empty.xml:openpower \ + attribute_types_oppowervm.xml:src/usr/targeting/common/xmltohb/target_types_empty.xml:openpower \ + target_types_oppowervm.xml:src/usr/targeting/common/xmltohb/target_types_empty.xml:openpower \ + attribute_types_openpower.xml:src/usr/targeting/common/xmltohb/target_types_empty.xml:openpower \ + target_types_openpower.xml:src/usr/targeting/common/xmltohb/target_types_empty.xml:openpower \ + makefile:src/build/mkrules/hbfw/makefile:fsp \ img/makefile:src/build/mkrules/hbfw/img/makefile:fsp \ hbicore.bin:img/hbicore$(UNDERSCORE_TEST).bin:vpo \ img/hostboot_bootloader.bin:img/hbibl.bin:fsp,openpower,vpo \ @@ -257,6 +266,8 @@ fsp.tar_CONTENTS = \ $(if $(CONFIG_SECUREBOOT),img/simics_CUMULUS_targeting.bin.protected) \ $(if $(CONFIG_SECUREBOOT),img/simics_CUMULUS_targeting.bin.unprotected) \ obj/genfiles/fapiattrs.xml \ + obj/genfiles/attribute_types_sp.xml \ + obj/genfiles/target_types_sp.xml \ obj/genfiles/hb_plat_attr_srvc.H \ src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml \ $(addsuffix :targeting/,\ diff --git a/src/build/mkrules/hbfw/makefile b/src/build/mkrules/hbfw/makefile index 44b087a5b..2f3f5ddd2 100755 --- a/src/build/mkrules/hbfw/makefile +++ b/src/build/mkrules/hbfw/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2012,2015 +# Contributors Listed Below - COPYRIGHT 2012,2017 # [+] International Business Machines Corp. # # @@ -63,10 +63,10 @@ TARFILES = fsp.tar simics.tar VPATH += fsp/hwas/common: -_SUBDIR/BUILD/SETUP/fsp: expand_tars_fsp.tar +_SUBDIR/BUILD/SETUP/fsp: expand_tars_fsp.tar overwrite_xml _SUBDIR/BUILD/SETUP/simics: expand_tars_simics.tar -SETUP_TARGETS += expand_tars +SETUP_TARGETS += expand_tars overwrite_xml EXPLIB_TARGETS += epub_check expand_tars: ${TARFILES:S/^/expand_tars_/g} @@ -76,8 +76,17 @@ expand_tars_%: $${@:S/expand_tars_//} @echo "===== src/hbfw/makefile: START EXTRACT of tarball $> :" `date` ${TAR} -x --file $> -C ${*:S/expand_tars_//} @echo "===== src/hbfw/makefile: END EXTRACT of tarball $> :" `date` + + +#Overwrites the old xml files with the new generated ones +overwrite_xml: expand_tars_fsp.tar + @echo "Replacing attribute_types.xml with attribute_types_sp.xml" + cp fsp/attribute_types_sp.xml fsp/targeting/common/xmltohb/attribute_types.xml + @echo "Replacing target_types.xml with target_types_sp.xml" + cp fsp/target_types_sp.xml fsp/targeting/common/xmltohb/target_types.xml + # Note that epub_check depends on expand_tars but it will always -# be run first due to force of it in EXPINC. +# be run first due to force of it in EXPINC. epub_check: epubProcedureID_check.pl epub_service_codes.H @echo "===== Checking epubProcedureID's Start:" `date` ${epubProcedureID_check.pl:P} ${epub_service_codes.H:P} ${hwasCallout.H:P} diff --git a/src/usr/hwas/common/deconfigGard.C b/src/usr/hwas/common/deconfigGard.C index 63787a046..d6b2f93e0 100644 --- a/src/usr/hwas/common/deconfigGard.C +++ b/src/usr/hwas/common/deconfigGard.C @@ -1573,11 +1573,14 @@ void DeconfigGard::_deconfigureByAssoc( targetService().getTopLevelTarget(pSys); HWAS_ASSERT(pSys, "HWAS _deconfigureByAssoc: no TopLevelTarget"); +#if 0 //@TODO RTC 178216 Re-Add this after proc_setup_bars_memory_attributes.xml + // is imported from ekb // done if not in interleaved mode if (!pSys->getAttr<ATTR_ALL_MCS_IN_INTERLEAVING_GROUP>()) { break; } +#endif // if paired mode (interleaved) // deconfigure paired MCS and MEMBUF (Centaur) // find paired MCS / MEMBUF (Centaur) @@ -1699,12 +1702,14 @@ void DeconfigGard::_deconfigureByAssoc( targetService().getTopLevelTarget(pSys); HWAS_ASSERT(pSys, "HWAS _deconfigureByAssoc: no TopLevelTarget"); +#if 0 //@TODO RTC 178216 Re-Add this after proc_setup_bars_memory_attributes.xml + // is imported from ekb // done if not in interleaved mode if (!pSys->getAttr<ATTR_ALL_MCS_IN_INTERLEAVING_GROUP>()) { break; } - +#endif // we need to make sure that MBA memory is balanced. // find parent MCS diff --git a/src/usr/isteps/istep06/thread_activate/thread_activate.C b/src/usr/isteps/istep06/thread_activate/thread_activate.C index c55205a28..dc7dce6ab 100644 --- a/src/usr/isteps/istep06/thread_activate/thread_activate.C +++ b/src/usr/isteps/istep06/thread_activate/thread_activate.C @@ -271,20 +271,20 @@ void activate_threads( errlHndl_t& io_rtaskRetErrl ) PVR_t l_pvr( mmio_pvr_read() & 0xFFFFFFFF ); if( l_pvr.isNimbusDD1() ) { - sys->setAttr<TARGETING::ATTR_FUSED_CORE_MODE> - (TARGETING::FUSED_CORE_MODE_SMT4_DEFAULT); + sys->setAttr<TARGETING::ATTR_FUSED_CORE_MODE_HB> + (TARGETING::FUSED_CORE_MODE_HB_SMT4_DEFAULT); } else { if( l_pvr.smt == PVR_t::SMT4_MODE ) { - sys->setAttr<TARGETING::ATTR_FUSED_CORE_MODE> - (TARGETING::FUSED_CORE_MODE_SMT4_ONLY); + sys->setAttr<TARGETING::ATTR_FUSED_CORE_MODE_HB> + (TARGETING::FUSED_CORE_MODE_HB_SMT4_ONLY); } else // SMT8_MODE { - sys->setAttr<TARGETING::ATTR_FUSED_CORE_MODE> - (TARGETING::FUSED_CORE_MODE_SMT8_ONLY); + sys->setAttr<TARGETING::ATTR_FUSED_CORE_MODE_HB> + (TARGETING::FUSED_CORE_MODE_HB_SMT8_ONLY); l_smt8 = true; } } diff --git a/src/usr/targeting/common/Targets.pm b/src/usr/targeting/common/Targets.pm index 943a741f8..3877ef475 100644 --- a/src/usr/targeting/common/Targets.pm +++ b/src/usr/targeting/common/Targets.pm @@ -1723,6 +1723,21 @@ sub getAttributeGroup return \%attr; } +## delete a target attribute +sub deleteAttribute +{ + my $self = shift; + my $target = shift; + my $Name = shift; + my $target_ptr = $self->{data}->{TARGETS}->{$target}; + if (!defined($target_ptr->{ATTRIBUTES}->{$Name})) + { + return 1; + } + delete($target_ptr->{ATTRIBUTES}->{$Name}); + $self->log($target, "Deleting attribute: $Name"); + return 0; +} ## renames a target attribute sub renameAttribute diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl index 80da2616d..4fca434ae 100755 --- a/src/usr/targeting/common/genHwsvMrwXml.pl +++ b/src/usr/targeting/common/genHwsvMrwXml.pl @@ -5093,6 +5093,10 @@ sub generate_obus <id>REL_POS</id> <default>$obus</default> </attribute> + <attribute> + <id>OPTICS_CONFIG_MODE</id> + <default>NV</default> + </attribute> "; addPervasiveParentLink($sys,$node,$proc,$obus,"obus"); diff --git a/src/usr/targeting/common/processMrw.pl b/src/usr/targeting/common/processMrw.pl index 4bf640950..70318f595 100755 --- a/src/usr/targeting/common/processMrw.pl +++ b/src/usr/targeting/common/processMrw.pl @@ -112,6 +112,37 @@ foreach my $target (sort keys %{ $targetObj->getAllTargets() }) if ($type eq "SYS") { processSystem($targetObj, $target); + #TODO RTC: 178351 Remove depricated Attribute from HB XML + #these are obsolete + $targetObj->deleteAttribute($target,"FUSED_CORE_MODE"); + $targetObj->deleteAttribute($target,"MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE"); + $targetObj->deleteAttribute($target,"MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE"); + $targetObj->deleteAttribute($target,"MRW_DRAMINIT_RESET_DISABLE"); + $targetObj->deleteAttribute($target,"MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP"); + $targetObj->deleteAttribute($target,"MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA"); + $targetObj->deleteAttribute($target,"MRW_STRICT_MBA_PLUG_RULE_CHECKING"); + $targetObj->deleteAttribute($target,"MSS_DRAMINIT_RESET_DISABLE"); + $targetObj->deleteAttribute($target,"MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_SLOT"); + $targetObj->deleteAttribute($target,"OPT_MEMMAP_GROUP_POLICY"); + $targetObj->deleteAttribute($target,"PFET_POWERDOWN_DELAY_NS"); + $targetObj->deleteAttribute($target,"PFET_POWERUP_DELAY_NS"); + $targetObj->deleteAttribute($target,"PFET_VCS_VOFF_SEL"); + $targetObj->deleteAttribute($target,"PFET_VDD_VOFF_SEL"); + $targetObj->deleteAttribute($target,"SYSTEM_IVRMS_ENABLED"); + $targetObj->deleteAttribute($target,"SYSTEM_RESCLK_ENABLE"); + $targetObj->deleteAttribute($target,"SYSTEM_WOF_ENABLED"); + $targetObj->deleteAttribute($target,"VDM_ENABLE"); + $targetObj->deleteAttribute($target,"CHIP_HAS_SBE"); + #handle enumeration changes + my $enum_val = $targetObj->getAttribute($target,"PROC_FABRIC_PUMP_MODE"); + if ( $enum_val =~ /MODE1/i) + { + $targetObj->setAttribute($target,"PROC_FABRIC_PUMP_MODE","CHIP_IS_NODE"); + } + elsif ( $enum_val =~ /MODE2/i) + { + $targetObj->setAttribute($target,"PROC_FABRIC_PUMP_MODE","CHIP_IS_GROUP"); + } } elsif ($type eq "PROC") { @@ -120,6 +151,29 @@ foreach my $target (sort keys %{ $targetObj->getAllTargets() }) { do_plugin("fsp_proc", $targetObj, $target); } + #TODO RTC: 178351 Remove depricated Attribute from HB XML + #these are obsolete + $targetObj->deleteAttribute($target,"CHIP_HAS_SBE"); + $targetObj->deleteAttribute($target,"FSI_GP_REG_SCOM_ACCESS"); + $targetObj->deleteAttribute($target,"I2C_SLAVE_ADDRESS"); + $targetObj->deleteAttribute($target,"LPC_BASE_ADDR"); + $targetObj->deleteAttribute($target,"NPU_MMIO_BAR_BASE_ADDR"); + $targetObj->deleteAttribute($target,"NPU_MMIO_BAR_SIZE"); + $targetObj->deleteAttribute($target,"PM_PFET_POWERDOWN_CORE_DELAY0"); + $targetObj->deleteAttribute($target,"PM_PFET_POWERDOWN_CORE_DELAY1"); + $targetObj->deleteAttribute($target,"PM_PFET_POWERDOWN_ECO_DELAY0"); + $targetObj->deleteAttribute($target,"PM_PFET_POWERDOWN_ECO_DELAY1"); + $targetObj->deleteAttribute($target,"PM_PFET_POWERUP_CORE_DELAY0"); + $targetObj->deleteAttribute($target,"PM_PFET_POWERUP_CORE_DELAY1"); + $targetObj->deleteAttribute($target,"PM_PFET_POWERUP_ECO_DELAY0"); + $targetObj->deleteAttribute($target,"PM_PFET_POWERUP_ECO_DELAY1"); + $targetObj->deleteAttribute($target,"PNOR_I2C_ADDRESS_BYTES"); + $targetObj->deleteAttribute($target,"PROC_PCIE_NUM_IOP"); + $targetObj->deleteAttribute($target,"PROC_PCIE_NUM_LANES"); + $targetObj->deleteAttribute($target,"PROC_PCIE_NUM_PEC"); + $targetObj->deleteAttribute($target,"PROC_PCIE_NUM_PHB"); + $targetObj->deleteAttribute($target,"PROC_SECURITY_SETUP_VECTOR"); + $targetObj->deleteAttribute($target,"SBE_SEEPROM_I2C_ADDRESS_BYTES"); } elsif ($type eq "APSS") { @@ -129,6 +183,30 @@ foreach my $target (sort keys %{ $targetObj->getAllTargets() }) { processMembuf($targetObj, $target); } + elsif ($type eq "DIMM") + { + #TODO RTC: 178351 Remove depricated Attribute from HB XML + $targetObj->deleteAttribute($target,"MBA_DIMM"); + $targetObj->deleteAttribute($target,"MBA_PORT"); + } + elsif ($type eq "PHB") + { + #TODO RTC: 178351 Remove depricated Attribute from HB XML + $targetObj->deleteAttribute($target,"DEVICE_ID"); + $targetObj->deleteAttribute($target,"HDDW_ORDER"); + $targetObj->deleteAttribute($target,"MAX_POWER"); + $targetObj->deleteAttribute($target,"MGC_LOAD_SOURCE"); + $targetObj->deleteAttribute($target,"PCIE_32BIT_DMA_SIZE"); + $targetObj->deleteAttribute($target,"PCIE_32BIT_MMIO_SIZE"); + $targetObj->deleteAttribute($target,"PCIE_64BIT_DMA_SIZE"); + $targetObj->deleteAttribute($target,"PCIE_64BIT_MMIO_SIZE"); + $targetObj->deleteAttribute($target,"PCIE_CAPABILITES"); + $targetObj->deleteAttribute($target,"PROC_PCIE_BAR_BASE_ADDR"); + $targetObj->deleteAttribute($target,"PROC_PCIE_NUM_LANES"); + $targetObj->deleteAttribute($target,"SLOT_INDEX"); + $targetObj->deleteAttribute($target,"SLOT_NAME"); + $targetObj->deleteAttribute($target,"VENDOR_ID"); + } processIpmiSensors($targetObj,$target); } @@ -574,6 +652,12 @@ sub processProcessor elsif ($child_type eq "OBUS") { processObus($targetObj, $child); + #handle enumeration changes + my $enum_val = $targetObj->getAttribute($child,"OPTICS_CONFIG_MODE"); + if ( $enum_val =~ /NVLINK/i) + { + $targetObj->setAttribute($child,"OPTICS_CONFIG_MODE","NV"); + } } elsif ($child_type eq "FSIM" || $child_type eq "FSICM") { @@ -985,6 +1069,11 @@ sub processObus foreach my $obrick (@{ $targetObj->getTargetChildren($target) }) { $targetObj->setAttribute($obrick, "OBUS_SLOT_INDEX", -1); + my $enum_val = $targetObj->getAttribute($obrick,"OPTICS_CONFIG_MODE"); + if ( $enum_val =~ /NVLINK/i) + { + $targetObj->setAttribute($obrick,"OPTICS_CONFIG_MODE","NV"); + } } } else @@ -1018,6 +1107,12 @@ sub processObus $targetObj->setAttribute($obrick, "OBUS_SLOT_INDEX", -1); } + + my $enum_val = $targetObj->getAttribute($obrick,"OPTICS_CONFIG_MODE"); + if ( $enum_val =~ /NVLINK/i) + { + $targetObj->setAttribute($obrick,"OPTICS_CONFIG_MODE","NV"); + } } } } diff --git a/src/usr/targeting/common/target.C b/src/usr/targeting/common/target.C index ec21890ec..fb651a27b 100644 --- a/src/usr/targeting/common/target.C +++ b/src/usr/targeting/common/target.C @@ -702,7 +702,6 @@ void setFrequencyAttributes( Target * i_sys, uint32_t l_newPll = (i_newNestFreq * l_oldPll)/l_oldNestFreq; // Needed for NEST_PLL_BUCKET - uint32_t l_i2cBusDiv = 0; size_t l_bucket; uint8_t nest_pll_freq_buckets = i_sys->getAttr<TARGETING::ATTR_NEST_PLL_FREQ_BUCKETS>(); @@ -748,7 +747,6 @@ void setFrequencyAttributes( Target * i_sys, "ATTR_NEST_PLL_BUCKET getting set to %x", l_bucket); i_sys->setAttr<TARGETING::ATTR_NEST_PLL_BUCKET>(l_bucket); - l_i2cBusDiv = i2cdiv_list[l_bucket-1]; break; } } @@ -765,13 +763,6 @@ void setFrequencyAttributes( Target * i_sys, TargetHandleList::iterator l_procTarget; - for( l_procTarget = l_procList.begin(); - l_procTarget != l_procList.end(); - ++l_procTarget ) - { - (*l_procTarget)->setAttr<TARGETING::ATTR_I2C_BUS_DIV_NEST>(l_i2cBusDiv); - } - TARG_EXIT(); #undef TARG_FN } diff --git a/src/usr/targeting/common/util.C b/src/usr/targeting/common/util.C index 92fec0365..c1be41203 100644 --- a/src/usr/targeting/common/util.C +++ b/src/usr/targeting/common/util.C @@ -326,13 +326,13 @@ uint8_t is_fused_mode( ) smt8_only / fused_cores / * --> fused */ - uint8_t l_mode = sys->getAttr<ATTR_FUSED_CORE_MODE>();; + uint8_t l_mode = sys->getAttr<ATTR_FUSED_CORE_MODE_HB>();; uint8_t l_option = sys->getAttr<ATTR_FUSED_CORE_OPTION>();; PAYLOAD_KIND l_payload = sys->getAttr<ATTR_PAYLOAD_KIND>(); if (FUSED_CORE_OPTION_USING_DEFAULT_CORES == l_option) { - if (FUSED_CORE_MODE_SMT4_DEFAULT == l_mode) + if (FUSED_CORE_MODE_HB_SMT4_DEFAULT == l_mode) { if (PAYLOAD_KIND_PHYP == l_payload) { @@ -343,7 +343,7 @@ uint8_t is_fused_mode( ) l_fused = false; } } - else if (FUSED_CORE_MODE_SMT4_ONLY == l_mode) + else if (FUSED_CORE_MODE_HB_SMT4_ONLY == l_mode) { l_fused = false; } diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml index 5e37e221f..357ffb31a 100644..100755 --- a/src/usr/targeting/common/xmltohb/attribute_types.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types.xml @@ -24,1501 +24,468 @@ <!-- IBM_PROLOG_END_TAG --> <attributes> - -<!-- ===================================================================== - HOST BOOT ATTRIBUTE TYPES - Contains the definition of all hostboot attributes which can be synced - to/from FSP - ================================================================= --> - -<enumerationType> - <id>CLASS</id> - <description>Enumeration indicating the target's class</description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>CARD</name> - <value>1</value> - </enumerator> - <enumerator> - <name>ENC</name> - <value>2</value> - </enumerator> - <enumerator> - <name>CHIP</name> - <value>3</value> - </enumerator> - <enumerator> - <name>UNIT</name> - <value>4</value> - </enumerator> - <enumerator> - <name>DEV</name> - <value>5</value> - </enumerator> - <enumerator> - <name>SYS</name> - <value>6</value> - </enumerator> - <enumerator> - <name>LOGICAL_CARD</name> - <value>7</value> - </enumerator> - <enumerator> - <name>BATTERY</name> - <value>8</value> - </enumerator> - <enumerator> - <name>LED</name> - <value>9</value> - </enumerator> - <enumerator> - <name>SP</name> - <value>10</value> - </enumerator> - <enumerator> - <name>MAX</name> - <value>11</value> - </enumerator> - <default>NA</default> -</enumerationType> - -<!-- The script genHwsvMrwXml.pl hardcodes the HUID type field to match - these values and should be kept in sync. Leave holes in in the range - if a type is deleted. Not changing the values keeps the values - consistent over builds making them easier to recognize. --> -<enumerationType> - <id>TYPE</id> - <description>Enumeration indicating the target's type</description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>SYS</name> - <value>1</value> - </enumerator> - <enumerator> - <name>NODE</name> - <value>2</value> - </enumerator> - <enumerator> - <name>DIMM</name> - <value>3</value> - </enumerator> - <enumerator> - <name>MEMBUF</name> - <value>4</value> - </enumerator> - <enumerator> - <name>PROC</name> - <value>5</value> - </enumerator> - <enumerator> - <name>EX</name> - <value>6</value> - </enumerator> - <enumerator> - <name>CORE</name> - <value>7</value> - </enumerator> - <enumerator> - <name>L2</name> - <value>8</value> - </enumerator> - <enumerator> - <name>L3</name> - <value>9</value> - </enumerator> - <enumerator> - <name>L4</name> - <value>10</value> - </enumerator> - <enumerator> - <name>MCS</name> - <value>11</value> - </enumerator> - <enumerator> - <name>MBA</name> - <value>13</value> - </enumerator> - <enumerator> - <name>XBUS</name> - <value>14</value> - </enumerator> - <enumerator> - <name>ABUS</name> - <value>15</value> - </enumerator> - <enumerator> - <name>PCI</name> - <value>16</value> - </enumerator> - <enumerator> - <name>DPSS</name> - <value>17</value> - </enumerator> - <enumerator> - <name>APSS</name> - <value>18</value> - </enumerator> - <enumerator> - <name>OCC</name> - <value>19</value> - </enumerator> - <enumerator> - <name>PSI</name> - <value>20</value> - </enumerator> - <enumerator> - <name>FSP</name> - <value>21</value> - </enumerator> - <enumerator> - <name>PNOR</name> - <value>22</value> - </enumerator> - <enumerator> - <name>OSC</name> - <value>23</value> - </enumerator> - <enumerator> - <name>TODCLK</name> - <value>24</value> - </enumerator> - <enumerator> - <name>CONTROL_NODE</name> - <value>25</value> - </enumerator> - <enumerator> - <name>OSCREFCLK</name> - <value>26</value> - </enumerator> - <enumerator> - <name>OSCPCICLK</name> - <value>27</value> - </enumerator> - <enumerator> - <name>REFCLKENDPT</name> - <value>28</value> - </enumerator> - <enumerator> - <name>PCICLKENDPT</name> - <value>29</value> - </enumerator> - <enumerator> - <name>NX</name> - <value>30</value> - </enumerator> - <enumerator> - <name>PORE</name> - <value>31</value> - </enumerator> - <enumerator> - <name>PCIESWITCH</name> - <value>32</value> - </enumerator> - <enumerator> - <name>CAPP</name> - <value>33</value> - </enumerator> - <enumerator> - <name>FSI</name> - <value>34</value> - </enumerator> - <!-- Add P9 targets --> - <enumerator> - <name>EQ</name> - <value>35</value> - </enumerator> - <enumerator> - <name>MCA</name> - <value>36</value> - </enumerator> - <enumerator> - <name>MCBIST</name> - <value>37</value> - </enumerator> - <enumerator> - <name>MI</name> - <value>38</value> - </enumerator> - <enumerator> - <name>DMI</name> - <value>39</value> - </enumerator> - <enumerator> - <name>OBUS</name> - <value>40</value> - </enumerator> - <!-- @TODO RTC:173529-Remove once NV is not used anywhere and leave a gap--> - <enumerator> - <name>NV</name> - <value>41</value> - </enumerator> - <enumerator> - <name>SBE</name> - <value>42</value> - </enumerator> - <enumerator> - <name>PPE</name> - <value>43</value> - </enumerator> - <enumerator> - <name>PERV</name> - <value>44</value> - </enumerator> - <enumerator> - <name>PEC</name> - <value>45</value> - </enumerator> - <enumerator> - <name>PHB</name> - <value>46</value> - </enumerator> - <enumerator> - <name>SYSREFCLKENDPT</name> - <value>47</value> - </enumerator> - <enumerator> - <name>MFREFCLKENDPT</name> - <value>48</value> - </enumerator> - <enumerator> - <name>TPM</name> - <value>49</value> - </enumerator> - <enumerator> - <name>SP</name> - <value>50</value> - </enumerator> - <enumerator> - <name>UART</name> - <value>51</value> - </enumerator> - <enumerator> - <name>PS</name> - <value>52</value> - </enumerator> - <enumerator> - <name>FAN</name> - <value>53</value> - </enumerator> - <enumerator> - <name>VRM</name> - <value>54</value> - </enumerator> - <enumerator> - <name>USB</name> - <value>55</value> - </enumerator> - <enumerator> - <name>ETH</name> - <value>56</value> - </enumerator> - <enumerator> - <name>PANEL</name> - <value>57</value> - </enumerator> - <enumerator> - <name>BMC</name> - <value>58</value> - </enumerator> - <enumerator> - <name>FLASH</name> - <value>59</value> - </enumerator> - <enumerator> - <name>SEEPROM</name> - <value>60</value> - </enumerator> - <enumerator> - <name>TMP</name> - <value>61</value> - </enumerator> - <enumerator> - <name>GPIO_EXPANDER</name> - <value>62</value> - </enumerator> - <enumerator> - <name>POWER_SEQUENCER</name> - <value>63</value> - </enumerator> - <enumerator> - <name>RTC</name> - <value>64</value> - </enumerator> - <enumerator> - <name>FANCTLR</name> - <value>65</value> - </enumerator> - <enumerator> - <name>OBUS_BRICK</name> - <value>66</value> - </enumerator> - <enumerator> - <name>NPU</name> - <value>67</value> - </enumerator> - <enumerator> - <name>MC</name> - <value>68</value> - </enumerator> - <!-- add any new types here, and increment TEST_FAIL and LAST_IN_RANGE --> - <enumerator> - <name>TEST_FAIL</name> - <value>69</value> - </enumerator> - <enumerator> - <name>MFREFCLK</name> - <value>70</value> - </enumerator> - <enumerator> - <name>LAST_IN_RANGE</name> - <value>71</value> - </enumerator> - <default>NA</default> -</enumerationType> - -<enumerationType> - <id>MODEL</id> - <description>Enumeration indicating the target's model</description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>RESERVED</name><!-- Left here to keep later values the same --> - <value>16</value> - </enumerator> - <enumerator> - <name>VENICE</name> - </enumerator> - <enumerator> - <name>MURANO</name> - </enumerator> - <enumerator> - <name>NAPLES</name> - </enumerator> - <enumerator> - <name>NIMBUS</name> - </enumerator> - <enumerator> - <name>CUMULUS</name> - </enumerator> - <enumerator> - <name>CENTAUR</name> - <value>48</value> - </enumerator> - <enumerator> - <name>JEDEC</name> - <value>80</value> - </enumerator> - <enumerator> - <name>CDIMM</name> - </enumerator> - <!-- POWER8 is system/node model, not processor chip level --> - <enumerator> - <name>POWER8</name> - <value>112</value> - </enumerator> - <!-- POWER9 is system/node model, not processor chip level --> - <enumerator> - <name>POWER9</name> - <value>144</value> - </enumerator> - <enumerator> - <name>CECTPM</name> - </enumerator> - <enumerator> - <name>BMC</name> - </enumerator> - <enumerator> - <name>AST2500</name> - </enumerator> - <default>NA</default> -</enumerationType> - -<enumerationType> - <id>ENGINE_TYPE</id> - <description>Enumeration indicating the target's engine type</description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>ENGINE_IIC</name> - <value>1</value> - </enumerator> - <enumerator> - <name>ENGINE_SCOM</name> - <value>2</value> - </enumerator> - <default>NA</default> -</enumerationType> - -<enumerationType> - <id>FSI_MASTER_TYPE</id> - <description>Enumeration indicating the master's FSI type</description> - <enumerator> - <name>MFSI</name> - <value>0</value> - </enumerator> - <enumerator> - <name>CMFSI</name> - <value>1</value> - </enumerator> - <enumerator> - <name>NO_MASTER</name> - <value>2</value> - </enumerator> - <default>NO_MASTER</default> -</enumerationType> - -<attribute> - <id>CLASS</id> + <attribute> <description>Attribute indicating the target's class</description> + <hasStringConversion></hasStringConversion> + <id>CLASS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <enumeration> - <id>CLASS</id> - </enumeration> + <enumeration> + <id>CLASS</id> + </enumeration> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hasStringConversion/> -</attribute> + </attribute> -<attribute> - <id>TYPE</id> + <attribute> <description>Attribute indicating the target's type</description> + <hasStringConversion></hasStringConversion> + <id>TYPE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <enumeration> - <id>TYPE</id> - </enumeration> + <enumeration> + <id>TYPE</id> + </enumeration> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hasStringConversion/> -</attribute> + </attribute> -<attribute> - <id>MODEL</id> + <attribute> <description>Attribute indicating the target's model</description> + <hasStringConversion></hasStringConversion> + <id>MODEL</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <enumeration> - <id>MODEL</id> - </enumeration> + <enumeration> + <id>MODEL</id> + </enumeration> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hasStringConversion/> -</attribute> + </attribute> -<attribute> - <id>ENGINE_TYPE</id> + <attribute> <description>Attribute indicating the target's engine type</description> - <simpleType> - <enumeration> - <id>ENGINE_TYPE</id> - </enumeration> - </simpleType> + <hasStringConversion></hasStringConversion> + <id>ENGINE_TYPE</id> <persistency>non-volatile</persistency> - <readable/> - <hasStringConversion/> -</attribute> -<attribute> - <id>SCRATCH_UINT8_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT8_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT8_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT8_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT8_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int8_t> - </int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT8_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT8_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int8_t> - </int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT8_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT16_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint16_t> - </uint16_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT16_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<attribute> - <id>SCRATCH_UINT16_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint16_t> - </uint16_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT16_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT16_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int16_t> - </int16_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT16_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<attribute> - <id>SCRATCH_INT16_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int16_t> - </int16_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT16_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT32_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT32_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT32_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT32_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT32_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT32_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT32_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT32_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT64_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT64_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT64_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT64_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT64_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int64_t> - </int64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT64_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT64_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int64_t> - </int64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT64_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT8_ARRAY_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>32</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT8_ARRAY_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT8_ARRAY_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2, 3, 4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT8_ARRAY_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT8_ARRAY_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int8_t> - </int8_t> - <array>32</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT8_ARRAY_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT8_ARRAY_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int8_t> - </int8_t> - <array>2, 3, 4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT8_ARRAY_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT16_ARRAY_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint16_t> - </uint16_t> - <array>16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT16_ARRAY_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT16_ARRAY_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint16_t> - </uint16_t> - <array>2, 3, 2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT16_ARRAY_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT16_ARRAY_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int16_t> - </int16_t> - <array>16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT16_ARRAY_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT16_ARRAY_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int16_t> - </int16_t> - <array>2, 3, 2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT16_ARRAY_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT32_ARRAY_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>8</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT32_ARRAY_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_UINT32_ARRAY_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,3</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT32_ARRAY_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT32_ARRAY_1</id> - <description>Scratch attribute that can be used for dev/test</description> + <readable></readable> <simpleType> - <int32_t> - </int32_t> - <array>8</array> + <enumeration> + <id>ENGINE_TYPE</id> + </enumeration> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT32_ARRAY_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCRATCH_INT32_ARRAY_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int32_t> - </int32_t> - <array>2,3</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT32_ARRAY_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>SCRATCH_UINT64_ARRAY_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint64_t> - </uint64_t> - <array>4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT64_ARRAY_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> <attribute> - <id>SCRATCH_UINT64_ARRAY_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <uint64_t> - </uint64_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_UINT64_ARRAY_2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <id>SYSTEM_IPL_PHASE</id> + <description>Define context for current phase of system IPL. + Provided by the platform. + HB_IPL = 0x1,HB_RUNTIME = 0x2,CACHE_CONTAINED = 0x4</description> + <simpleType> + <uint8_t> + <default>0x01</default> + </uint8_t> + </simpleType> + <hwpfToHbAttrMap> + <id>ATTR_SYSTEM_IPL_PHASE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> </attribute> -<attribute> - <id>SCRATCH_INT64_ARRAY_1</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int64_t> - </int64_t> - <array>4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT64_ARRAY_1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<attribute> - <id>SCRATCH_INT64_ARRAY_2</id> - <description>Scratch attribute that can be used for dev/test</description> - <simpleType> - <int64_t> - </int64_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> + <attribute> + <description>Dummy attribute with read/write permissions</description> <hwpfToHbAttrMap> - <id>ATTR_SCRATCH_INT64_ARRAY_2</id> - <macro>DIRECT</macro> + <id>ATTR_DUMMY_SCRATCH_PLAT_INIT_UINT8</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> <id>DUMMY_RW</id> - <description>Dummy attribute with read/write permissions</description> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - <default>5</default> - </uint8_t> - <array>1,3,5</array> + <array>1,3,5</array> + <uint8_t> + <default>5</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_DUMMY_SCRATCH_PLAT_INIT_UINT8</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + <ignoreEkb/> + </attribute> -<attribute> - <id>DUMMY_WO</id> + <attribute> <description>Dummy attribute with write-only permissions</description> + <id>DUMMY_WO</id> + <persistency>non-volatile</persistency> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>DUMMY_RO</id> + <attribute> <description>Dummy attribute with read-only permissions</description> + <id>DUMMY_RO</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>DUMMY_HEAP_ZERO_DEFAULT</id> + <attribute> <description>Dummy attribute on the heap with zero initialization</description> + <id>DUMMY_HEAP_ZERO_DEFAULT</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>PHYS_PATH</id> + <attribute> <description>Physical hierarchical path to the target</description> + <id>PHYS_PATH</id> <nativeType> - <name>EntityPath</name> + <name>EntityPath</name> </nativeType> <persistency>non-volatile</persistency> - <readable/> + <readable></readable> <no_export/> -</attribute> + </attribute> -<attribute> - <id>AFFINITY_PATH</id> + <attribute> <description>Hierarchical path to the target with respect to logical affinity</description> + <id>AFFINITY_PATH</id> <nativeType> - <name>EntityPath</name> + <name>EntityPath</name> </nativeType> <persistency>non-volatile</persistency> - <readable/> + <readable></readable> <no_export/> -</attribute> + </attribute> -<attribute> - <id>POWER_PATH</id> + <attribute> <description>Hierarchical path to the target with respect to power</description> + <id>POWER_PATH</id> <nativeType> - <name>EntityPath</name> + <name>EntityPath</name> </nativeType> <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + </attribute> -<attribute> - <id>PRIMARY_CAPABILITIES</id> - <description>Attribute which describes capabilities of a target</description> + <attribute> <complexType> - <description>Structure which defines a target's primary capabilities. + <description>Structure which defines a target's primary capabilities. A target can only support at most FSI SCOM and one of the other two SCOM types. Applicable for all targets. Structure is read-only. </description> - <field> - <name>supportsFsiScom</name> - <description>0b0: Target does not support FSI SCOM; + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Target does not support FSI SCOM; 0b1: Target supports FSI SCOM </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>supportsXscom</name> - <description>0b0: Target does not support XSCOM; + <name>supportsFsiScom</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Target does not support XSCOM; 0b1: Target supports FSI XSCOM</description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>supportsInbandScom</name> - <description>0b0: Target does not support inband SCOM</description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>reserved</name> - <description>Reserved for future use</description> - <type>uint8_t</type> - <bits>5</bits> - <default>0</default> - </field> - </complexType> + <name>supportsXscom</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Target does not support inband SCOM</description> + <name>supportsInbandScom</name> + <type>uint8_t</type> + </field> + <field> + <bits>5</bits> + <default>0</default> + <description>Reserved for future use</description> + <name>reserved</name> + <type>uint8_t</type> + </field> + </complexType> + <description>Attribute which describes capabilities of a target</description> + <id>PRIMARY_CAPABILITIES</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + </attribute> -<attribute> - <id>CPU_ATTR</id> + <attribute> <description>CPU Attribute</description> + <id>CPU_ATTR</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>SCOM_SWITCHES</id> - <description>Attribute storing information about which SCOM path to use</description> + <attribute> <complexType> - <description>Structure which defines which SCOM to use at a point in + <description>Structure which defines which SCOM to use at a point in time. Only applicable if target supports one or more SCOM types. Only one bit (of the first three) can ever be set at any one time. </description> - <field> - <name>useFsiScom</name> - <description>0b0: Do not use FSI SCOM at this time. 0b1: Use FSI + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use FSI SCOM at this time. 0b1: Use FSI SCOM at this time</description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>useXscom</name> - <description>0b0: Do not use XSCOM at this time. 0b1: Use XSCOM at + <name>useFsiScom</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use XSCOM at this time. 0b1: Use XSCOM at this time</description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>useInbandScom</name> - <description>0b0: Do not use inband SCOM at this time. 0b1: Use + <name>useXscom</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use inband SCOM at this time. 0b1: Use inband SCOM at this time</description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>useSbeScom</name> - <description>0b0: Do not use SBE SCOM at this time. 0b1: Use + <name>useInbandScom</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use SBE SCOM at this time. 0b1: Use SBE SCOM at this time</description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>reserved</name> - <description>Reserved for future expansion</description> - <type>uint8_t</type> - <bits>4</bits> - <default>0</default> - </field> + <name>useSbeScom</name> + <type>uint8_t</type> + </field> + <field> + <bits>4</bits> + <default>0</default> + <description>Reserved for future expansion</description> + <name>reserved</name> + <type>uint8_t</type> + </field> </complexType> + <description>Attribute storing information about which SCOM path to use</description> + <id>SCOM_SWITCHES</id> <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>ISDIMM_MBVPD_INDEX</id> - <description> - Multiple centaurs can sometimes have their VPD located in one - physical SEEPROM. This is the index into the memory buffer VPD - for this centaur. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_ISDIMM_MBVPD_INDEX</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <no_export/> -</attribute> + <readable></readable> + <writeable></writeable> + </attribute> -<attribute> - <id>FSI_MASTER_CHIP</id> + <attribute> <description>Chip which contains the FSI master logic that drives this slave when booting from the default master processor</description> + <id>FSI_MASTER_CHIP</id> <nativeType> - <name>EntityPath</name> - <default>physical:sys-0</default> + <default>physical:sys-0</default> + <name>EntityPath</name> </nativeType> <persistency>non-volatile</persistency> - <readable/> + <readable></readable> <no_export/> -</attribute> + </attribute> -<attribute> - <id>ALTFSI_MASTER_CHIP</id> + <attribute> <description>Chip which contains the FSI master logic that drives this slave when booting from the alternate master processor</description> + <id>ALTFSI_MASTER_CHIP</id> <nativeType> - <name>EntityPath</name> - <default>physical:sys-0</default> + <default>physical:sys-0</default> + <name>EntityPath</name> </nativeType> <persistency>non-volatile</persistency> - <readable/> + <readable></readable> <no_export/> -</attribute> + </attribute> -<attribute> - <id>FSI_MASTER_TYPE</id> + <attribute> <description>Type of Master FSI connection to this slave (MFSI or cMFSI)</description> + <hasStringConversion></hasStringConversion> + <id>FSI_MASTER_TYPE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <enumeration> - <id>FSI_MASTER_TYPE</id> - <default>NO_MASTER</default> - </enumeration> + <enumeration> + <default>NO_MASTER</default> + <id>FSI_MASTER_TYPE</id> + </enumeration> </simpleType> - <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> <no_export/> -</attribute> + </attribute> -<attribute> - <id>FSI_MASTER_PORT</id> + <attribute> <description>Which port is this chip hanging off of when booting from the default master processor</description> + <id>FSI_MASTER_PORT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - <default>0xFF</default> - </uint8_t> + <uint8_t> + <default>0xFF</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> + </attribute> -<attribute> - <id>ALTFSI_MASTER_PORT</id> + <attribute> <description>Which port is this chip hanging off of when booting from the alternate master processor</description> + <id>ALTFSI_MASTER_PORT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - <default>0xFF</default> - </uint8_t> + <uint8_t> + <default>0xFF</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> - -<attribute> - <id>I2C_SLAVE_ADDRESS</id> - <description>I2C Slave Address</description> - <simpleType> - <uint8_t> - <default>0x00</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_I2C_SLAVE_ADDRESS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>FSI_SLAVE_CASCADE</id> + <attribute> <description>Slave cascade position</description> + <id>FSI_SLAVE_CASCADE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> + </attribute> -<attribute> - <id>FSI_OPTION_FLAGS</id> - <description> - Reserved for any special flags we might need to access FSI - </description> + <attribute> <complexType> - <description>FSI flags</description> - <field> - <name>flipPort</name> - <description> + <description>FSI flags</description> + <field> + <bits>1</bits> + <default>0</default> + <description> Set on FSI master chips (procs) if that chip uses slaveB to attach to the acting master chip. </description> - <type>uint16_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>reserved</name> - <description>Reserved for future expansion</description> - <type>uint16_t</type> - <bits>15</bits> - <default>0</default> - </field> + <name>flipPort</name> + <type>uint16_t</type> + </field> + <field> + <bits>15</bits> + <default>0</default> + <description>Reserved for future expansion</description> + <name>reserved</name> + <type>uint16_t</type> + </field> </complexType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>EXECUTION_PLATFORM</id> <description> - Which execution platform the HW Procedure is running on - Some HWPs (e.g. special wakeup) use different registers for different - platforms to avoid arbitration problems when multiple platforms do - the same thing concurrently - HOST = 0x01, FSP = 0x02, OCC = 0x03 + Reserved for any special flags we might need to access FSI </description> - <simpleType><uint8_t></uint8_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EXECUTION_PLATFORM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IS_SIMULATION</id> - <description>env: 1 = Awan/HWSimulator. 0 = Simics/RealHW.</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <id>FSI_OPTION_FLAGS</id> <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_IS_SIMULATION</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <readable></readable> + </attribute> -<attribute> - <id>HWAS_STATE</id> - <description>HardWare Availability Service State Attribute. - Keeps track of Target values poweredOn, present, functional</description> + <attribute> <complexType> - <description>struct - 4 booleans and a PLID</description> - <field> - <name>deconfiguredByEid</name> - <description>if this target was deconfigured, + <description>struct - 4 booleans and a PLID</description> + <field> + <default>0</default> + <description>if this target was deconfigured, this will be a special DECONFIGURED_BY_ enum, OR it will be the errlog EID that caused it, either directly or by association, </description> - <type>uint32_t</type> - <default>0</default> - </field> - <field> - <name>poweredOn</name> - <description> + <name>deconfiguredByEid</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description> 0b0: Target is not powered on (is off); 0b1: Target is powered on; </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>present</name> - <description> + <name>poweredOn</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description> 0b0: Target is not present in the system; 0b1: Target is present in the system </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>functional</name> - <description> + <name>present</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description> 0b0: Target is not functional; 0b1: Target is functional </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>dumpfunctional</name> - <description>FSP Only, used by DUMP applet; + <name>functional</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>FSP Only, used by DUMP applet; 0b0: target is dump capabile; 0b1: target is not dump capabile; </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>specdeconfig</name> - <description>Set for speculative deconfig; + <name>dumpfunctional</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>Set for speculative deconfig; 0b0: target not speculative deconfig; 0b1: target is speculatively deconfigured; </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> + <name>specdeconfig</name> + <type>uint8_t</type> + </field> </complexType> + <description>HardWare Availability Service State Attribute. + Keeps track of Target values poweredOn, present, functional</description> + <id>HWAS_STATE</id> <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> + <readable></readable> + <writeable></writeable> + </attribute> -<attribute> - <id>HWAS_STATE_CHANGED_FLAG</id> + <attribute> <description>HardWare Availability Service State Changed Attribute. Keeps track of changedSinceChecked state, indicates if the target has changed since last checked by the appropriate service. This is a bit field of flags (see HWAS_CHANGED_BIT enumeration that follows). </description> + <id>HWAS_STATE_CHANGED_FLAG</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <default>0x0</default> - </uint64_t> + <uint64_t> + <default>0x0</default> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <attribute> <description>HardWare Availability Service State Changed Mask. Used when a target changes (ie, via HCDB change) to set the HWAS_STATE_CHANGED_FLAG, so that the appropriate services will @@ -1526,183 +493,134 @@ This is a bit field of flags (see HWAS_CHANGED_BIT enumeration that follows). </description> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <default>0x0</default> - </uint64_t> + <uint64_t> + <default>0x0</default> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<enumerationType> - <id>HWAS_CHANGED_BIT</id> - <description>Enumeration indicating the services that are concerned - with target changes (ie, via HCDB change). - The values can be combined using a bitwise 'OR'. - </description> - <enumerator> - <name>GARD</name> - <value>0x00000001</value> - </enumerator> - <enumerator> - <name>MEMDIAG</name> - <value>0x00000002</value> - </enumerator> - <enumerator> - <name>PSIDIAG</name> - <value>0x00000004</value> - </enumerator> - <!-- combination of all DIAG values --> - <!-- if you add a DIAG flag above, add the bit in the mask below --> - <enumerator> - <name>DIAG_MASK</name> - <value>0x00000006</value> - </enumerator> - <enumerator> - <name>HOSTSVC_HBEL</name> - <value>0x00000008</value> - </enumerator> -</enumerationType> + </attribute> -<!-- For POD Testing --> -<attribute> - <id>NUMERIC_POD_TYPE_TEST</id> - <description>Attribute which tests numeric POD types</description> + <attribute> <complexType> - <description>Numeric POD type test structure</description> - <field> - <name>fsiPath</name> - <description>Entity path for testing purposes</description> - <type>EntityPath</type> - <default>physical:sys-0</default> - </field> - <field> - <name>className</name> - <description>Class for testing purposes</description> - <type>CLASS</type> - <default>CHIP</default> - </field> - <field> - <name>uint8</name> - <description>Test uint8</description> - <type>uint8_t</type> - <default>0xAB</default> - </field> - <field> - <name>uint16</name> - <description>Test uint16</description> - <type>uint16_t</type> - <default>0xABCD</default> - </field> - <field> - <name>uint32</name> - <description>Test uint32</description> - <type>uint32_t</type> - <default>0xABCDEF01</default> - </field> - <field> - <name>uint64</name> - <description>Test uint64</description> - <type>uint64_t</type> - <default>0xABCDEF0123456789</default> - </field> - <field> - <name>int8</name> - <description>Test int8</description> - <type>int8_t</type> - <default>-124</default> - </field> - <field> - <name>int16</name> - <description>Test int16</description> - <type>int16_t</type> - <default>-32764</default> - </field> - <field> - <name>int32</name> - <description>Test int32</description> - <type>int32_t</type> - <default>-2147483644</default> - </field> - <field> - <name>int64</name> - <description>Test int64</description> - <type>int64_t</type> - <default>-9223372036854775804</default> - </field> - </complexType> + <description>Numeric POD type test structure</description> + <field> + <default>physical:sys-0</default> + <description>Entity path for testing purposes</description> + <name>fsiPath</name> + <type>EntityPath</type> + </field> + <field> + <default>CHIP</default> + <description>Class for testing purposes</description> + <name>className</name> + <type>CLASS</type> + </field> + <field> + <default>0xAB</default> + <description>Test uint8</description> + <name>uint8</name> + <type>uint8_t</type> + </field> + <field> + <default>0xABCD</default> + <description>Test uint16</description> + <name>uint16</name> + <type>uint16_t</type> + </field> + <field> + <default>0xABCDEF01</default> + <description>Test uint32</description> + <name>uint32</name> + <type>uint32_t</type> + </field> + <field> + <default>0xABCDEF0123456789</default> + <description>Test uint64</description> + <name>uint64</name> + <type>uint64_t</type> + </field> + <field> + <default>-124</default> + <description>Test int8</description> + <name>int8</name> + <type>int8_t</type> + </field> + <field> + <default>-32764</default> + <description>Test int16</description> + <name>int16</name> + <type>int16_t</type> + </field> + <field> + <default>-2147483644</default> + <description>Test int32</description> + <name>int32</name> + <type>int32_t</type> + </field> + <field> + <default>-9223372036854775804</default> + <description>Test int64</description> + <name>int64</name> + <type>int64_t</type> + </field> + </complexType> + <description>Attribute which tests numeric POD types</description> + <id>NUMERIC_POD_TYPE_TEST</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + </attribute> -<attribute> - <id>DECONFIG_GARDABLE</id> + <attribute> <description>If the Target is directly deconfigurable and GARDable; target may still be deconfigured in 'by association' processing.</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <id>DECONFIG_GARDABLE</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>ISTEP_MODE</id> - <description>If True, puts HostBoot into SPLess SingleStep mode.</description> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_ISTEP_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>EEPROM_VPD_PRIMARY_INFO</id> - <description>Information needed to address the EEPROM slaves</description> + <attribute> <complexType> - <description>Structure to define the addressing for an I2C + <description>Structure to define the addressing for an I2C slave device.</description> - <field> - <name>i2cMasterPath</name> - <description>Entity path to the chip that contains the I2C + <field> + <default>physical:sys-0</default> + <description>Entity path to the chip that contains the I2C master</description> - <type>EntityPath</type> - <default>physical:sys-0</default> - </field> - <field> - <name>port</name> - <description>Port from the I2C Master device. This is a 6-bit + <name>i2cMasterPath</name> + <type>EntityPath</type> + </field> + <field> + <default>0x80</default> + <description>Port from the I2C Master device. This is a 6-bit value.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>devAddr</name> - <description>Device address on the I2C bus. This is a 7-bit value, + <name>port</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>Device address on the I2C bus. This is a 7-bit value, but then shifted 1 bit left.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>engine</name> - <description>I2C master engine. This is a 2-bit + <name>devAddr</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>I2C master engine. This is a 2-bit value.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>byteAddrOffset</name> - <description> + <name>engine</name> + <type>uint8_t</type> + </field> + <field> + <default>0x02</default> + <description> The number of bytes a device requires to set its internal address/offset. DDR4 DIMMs require a special EEPROM page switching mechanic denoted here by a value of 1 @@ -1711,974 +629,513 @@ 2 = Two Byte Addressing 3 = OneByte Addressing with no page select </description> - <type>uint8_t</type> - <default>0x02</default> - </field> - <field> - <name>maxMemorySizeKB</name> - <description>The number of kilobytes a device can hold. 'Zero' + <name>byteAddrOffset</name> + <type>uint8_t</type> + </field> + <field> + <default>0x0</default> + <description>The number of kilobytes a device can hold. 'Zero' value possible for some devices.</description> - <type>uint64_t</type> - <default>0x0</default> - </field> - <field> - <name>chipCount</name> - <description>The number of chips making up an eeprom device. + <name>maxMemorySizeKB</name> + <type>uint64_t</type> + </field> + <field> + <default>0x01</default> + <description>The number of chips making up an eeprom device. </description> - <type>uint8_t</type> - <default>0x01</default> - </field> - <field> - <name>writePageSize</name> - <description>The maximum number of bytes that can be written to + <name>chipCount</name> + <type>uint8_t</type> + </field> + <field> + <default>0x0</default> + <description>The maximum number of bytes that can be written to a device at one time. 'Zero' value means no maximum value is expected or checked.</description> - <type>uint64_t</type> - <default>0x0</default> - </field> - <field> - <name>writeCycleTime</name> - <description>The amount of time in milliseconds a device requires + <name>writePageSize</name> + <type>uint64_t</type> + </field> + <field> + <default>0xA</default> + <description>The amount of time in milliseconds a device requires on the completion of a write command to update its internal memory.</description> - <type>uint64_t</type> - <default>0xA</default> - </field> + <name>writeCycleTime</name> + <type>uint64_t</type> + </field> </complexType> + <description>Information needed to address the EEPROM slaves</description> + <id>EEPROM_VPD_PRIMARY_INFO</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + </attribute> -<attribute> - <id>EEPROM_VPD_BACKUP_INFO</id> - <description>Information needed to address the EERPROM slaves</description> + <attribute> <complexType> - <description>Structure to define the addressing for an I2C + <description>Structure to define the addressing for an I2C slave device.</description> - <field> - <name>i2cMasterPath</name> - <description>Entity path to the chip that contains the I2C + <field> + <default>physical:sys-0</default> + <description>Entity path to the chip that contains the I2C master</description> - <type>EntityPath</type> - <default>physical:sys-0</default> - </field> - <field> - <name>port</name> - <description>Port from the I2C Master device. This is a 6-bit + <name>i2cMasterPath</name> + <type>EntityPath</type> + </field> + <field> + <default>0x80</default> + <description>Port from the I2C Master device. This is a 6-bit value.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>devAddr</name> - <description>Device address on the I2C bus. This is a 7-bit value, + <name>port</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>Device address on the I2C bus. This is a 7-bit value, but then shifted 1 bit left.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>engine</name> - <description>I2C master engine. This is a 2-bit + <name>devAddr</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>I2C master engine. This is a 2-bit value.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>byteAddrOffset</name> - <description>The number of bytes a device requires to set its + <name>engine</name> + <type>uint8_t</type> + </field> + <field> + <default>0x02</default> + <description>The number of bytes a device requires to set its internal address/offset.</description> - <type>uint8_t</type> - <default>0x02</default> - </field> - <field> - <name>maxMemorySizeKB</name> - <description>The number of kilobytes a device can hold. 'Zero' + <name>byteAddrOffset</name> + <type>uint8_t</type> + </field> + <field> + <default>0x0</default> + <description>The number of kilobytes a device can hold. 'Zero' value possible for some devices.</description> - <type>uint64_t</type> - <default>0x0</default> - </field> - <field> - <name>chipCount</name> - <description>The number of chips making up an eeprom device. + <name>maxMemorySizeKB</name> + <type>uint64_t</type> + </field> + <field> + <default>0x01</default> + <description>The number of chips making up an eeprom device. </description> - <type>uint8_t</type> - <default>0x01</default> - </field> - <field> - <name>writePageSize</name> - <description>The maximum number of bytes that can be written to + <name>chipCount</name> + <type>uint8_t</type> + </field> + <field> + <default>0x0</default> + <description>The maximum number of bytes that can be written to a device at one time. 'Zero' value means no maximum value is expected or checked.</description> - <type>uint64_t</type> - <default>0x0</default> - </field> - <field> - <name>writeCycleTime</name> - <description>The amount of time in milliseconds a device requires + <name>writePageSize</name> + <type>uint64_t</type> + </field> + <field> + <default>0xA</default> + <description>The amount of time in milliseconds a device requires on the completion of a write command to update its internal memory.</description> - <type>uint64_t</type> - <default>0xA</default> - </field> + <name>writeCycleTime</name> + <type>uint64_t</type> + </field> </complexType> + <description>Information needed to address the EERPROM slaves</description> + <id>EEPROM_VPD_BACKUP_INFO</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + </attribute> -<attribute> - <id>EEPROM_SBE_PRIMARY_INFO</id> - <description>Information needed to address the EERPROM slaves</description> + <attribute> <complexType> - <description>Structure to define the addressing for an I2C + <description>Structure to define the addressing for an I2C slave device.</description> - <field> - <name>i2cMasterPath</name> - <description>Entity path to the chip that contains the I2C + <field> + <default>physical:sys-0</default> + <description>Entity path to the chip that contains the I2C master</description> - <type>EntityPath</type> - <default>physical:sys-0</default> - </field> - <field> - <name>port</name> - <description>Port from the I2C Master device. This is a 6-bit + <name>i2cMasterPath</name> + <type>EntityPath</type> + </field> + <field> + <default>0x80</default> + <description>Port from the I2C Master device. This is a 6-bit value.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>devAddr</name> - <description>Device address on the I2C bus. This is a 7-bit value, + <name>port</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>Device address on the I2C bus. This is a 7-bit value, but then shifted 1 bit left.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>engine</name> - <description>I2C master engine. This is a 2-bit + <name>devAddr</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>I2C master engine. This is a 2-bit value.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>byteAddrOffset</name> - <description>The number of bytes a device requires to set its + <name>engine</name> + <type>uint8_t</type> + </field> + <field> + <default>0x02</default> + <description>The number of bytes a device requires to set its internal address/offset.</description> - <type>uint8_t</type> - <default>0x02</default> - </field> - <field> - <name>maxMemorySizeKB</name> - <description>The number of kilobytes a device can hold. 'Zero' + <name>byteAddrOffset</name> + <type>uint8_t</type> + </field> + <field> + <default>0x100</default> + <description>The number of kilobytes a device can hold. 'Zero' value possible for some devices.</description> - <type>uint64_t</type> - <default>0x100</default> - </field> - <field> - <name>chipCount</name> - <description>The number of chips making up an eeprom device. + <name>maxMemorySizeKB</name> + <type>uint64_t</type> + </field> + <field> + <default>0x04</default> + <description>The number of chips making up an eeprom device. </description> - <type>uint8_t</type> - <default>0x04</default> - </field> - <field> - <name>writePageSize</name> - <description>The maximum number of bytes that can be written to + <name>chipCount</name> + <type>uint8_t</type> + </field> + <field> + <default>0x0</default> + <description>The maximum number of bytes that can be written to a device at one time. 'Zero' value means no maximum value is expected or checked.</description> - <type>uint64_t</type> - <default>0x0</default> - </field> - <field> - <name>writeCycleTime</name> - <description>The amount of time in milliseconds a device requires + <name>writePageSize</name> + <type>uint64_t</type> + </field> + <field> + <default>0x0</default> + <description>The amount of time in milliseconds a device requires on the completion of a write command to update its internal memory.</description> - <type>uint64_t</type> - <default>0x0</default> - </field> + <name>writeCycleTime</name> + <type>uint64_t</type> + </field> </complexType> + <description>Information needed to address the EERPROM slaves</description> + <id>EEPROM_SBE_PRIMARY_INFO</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + </attribute> -<attribute> - <id>EEPROM_SBE_BACKUP_INFO</id> - <description>Information needed to address the EERPROM slaves</description> + <attribute> <complexType> - <description>Structure to define the addressing for an I2C + <description>Structure to define the addressing for an I2C slave device.</description> - <field> - <name>i2cMasterPath</name> - <description>Entity path to the chip that contains the I2C + <field> + <default>physical:sys-0</default> + <description>Entity path to the chip that contains the I2C master</description> - <type>EntityPath</type> - <default>physical:sys-0</default> - </field> - <field> - <name>port</name> - <description>Port from the I2C Master device. This is a 6-bit + <name>i2cMasterPath</name> + <type>EntityPath</type> + </field> + <field> + <default>0x80</default> + <description>Port from the I2C Master device. This is a 6-bit value.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>devAddr</name> - <description>Device address on the I2C bus. This is a 7-bit value, + <name>port</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>Device address on the I2C bus. This is a 7-bit value, but then shifted 1 bit left.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>engine</name> - <description>I2C master engine. This is a 2-bit + <name>devAddr</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>I2C master engine. This is a 2-bit value.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>byteAddrOffset</name> - <description>The number of bytes a device requires to set its + <name>engine</name> + <type>uint8_t</type> + </field> + <field> + <default>0x02</default> + <description>The number of bytes a device requires to set its internal address/offset.</description> - <type>uint8_t</type> - <default>0x02</default> - </field> - <field> - <name>maxMemorySizeKB</name> - <description>The number of kilobytes a device can hold. 'Zero' + <name>byteAddrOffset</name> + <type>uint8_t</type> + </field> + <field> + <default>0x100</default> + <description>The number of kilobytes a device can hold. 'Zero' value possible for some devices.</description> - <type>uint64_t</type> - <default>0x100</default> - </field> - <field> - <name>chipCount</name> - <description>The number of chips making up an eeprom device. + <name>maxMemorySizeKB</name> + <type>uint64_t</type> + </field> + <field> + <default>0x04</default> + <description>The number of chips making up an eeprom device. </description> - <type>uint8_t</type> - <default>0x04</default> - </field> - <field> - <name>writePageSize</name> - <description>The maximum number of bytes that can be written to + <name>chipCount</name> + <type>uint8_t</type> + </field> + <field> + <default>0x0</default> + <description>The maximum number of bytes that can be written to a device at one time. 'Zero' value means no maximum value is expected or checked.</description> - <type>uint64_t</type> - <default>0x0</default> - </field> - <field> - <name>writeCycleTime</name> - <description>The amount of time in milliseconds a device requires + <name>writePageSize</name> + <type>uint64_t</type> + </field> + <field> + <default>0x0</default> + <description>The amount of time in milliseconds a device requires on the completion of a write command to update its internal memory.</description> - <type>uint64_t</type> - <default>0x0</default> - </field> + <name>writeCycleTime</name> + <type>uint64_t</type> + </field> </complexType> + <description>Information needed to address the EERPROM slaves</description> + <id>EEPROM_SBE_BACKUP_INFO</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + </attribute> -<attribute> - <id>TEMP_SENSOR_I2C_CONFIG</id> - <description>Information needed to address an I2C slave device</description> + <attribute> <complexType> - <description>Structure to define the addressing for an I2C + <description>Structure to define the addressing for an I2C slave device.</description> - <field> - <name>i2cMasterPath</name> - <description>Entity path to the chip that contains the I2C + <field> + <default>physical:sys-0</default> + <description>Entity path to the chip that contains the I2C master</description> - <type>EntityPath</type> - <default>physical:sys-0</default> - </field> - <field> - <name>engine</name> - <description>I2C master engine. This is a 2-bit + <name>i2cMasterPath</name> + <type>EntityPath</type> + </field> + <field> + <default>0x80</default> + <description>I2C master engine. This is a 2-bit value.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>port</name> - <description>Port from the I2C Master device. This is a 6-bit + <name>engine</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>Port from the I2C Master device. This is a 6-bit value.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> - <field> - <name>devAddr</name> - <description>Device address on the I2C bus. This is a 7-bit value, + <name>port</name> + <type>uint8_t</type> + </field> + <field> + <default>0x80</default> + <description>Device address on the I2C bus. This is a 7-bit value, but then shifted 1 bit left.</description> - <type>uint8_t</type> - <default>0x80</default> - </field> + <name>devAddr</name> + <type>uint8_t</type> + </field> </complexType> + <description>Information needed to address an I2C slave device</description> + <id>TEMP_SENSOR_I2C_CONFIG</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + </attribute> -<attribute> - <id>TPM_INFO</id> - <description>Information needed to address the TPM slaves</description> + <attribute> <complexType> - <description>Structure to define the addressing for an I2C + <description>Structure to define the addressing for an I2C TPM.</description> - <field> - <name>tpmEnabled</name> - <description>Boolean indicating whether this TPM is available + <field> + <default>0x0</default> + <description>Boolean indicating whether this TPM is available in the system</description> - <type>uint8_t</type> - <default>0x0</default> - </field> - <field> - <name>i2cMasterPath</name> - <description>Entity path to the chip that contains the I2C + <name>tpmEnabled</name> + <type>uint8_t</type> + </field> + <field> + <default>physical:sys-0</default> + <description>Entity path to the chip that contains the I2C master</description> - <type>EntityPath</type> - <default>physical:sys-0</default> - </field> - <field> - <name>port</name> - <description>Port from the I2C Master device. This is a 6-bit + <name>i2cMasterPath</name> + <type>EntityPath</type> + </field> + <field> + <default>0x01</default> + <description>Port from the I2C Master device. This is a 6-bit value.</description> - <type>uint8_t</type> - <default>0x01</default> - </field> - <field> - <name>devAddrLocality0</name> - <description>Device address on the I2C bus for Locality 0. + <name>port</name> + <type>uint8_t</type> + </field> + <field> + <default>0xAE</default> + <description>Device address on the I2C bus for Locality 0. This is a 7-bit value, but then shifted 1 bit left.</description> - <type>uint8_t</type> - <default>0xAE</default> - </field> - <field> - <name>devAddrLocality1</name> - <description>Device address on the I2C bus for Locality 1. + <name>devAddrLocality0</name> + <type>uint8_t</type> + </field> + <field> + <default>0xA8</default> + <description>Device address on the I2C bus for Locality 1. This is a 7-bit value, but then shifted 1 bit left.</description> - <type>uint8_t</type> - <default>0xA8</default> - </field> - <field> - <name>devAddrLocality2</name> - <description>Device address on the I2C bus for Locality 2. + <name>devAddrLocality1</name> + <type>uint8_t</type> + </field> + <field> + <default>0xAA</default> + <description>Device address on the I2C bus for Locality 2. This is a 7-bit value, but then shifted 1 bit left.</description> - <type>uint8_t</type> - <default>0xAA</default> - </field> - <field> - <name>devAddrLocality3</name> - <description>Device address on the I2C bus for Locality 3. + <name>devAddrLocality2</name> + <type>uint8_t</type> + </field> + <field> + <default>0xA4</default> + <description>Device address on the I2C bus for Locality 3. This is a 7-bit value, but then shifted 1 bit left.</description> - <type>uint8_t</type> - <default>0xA4</default> - </field> - <field> - <name>devAddrLocality4</name> - <description>Device address on the I2C bus for Locality 4. + <name>devAddrLocality3</name> + <type>uint8_t</type> + </field> + <field> + <default>0xA6</default> + <description>Device address on the I2C bus for Locality 4. This is a 7-bit value, but then shifted 1 bit left.</description> - <type>uint8_t</type> - <default>0xA6</default> - </field> - <field> - <name>engine</name> - <description>I2C master engine. This is a 2-bit + <name>devAddrLocality4</name> + <type>uint8_t</type> + </field> + <field> + <default>0x00</default> + <description>I2C master engine. This is a 2-bit value.</description> - <type>uint8_t</type> - <default>0x00</default> - </field> - <field> - <name>byteAddrOffset</name> - <description>The number of bytes a device requires to set its + <name>engine</name> + <type>uint8_t</type> + </field> + <field> + <default>0x01</default> + <description>The number of bytes a device requires to set its internal address/offset.</description> - <type>uint8_t</type> - <default>0x01</default> - </field> + <name>byteAddrOffset</name> + <type>uint8_t</type> + </field> </complexType> + <description>Information needed to address the TPM slaves</description> + <id>TPM_INFO</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>EC</id> - <description>attribute indicating the chip target's EC level</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <readable></readable> + </attribute> -<attribute> - <id>HDAT_EC</id> + <attribute> <description> Indicates the chip's EC level, distinct from ATTR_EC to handle non-standard mini-ECs, e.g. 1.01, separate from the real hardware-defined EC level. By default, ATTR_HDAT_EC==ATTR_EC unless the chip has a mini-EC. </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>MINI_EC</id> - <description> - Specifies extra mini-EC versions beyond the standard Major.Minor - Ex. 1.04 -> ATTR_EC=0x10, ATTR_MINI_EC=4 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MINI_EC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CHIP_ID</id> - <description>attribute indicating the chip's ID</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CHIP_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FSI_GP_REG_SCOM_ACCESS</id> - <description>attribute indicating if the chip's FSI GP regs have scom access</description> - <simpleType><uint8_t></uint8_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_FSI_GP_REG_SCOM_ACCESS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L2_R_T0_EPS</id> - <description>L2 tier0 read epsilon register value.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L2_R_T0_EPS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L2_R_T1_EPS</id> - <description>L2 tier1 read epsilon register value.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L2_R_T1_EPS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L2_R_T2_EPS</id> - <description>L2 tier2 read epsilon register value.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L2_R_T2_EPS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L2_FORCE_R_T2_EPS</id> - <description>L2 force tier2 read epsilon protect (all tiers).</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L2_FORCE_R_T2_EPS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L2_W_EPS</id> - <description>L2 write epsilon register value.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L2_W_EPS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L3_R_T0_EPS</id> - <description>L3 tier0 read epsilon register value.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L3_R_T0_EPS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L3_R_T1_EPS</id> - <description>L3 tier1 read epsilon register value.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L3_R_T1_EPS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L3_R_T2_EPS</id> - <description>L3 tier2 read epsilon register value.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> + <id>HDAT_EC</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L3_R_T2_EPS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L3_FORCE_R_T2_EPS</id> - <description>L3 force tier2 read epsilon protect (all tiers).</description> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L3_FORCE_R_T2_EPS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>L3_W_EPS</id> - <description>L3 write epsilon register value.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> + <attribute> + <description>A unit (chiplet) 's offset number within the chip. </description> <hwpfToHbAttrMap> - <id>ATTR_L3_W_EPS</id> - <macro>DIRECT</macro> + <id>ATTR_CHIP_UNIT_POS</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> <id>CHIP_UNIT</id> - <description>A unit (chiplet) 's offset number within the chip. </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CHIP_UNIT_POS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>POSITION</id> - <description>Position of target relative to node</description> + <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> + </attribute> -<attribute> - <id>MBA_PORT</id> - <description>MBA port this DIMM is connected to</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <attribute> + <description>Position of target relative to node</description> + <id>POSITION</id> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MBA_PORT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <no_export/> -</attribute> - -<attribute> - <id>MBA_DIMM</id> - <description>MBA port DIMM number of this DIMM</description> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MBA_DIMM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <no_export/> -</attribute> + </attribute> -<attribute> - <id>CEN_DQ_TO_DIMM_CONN_DQ</id> + <attribute> <description> Centaur DQ to DIMM connector DQ mapping for a JEDEC DIMM. Uint8 value for each Centaur DQ (0-79). The value is the corresponding DIMM Connector DQ. </description> + <id>CEN_DQ_TO_DIMM_CONN_DQ</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - <!-- Default is 1:1 mapping, DQ0-DQ0, DQ1-DQ1 etc --> - <!-- Data will eventually come from MRW --> - <default> + <array>80</array> + <uint8_t> + <default> 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19, 20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39, 40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59, 60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79 </default> - </uint8_t> - <array>80</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<enumerationType> - <id>PROC_EPS_TABLE_TYPE</id> - <description>Enumeration indicating the PROC_EPS_TABLE_TYPE</description> - <enumerator> - <name>EPS_TYPE_LE</name> - <value>1</value> - </enumerator> - <enumerator> - <name>EPS_TYPE_HE</name> - <value>2</value> - </enumerator> -</enumerationType> - -<attribute> - <id>PROC_EPS_TABLE_TYPE</id> - <description> - System attribute. - Processor epsilon table type. Used to calculate the processor nest - epsilon register values. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_EPS_TABLE_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>PROC_FABRIC_PUMP_MODE</id> - <description>Enumeration indicating the PROC_FABRIC_PUMP_MODE</description> - <enumerator> - <name>MODE1</name> - <value>1</value> - </enumerator> - <enumerator> - <name>MODE2</name> - <value>2</value> - </enumerator> -</enumerationType> - -<attribute> - <id>PROC_FABRIC_PUMP_MODE</id> - <description> - System attribute. - Processor SMP Fabric broadcast scope configuration. - MODE1 = default = chip/group/system/remote group/foreign. - MODE2 = group/system/remote group/foreign. - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_PUMP_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>ALL_MCS_IN_INTERLEAVING_GROUP</id> - <description> - System attribute. - If all MCS chiplets are in an interleaving group (1=true, 0=false). - - If true the SMP fabric is setup in normal mode and multiple MCSs - are grouped (disallowing systems with memory only under 1 MCS - (i.e. systems with a single C-DIMM)) - - If false the SMP fabric is setup in checkerboard mode. - Provided by the Machine Readable Workbook. - This attribute is based on Machine-Type-Model (MTM) and is setup by - the service processor. - </description> - <simpleType> - <uint8_t> - <default>0x00</default> - </uint8_t> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_ALL_MCS_IN_INTERLEAVING_GROUP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>FABRIC_GROUP_ID</id> + <attribute> <description> Chip attribute. Logical fabric group the chip belongs to. Provided by the Machine Readable Workbook. Can vary across drawers. </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_GROUP_ID</id> - <macro>DIRECT</macro> + <id>ATTR_PROC_FABRIC_GROUP_ID</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> - <no_export/> -</attribute> - -<attribute> - <id>PROC_EFF_FABRIC_GROUP_ID</id> - <description> - Effective fabric group ID associated with this chip. - Directly drives programming of chip memory map layout. - Compared with ATTR_PROC_FABRIC_GROUP_ID to configure FBC XOR masking. - </description> + <id>FABRIC_GROUP_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_EFF_FABRIC_GROUP_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable></writeable> <no_export/> -</attribute> + </attribute> -<attribute> - <id>FABRIC_CHIP_ID</id> + <attribute> <description> Chip attribute. Logical fabric chip id for this chip (position within the fabric). Provided by the Machine Readable Workbook. Can vary across drawers. </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_CHIP_ID</id> - <macro>DIRECT</macro> + <id>ATTR_PROC_FABRIC_CHIP_ID</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> - <no_export/> -</attribute> - -<attribute> - <id>PROC_EFF_FABRIC_CHIP_ID</id> - <description> - Effective fabric chip ID associated with this chip. - Directly drives programming of chip memory map layout. - Compared with ATTR_PROC_FABRIC_CHIP_ID to configure FBC XOR masking. - </description> + <id>FABRIC_CHIP_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_EFF_FABRIC_CHIP_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable></writeable> <no_export/> -</attribute> - -<attribute> - <id>CHIP_HAS_SBE</id> - <description> - Chip attribute. - If true, the chip has an SBE and the associated registers. - Provided by the Machine Readable Workbook. - </description> - <simpleType><uint8_t></uint8_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CHIP_HAS_SBE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FREQ_PROC_REFCLOCK</id> - <description> - System attribute. - The frequency of the processor refclock in MHz. - Provided by the MRW. - </description> - <simpleType><uint32_t></uint32_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_PROC_REFCLOCK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FREQ_PROC_REFCLOCK_KHZ</id> - <description> - System attribute. - The frequency of the processor refclock in KHz. - Provided by the MRW. - </description> - <simpleType><uint32_t></uint32_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_PROC_REFCLOCK_KHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FREQ_MEM_REFCLOCK</id> - <description> - System attribute. - The frequency of the memory refclock in MHz. - Provided by the MRW. - </description> - <simpleType><uint32_t></uint32_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_MEM_REFCLOCK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>MIN_FREQ_MHZ</id> + <attribute> <description> System attribute. The lowest frequency that a core can be set to in MHz. @@ -2686,22 +1143,22 @@ Data is provided by MVPD #V and is calculated as the Maximum of the power save frequencies. </description> - <simpleType> - <uint32_t> - <default>4800</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> <hwpfToHbAttrMap> - <id>ATTR_FREQ_CORE_FLOOR_MHZ</id> - <macro>DIRECT</macro> + <id>ATTR_FREQ_CORE_FLOOR_MHZ</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> + <id>MIN_FREQ_MHZ</id> + <persistency>volatile</persistency> + <readable></readable> + <simpleType> + <uint32_t> + <default>4800</default> + </uint32_t> + </simpleType> + <writeable></writeable> + </attribute> -<attribute> - <id>DPO_MIN_FREQ_PERCENT</id> + <attribute> <description> Defines a negative percentage value that is applied to the ATTR_NOMINAL_FREQ_MHZ determined from MVPD #V. It @@ -2711,171 +1168,22 @@ Value must be between 0 and -100. A value of zero indicates no override. </description> + <id>DPO_MIN_FREQ_PERCENT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <int32_t> - <default>0</default> - </int32_t> - </simpleType> - <range> + <int32_t> + <default>0</default> + </int32_t> + <range> <min>-100</min> <max>0</max> - </range> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>FREQ_PB_MHZ</id> - <description> - System attribute. - The frequency of a processor's PB chiplet in MHz. - This is the same for all PB chiplets in the system. - Provided by the MRW. - </description> - <simpleType><uint32_t></uint32_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_PB_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FREQ_A_MHZ</id> - <description> - System attribute. - The frequency of a processor's A-bus chiplet in MHz. - This is the same for all A-bus chiplets in the system. - Provided by the MRW. - </description> - <simpleType><uint32_t> - <default>0x1900</default> - </uint32_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/><!-- Only because SBE needs it --> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_A_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FREQ_O_MHZ</id> - <description> - The frequency of a processor's Obus mesh clocks, in MHz. - Provided by the MRW. - </description> - <simpleType> - <uint32_t> - <default>1611</default> - </uint32_t> - <array>4</array> + </range> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/><!-- Only because SBE needs it --> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_O_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OB0_PLL_BUCKET</id> - <description> - Select OBUS0 pll setting from one of the supported frequencies - </description> - <simpleType> - <uint8_t><default>1</default></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/><!-- Only because SBE needs it --> - <hwpfToHbAttrMap> - <id>ATTR_OB0_PLL_BUCKET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OB1_PLL_BUCKET</id> - <description> - Select OBUS1 pll setting from one of the supported frequencies - </description> - <simpleType> - <uint8_t><default>1</default></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/><!-- Only because SBE needs it --> - <hwpfToHbAttrMap> - <id>ATTR_OB1_PLL_BUCKET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OB2_PLL_BUCKET</id> - <description> - Select OBUS2 pll setting from one of the supported frequencies - </description> - <simpleType> - <uint8_t><default>1</default></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/><!-- Only because SBE needs it --> - <hwpfToHbAttrMap> - <id>ATTR_OB2_PLL_BUCKET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OB3_PLL_BUCKET</id> - <description> - Select OBUS3 pll setting from one of the supported frequencies - </description> - <simpleType> - <uint8_t><default>1</default></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/><!-- Only because SBE needs it --> - <hwpfToHbAttrMap> - <id>ATTR_OB3_PLL_BUCKET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FREQ_X_MHZ</id> - <description> - System attribute. - The frequency of a processor's X-bus chiplet in MHz. - This is the same for all X-bus chiplets in the system. - Provided by the MRW. - </description> - <simpleType> - <uint32_t> - <default>2000</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_X_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>HUID</id> + <attribute> <description> Hardware Unit ID SSSSNNNNTTTTTTTTiiiiiiiiiiiiiiii @@ -2884,285 +1192,280 @@ T=Target Type (matches TYPE attribute) i=Instance/Sequence number of target, relative to node </description> + <id>HUID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t></uint32_t> - <default>0xFFFFFFFF</default> + <default>0xFFFFFFFF</default> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> -<attribute> - <id>SP_FUNCTIONS</id> - <description> - Attribute which describes what the SP is or is not doing in this system - </description> + </attribute> + + <attribute> <complexType> - <description>Structure which defines a system's SP functions. + <description>Structure which defines a system's SP functions. Applicable for System target only. Structure is read-only. </description> - <field> - <name>baseServices</name> - <description> + <field> + <bits>1</bits> + <default>1</default> + <description> If this flag is set then mailboxEnabled MUST also be set 0b0: SP does not support for VPD, payload, ATTR sync, VDDR, TOD; 0b1: SP supports VPD, payload, ATTR sync, VDDR, TOD </description> - <type>uint32_t</type> - <bits>1</bits> - <default>1</default> - </field> - <field> - <name>fsiSlaveInit</name> - <description> + <name>baseServices</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>1</default> + <description> 0b0: SP does not initialize FSI slave logic, Hostboot must; 0b1: SP does initialize FSI slave logic so Hostboot should not </description> - <type>uint32_t</type> - <bits>1</bits> - <default>1</default> - </field> - <field> - <name>mailboxEnabled</name> - <description> + <name>fsiSlaveInit</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description> 0b0: There is no SP mailbox support; 0b1: There is SP mailbox support </description> - <type>uint32_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>fsiMasterInit</name> - <description> + <name>mailboxEnabled</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>1</default> + <description> 0b0: SP does not initialize FSI master logic, Hostboot must; 0b1: SP does initialize FSI master logic so Hostboot should not </description> - <type>uint32_t</type> - <bits>1</bits> - <default>1</default> - </field> - <field> - <name>hardwareChangeDetection</name> - <description> + <name>fsiMasterInit</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>1</default> + <description> 0b0: SP does not perform hardware change detection, Hostboot must; 0b1: SP does perform hardware change detection (HCDB) so Hostboot should not </description> - <type>uint32_t</type> - <bits>1</bits> - <default>1</default> - </field> - <field> - <name>powerLineDisturbance</name> - <description> + <name>hardwareChangeDetection</name> + <type>uint32_t</type> + </field> + <field> + <bits>1</bits> + <default>1</default> + <description> 0b0: SP does not perform Power Line Disturbance (PLD) detection, Hostboot must; 0b1: SP does perform Power Line Disturbance (PLD) detection so Hostboot should not </description> - <type>uint32_t</type> - <bits>1</bits> - <default>1</default> - </field> - <field> - <name>reserved</name> - <description>Reserved for future use</description> - <type>uint32_t</type> - <bits>26</bits> - <default>0</default> - </field> - </complexType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>HB_SETTINGS</id> + <name>powerLineDisturbance</name> + <type>uint32_t</type> + </field> + <field> + <bits>26</bits> + <default>0</default> + <description>Reserved for future use</description> + <name>reserved</name> + <type>uint32_t</type> + </field> + </complexType> <description> - Attribute which describes how the SP has configured features in - Hostboot. + Attribute which describes what the SP is or is not doing in this system </description> + <id>SP_FUNCTIONS</id> + <persistency>non-volatile</persistency> + <readable></readable> + </attribute> + + <attribute> <complexType> - <description>Structure which defines a system's HB settings. + <description>Structure which defines a system's HB settings. Applicable for System target only. </description> - <field> - <name>traceContinuous</name> - <description> + <field> + <bits>1</bits> + <default>0</default> + <description> Enable / Disable continuous trace. 0b0: Continuous trace is disabled. 0b1: Continuous trace is enabled. </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>traceScanDebug</name> - <description> + <name>traceContinuous</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description> Override trace debug selection for SCAN component. 0b0: TRACS entries for SCAN have default behavior. 0b1: TRACS entries for SCAN are enabled. </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>traceFapiDebug</name> - <description> + <name>traceScanDebug</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description> Override trace debug selection for DBG component. 0b0: TRACS entries for DBG have default behavior. 0b1: TRACS entries for DBG are enabled. </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>reserved</name> - <description>Reserved for future use</description> - <type>uint8_t</type> - <bits>5</bits> - <default>0</default> - </field> - </complexType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>CEC_IPL_TYPE</id> + <name>traceFapiDebug</name> + <type>uint8_t</type> + </field> + <field> + <bits>5</bits> + <default>0</default> + <description>Reserved for future use</description> + <name>reserved</name> + <type>uint8_t</type> + </field> + </complexType> <description> - Attribute which describes optional IPL flavors + Attribute which describes how the SP has configured features in + Hostboot. </description> + <id>HB_SETTINGS</id> + <persistency>non-volatile</persistency> + <readable></readable> + <writeable></writeable> + </attribute> + + <attribute> <complexType> - <description>Structure which defines a they IPL types + <description>Structure which defines a they IPL types Applicable for System target only. </description> - <field> - <name>PostDump</name> - <description> + <field> + <bits>1</bits> + <default>0</default> + <description> Perform mainstore dump collection. Only valid for MPIPL 0b0: Do not collect mainstore dump 0b1: Perform mainstore dump collection </description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>MinorIPLType</name> - <description>Minor IPL Type</description> - <type>uint8_t</type> - <bits>7</bits> - <default>0</default> - </field> - </complexType> + <name>PostDump</name> + <type>uint8_t</type> + </field> + <field> + <bits>7</bits> + <default>0</default> + <description>Minor IPL Type</description> + <name>MinorIPLType</name> + <type>uint8_t</type> + </field> + </complexType> + <description> + Attribute which describes optional IPL flavors + </description> + <id>CEC_IPL_TYPE</id> <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> - - -<!-- Begin attributes (4) to test string support --> + <readable></readable> + <writeable></writeable> + </attribute> -<attribute> - <id>TEST_NULL_STRING</id> + <attribute> <description>Test attribute; string with empty default value</description> + <id>TEST_NULL_STRING</id> + <persistency>volatile</persistency> + <readable></readable> <simpleType> - <string> - <default></default> - <sizeInclNull>10</sizeInclNull> - </string> + <string> + <default></default> + <sizeInclNull>10</sizeInclNull> + </string> </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>TEST_MIN_STRING</id> + <attribute> <description>Test attribute; smallest string possible given size</description> + <id>TEST_MIN_STRING</id> + <persistency>volatile</persistency> + <readable></readable> <simpleType> - <string> - <default>a</default> - <sizeInclNull>10</sizeInclNull> - </string> + <string> + <default>a</default> + <sizeInclNull>10</sizeInclNull> + </string> </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>TEST_MAX_STRING</id> + <attribute> <description>Test attribute; largest string possible given size</description> + <id>TEST_MAX_STRING</id> + <persistency>volatile</persistency> + <readable></readable> <simpleType> - <string> - <default>abc</default> - <sizeInclNull>4</sizeInclNull> - </string> + <string> + <default>abc</default> + <sizeInclNull>4</sizeInclNull> + </string> </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>TEST_NO_DEFAULT_STRING</id> + <attribute> <description>Test attribute; string with no default supplied</description> + <id>TEST_NO_DEFAULT_STRING</id> + <persistency>volatile</persistency> + <readable></readable> <simpleType> - <string> - <sizeInclNull>10</sizeInclNull> - </string> + <string> + <sizeInclNull>10</sizeInclNull> + </string> </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<!-- End attributes (4) to test string support --> + <writeable></writeable> + </attribute> -<attribute> - <id>FAPI_NAME</id> + <attribute> <description>Common name across FAPI environments - chip target -> pu:k0:n0:s0:p00 - DIMM target -> dimm:k0:n0:s0:p00 - chip unit target -> pu.core:k0:n0:s0:p00:c0 - cage/system target -> k0 + chip target -> pu:k0:n0:s0:p00 + DIMM target -> dimm:k0:n0:s0:p00 + chip unit target -> pu.core:k0:n0:s0:p00:c0 + cage/system target -> k0 (chip type).(unit type):k(cage,always zero for us):n(node/drawer) :s(slot,always zero for us):p(chip position):c(core/unit position) pu = generic processor </description> + <id>FAPI_NAME</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <string> - <default>unknown</default> - <sizeInclNull>64</sizeInclNull> - </string> + <string> + <default>unknown</default> + <sizeInclNull>64</sizeInclNull> + </string> </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> - + </attribute> -<attribute> - <id>VPD_REC_NUM</id> + <attribute> <description>Record offset for this target's VPD</description> + <id>VPD_REC_NUM</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - <default>0xFFFF</default> - </uint16_t> + <uint16_t> + <default>0xFFFF</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> + </attribute> -<attribute> - <id>PEER_TARGET</id> + <attribute> <description>Peer target's address of a A/X-bus connection. NULL means address 0 for no peer target. If a target instance overrides the default with the @@ -3170,448 +1473,145 @@ convert the valid PHYS_PATH string into the runtime virtual address of the peer target instance. </description> + <id>PEER_TARGET</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <Target_t> - <default>NULL</default> - </Target_t> + <Target_t> + <default>NULL</default> + </Target_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>PAYLOAD_BASE</id> + <attribute> <description>Base address (target HRMOR) of the payload. Value is in MB.</description> + <id>PAYLOAD_BASE</id> + <persistency>volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <default>256</default> - </uint64_t> + <uint64_t> + <default>256</default> + </uint64_t> </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>PAYLOAD_ENTRY</id> + <attribute> <description>The offset from base address of the payload entry-point. Current default is 0x180</description> + <id>PAYLOAD_ENTRY</id> + <persistency>volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <default>0x180</default> - </uint64_t> + <uint64_t> + <default>0x180</default> + </uint64_t> </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<enumerationType> - <id>PAYLOAD_KIND</id> - <description> - Enumeration indicating what kind of payload is to be started - </description> - <enumerator> - <name>UNKNOWN</name> - <value>0</value> - </enumerator> - <enumerator> - <name>PHYP</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SAPPHIRE</name> - <value>2</value> - </enumerator> - <enumerator> - <name>NONE</name> - <value>3</value> - </enumerator> - <default>UNKNOWN</default> -</enumerationType> + <writeable></writeable> + </attribute> -<attribute> - <id>PAYLOAD_KIND</id> + <attribute> <description> Attribute indicating what kind of payload is to be started. </description> + <hasStringConversion></hasStringConversion> + <id>PAYLOAD_KIND</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <enumeration> - <id>PAYLOAD_KIND</id> - </enumeration> + <enumeration> + <id>PAYLOAD_KIND</id> + </enumeration> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hasStringConversion/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>HB_HRMOR_NODAL_BASE</id> + <attribute> <description>Hostboot HRMOR = (HB_HRMOR_NODAL_BASE * node) + offset. </description> - <!-- This value is set by the FSP. - Hostboot uses it to find the HRMOR of Hostboot images running on other nodes. - The value of HB_HRMOR_NODAL_BASE does NOT include the offset --> + <id>HB_HRMOR_NODAL_BASE</id> + <persistency>volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <default>0x200000000000</default> <!-- 32TB --> - </uint64_t> + <uint64_t> + <default>0x200000000000</default> + </uint64_t> </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>FABRIC_TO_PHYSICAL_NODE_MAP</id> + <attribute> <description> Correlate HDAT node number (physical) to the logical node (based on the PIR) that contains the host boot image. </description> - <!-- 8 byte array. The index is the physical node number. The value - at that index is the hb instance number, based on the processor PIR, that - contains or would contain the host boot image if the drawer exists or were - to exist. Host boot uses this value and HB_HRMOR_NODAL_BASE to calculate - the HRMOR of the hostboot image for each drawer. - If the drawer does NOT physically exist then enter a logical node that - does NOT physically exist. - - It's conceivable that there could be more than one logical node contained - in a physical drawer, if that is ever the case then the FSP would need to - modify this attribute to indicate which logical node contains the hostboot - image for each drawer. --> - <simpleType> - <uint8_t> - <!-- Default is for single node system --> - <default>0,255,255,255,255,255,255,255</default> - </uint8_t> - <array>8</array> - </simpleType> + <id>FABRIC_TO_PHYSICAL_NODE_MAP</id> <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<!-- TARGETING attributes to support mss_setup_bars and proc_setup_bars --> - -<attribute> - <id>PROC_MEM_BASES</id> - <description> - read/write HWP attribute mapped to TARGETING - Non-mirrored memory base addresses - creator: mss_setup_bars - consumer: proc_setup_bars, platform - firmware notes: - 64-bit RA - eight independent non-mirrored segments are supported - (max number based on Venice design) - </description> - <simpleType> - <uint64_t></uint64_t> - <array>8</array><!--per group--> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_MEM_BASES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_MEM_SIZES</id> - <description> - read/write HWP attribute mapped to TARGETING - Size of non-mirrored memory regions - creator: mss_setup_bars - consumer: proc_setup_bars, platform - firmware notes: - for given index value, address space assumed to be contiguous - from ATTR_PROC_MEM_BASES value at matching index - eight independent non-mirrored segments are supported - (max number based on Venice design) - </description> - <simpleType> - <uint64_t></uint64_t> - <array>8</array><!--per group--> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_MEM_SIZES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_MIRROR_BASES</id> - <description>Mirrored memory base addresses - creator: mss_setup_bars - consumer: proc_setup_bars, platform - firmware notes: - 64-bit RA - four independent mirrored segments are supported - (max number based on Venice design) - </description> - <simpleType> - <uint64_t></uint64_t> - <array>4</array><!--per group--> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_MIRROR_BASES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_MIRROR_SIZES</id> - <description>Size of mirrored memory region - creator: mss_setup_bars - consumer: proc_setup_bars, platform - firmware notes: - for given index value, address space assumed to be contiguous - from ATTR_PROC_MIRROR_BASES value at matching index - four independent mirrored segments are supported - (max number based on Venice design) - </description> - <simpleType> - <uint64_t></uint64_t> - <array>4</array><!--per group--> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_MIRROR_SIZES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_L3_BAR1_REG</id> - <description> - read/write HWP attribute mapped to TARGETING - L3 BAR1 register value - creator: proc_setup_bars - consumer: winkle image setup procedures - notes: - 64-bit register value - SCOM address: 0x1001080B - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_L3_BAR1_REG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_L3_BAR2_REG</id> - <description> - read/write HWP attribute mapped to TARGETING - L3 BAR2 register value - creator: proc_setup_bars - consumer: winkle image setup procedures - notes: - 64-bit register value - SCOM address: 0x10010813 - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_L3_BAR2_REG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_L3_BAR_GROUP_MASK_REG</id> - <description> - read/write HWP attribute mapped to TARGETING - L3 BAR Group Mask register value - creator: proc_setup_bars - consumer: winkle image setup procedures - notes: - 64-bit register value - SCOM address: 0x10010816 - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_L3_BAR_GROUP_MASK_REG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>FREQ_CORE</id> - <description> - firmware notes: - Nominal processor's core DPLL frequency (MHz). - Default value provided by Machine Readable Workbook. - This attribute is the current value. - @note this should be initialized by istep 7.1 proc_a_x_pci_dmi_pll_setup - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_CORE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_NOT_F_LINK</id> - <description> - firmware notes: - Set IPL time mux/switch between PCIE PHB/F link function - (one per foreign link) - </description> - <simpleType> + <readable></readable> + <simpleType> + <array>8</array> <uint8_t> - <default>1,1</default> + <default>0,255,255,255,255,255,255,255</default> </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_NOT_F_LINK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_MCS_GROUPS</id> - <description> - Per MCS group number - Value is index for PROC_MEM_BASES and PROC_MEM_SIZES arrays - creator: mss_eff_grouping.C - consumer: HDAT - </description> - <simpleType> - <uint8_t> - <default>0,0,0,0,0,0,0,0</default> - </uint8_t> - <array>8</array><!--per MCS--> </simpleType> - <persistency>volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_MCS_GROUPS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== - Memory Map - The attributes below are defined by the PHYP Memory Map - documentation owned by Shawn Lambeth - - @todo: RTC:44128 will be used to automatically create this data - ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== --> - -<!-- ===== System Attributes ===== --> + <writeable></writeable> + </attribute> -<attribute> - <id>XSCOM_BASE_ADDRESS</id> + <attribute> <description>System XSCOM base address</description> + <id>XSCOM_BASE_ADDRESS</id> + <persistency>non-volatile</persistency> + <readable></readable> + <writeable></writeable> <simpleType> - <uint64_t> - </uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>IBSCOM_MCS_BASE_ADDR</id> + <attribute> <description>MCS Inband Scom base address</description> - <simpleType> - <uint64_t> - <default>0x0003E00000000000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> <hwpfToHbAttrMap> - <id>ATTR_MCS_INBAND_BASE_ADDRESS</id> - <macro>DIRECT</macro> + <id>ATTR_MCS_INBAND_BASE_ADDRESS</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IBSCOM_PROC_BASE_ADDR</id> - <description>PROC Inband Scom base address</description> + <id>IBSCOM_MCS_BASE_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <default>0x0003E00000000000</default> - </uint64_t> + <uint64_t> + <default>0x0003E00000000000</default> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MIRROR_BASE_ADDRESS</id> - <description>System Mirrorable base address</description> + <attribute> + <description>PROC Inband Scom base address</description> + <id>IBSCOM_PROC_BASE_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <default>0x0000800000000000</default><!-- 128 TB --> - </uint64_t> + <uint64_t> + <default>0x0003E00000000000</default> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MIRROR_BASE_ADDRESS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>PAYLOAD_IN_MIRROR_MEM</id> + <attribute> <description>Indicate that payload should be placed in mirrored memory. Set by the FSP based on the value of the registry key indicating the memory mirroring mode. </description> + <id>PAYLOAD_IN_MIRROR_MEM</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> <!-- false --> - </uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<!-- ===== Processor Chip Attributes ===== --> + <writeable></writeable> + </attribute> -<attribute> - <id>NPU_MMIO_BAR_BASE_ADDR</id> + <attribute> <description>NPU MMIO BAR base address values creator: platform consumer: proc_setup_bars @@ -3621,51 +1621,22 @@ first dimension: unit number (0:3) second dimension: BAR number (0:1) </description> - <simpleType> - <uint64_t> - <default>0</default> - </uint64_t> - <array>4,2</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> <hwpfToHbAttrMap> - <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> + <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> + <id>NPU_MMIO_BAR_BASE_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> + <simpleType> + <array>4,2</array> + <uint64_t> + <default>0</default> + </uint64_t> + </simpleType> + </attribute> -<enumerationType> - <id>NPU_MMIO_BAR_SIZE</id> - <description>Enumeration indicating the BAR size - used with ATTR_PROC_NPU_MMIO_BAR_SIZE</description> - <enumerator> - <name>2_MB</name> - <value>0x0000000000200000</value> - </enumerator> - <enumerator> - <name>1_MB</name> - <value>0x0000000000100000</value> - </enumerator> - <enumerator> - <name>512_KB</name> - <value>0x0000000000080000</value> - </enumerator> - <enumerator> - <name>256_KB</name> - <value>0x0000000000040000</value> - </enumerator> - <enumerator> - <name>128_KB</name> - <value>0x0000000000020000</value> - </enumerator> - <enumerator> - <name>64_KB</name> - <value>0x0000000000010000</value> - </enumerator> -</enumerationType> -<attribute> - <id>NPU_MMIO_BAR_SIZE</id> + <attribute> <description>NPU MMIO BAR size values creator: platform consumer: proc_setup_bars @@ -3673,3640 +1644,495 @@ first dimension: unit number (0:3) second dimension: BAR number (0:1) </description> + <hwpfToHbAttrMap> + <id>ATTR_PROC_NPU_MMIO_BAR_SIZE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + <id>NPU_MMIO_BAR_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <default>0</default> - </uint64_t> - <array>4,2</array> + <array>4,2</array> + <uint64_t> + <default>0</default> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> + </attribute> + + <attribute> + <description>Base Address of FSP IO Region</description> <hwpfToHbAttrMap> - <id>ATTR_PROC_NPU_MMIO_BAR_SIZE</id> - <macro>DIRECT</macro> + <id>ATTR_PROC_FSP_BAR_BASE_ADDR</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> <id>FSP_BASE_ADDR</id> - <description>Base Address of FSP IO Region</description> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <!-- Starts at 1024TB - 128GB, 4GB per proc --> - <default>0x0003FFE000000000</default> - </uint64_t> + <uint64_t> + <default>0x0003FFE000000000</default> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FSP_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>FSP_BAR_SIZE</id> + <attribute> <description>Size of FSP IO Region</description> + <id>FSP_BAR_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <!-- 4GB per Proc --> - <default>0x0000000100000000</default> - </uint64_t> + <uint64_t> + <default>0x0000000100000000</default> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>PSI_BRIDGE_BASE_ADDR</id> + <attribute> <description>Base Address of PSI Bridge Logic</description> - <simpleType> - <uint64_t> - <!-- Starts at 1024TB - 6GB, 1MB per link --> - <!-- 0x0003FFFE80000000 + 0x100000*procnum --> - <default>0xFFFFFFFFFFFFFFFF</default> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> <hwpfToHbAttrMap> - <id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> + <id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> + <id>PSI_BRIDGE_BASE_ADDR</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> + <writeable></writeable> + <simpleType> + <uint64_t> + <default>0xFFFFFFFFFFFFFFFF</default> + </uint64_t> + </simpleType> + </attribute> -<attribute> - <id>INTP_BASE_ADDR</id> + <attribute> <description>Base Address of Interrupt Presenter</description> + <id>INTP_BASE_ADDR</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> + <writeable></writeable> <simpleType> - <uint64_t> - <!-- Starts at 1024TB - 2GB, 1MB per proc --> - <!-- 0x0003FFFF80000000 + 0x100000*procnum --> - <default>0xFFFFFFFFFFFFFFFF</default> - </uint64_t> + <uint64_t> + <default>0xFFFFFFFFFFFFFFFF</default> + </uint64_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>PHB_BASE_ADDRS</id> + <attribute> <description>Base Address of PHB Register Space</description> + <id>PHB_BASE_ADDRS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <!-- Starts at 1024TB - 7GB --> - <!-- 0x0003FFFE40000000 + 0x400000*procnum + 0x100000*phbnum --> - <default> + <array>4</array> + <uint64_t> + <default> 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF </default> - </uint64_t> - <array>4</array><!-- per PHB --> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>PCI_BASE_ADDRS_64</id> + <attribute> <description>Base Address of PCI 64 bit Memory Space</description> + <id>PCI_BASE_ADDRS_64</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - </uint64_t> - <array>4</array><!-- per PHB --> + <array>4</array> + <uint64_t></uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>PCI_BASE_ADDRS_32</id> + <attribute> <description>Base Address of PCI 32 bit Memory Space</description> + <id>PCI_BASE_ADDRS_32</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - </uint64_t> - <array>4</array><!-- per PHB --> + <array>4</array> + <uint64_t></uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - + </attribute> -<attribute> - <id>MEM_BASE</id> + <attribute> <description>Base Address for all mainstore behind this processor</description> + <hwpfToHbAttrMap> + <id>ATTR_PROC_MEM_BASE</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + <id>MEM_BASE</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint64_t> - </uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> + <writeable></writeable> + </attribute> + + <attribute> + <description>Base Address for all mirrored mainstore behind this processor</description> <hwpfToHbAttrMap> - <id>ATTR_PROC_MEM_BASE</id> - <macro>DIRECT</macro> + <id>ATTR_PROC_MIRROR_BASE</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> <id>MIRROR_BASE</id> - <description>Base Address for all mirrored mainstore behind this processor</description> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint64_t> - </uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> + <writeable></writeable> + </attribute> + + <attribute> + <description>Base Address of RNG IO Region</description> <hwpfToHbAttrMap> - <id>ATTR_PROC_MIRROR_BASE</id> - <macro>DIRECT</macro> + <id>ATTR_PROC_NX_MMIO_BAR_BASE_ADDR</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> <id>RNG_BASE_ADDR</id> - <description>Base Address of RNG IO Region</description> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <!-- Starts at 1024TB - 3GB --> - <!-- 0x0003FFFF40000000 + 0x1000*procnum --> - <default>0xFFFFFFFFFFFFFFFF</default> - </uint64_t> + <uint64_t> + <default>0xFFFFFFFFFFFFFFFF</default> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NX_MMIO_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>RNG_BAR_SIZE</id> + <attribute> <description>Size of RNG IO Region</description> + <id>RNG_BAR_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <!-- 4 KB per processor --> - <default>0x000000000001000</default> - </uint64_t> + <uint64_t> + <default>0x000000000001000</default> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>IMT_BASE_ADDR</id> + <attribute> <description>Base Address of In-Memory Trace Region Set by FSP-based tooling </description> + <id>IMT_BASE_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <default>0xFFFFFFFFFFFFFFFF</default> - </uint64_t> + <uint64_t> + <default>0xFFFFFFFFFFFFFFFF</default> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>IMT_BAR_SIZE</id> + <attribute> <description>Size of IMT IO Region Set by FSP-based tooling </description> + <id>IMT_BAR_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t> - <default>0x0000000000000000</default> - </uint64_t> + <uint64_t> + <default>0x0000000000000000</default> + </uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<!-- ===== ===== End Memory Map ===== ===== ===== ===== ===== ===== --> - -<attribute> - <id>PROC_EPS_GB_PERCENTAGE</id> - <description> - firmware notes: - Guardband percentage to apply to baseline epsilon values - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_EPS_GB_PERCENTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_EPS_GB_DIRECTION</id> - <description> - firmware notes: - Direction to apply guardband margin (positive/negative) - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_EPS_GB_DIRECTION</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_ASYNC_SAFE_MODE</id> - <description> - firmware notes: - Set to force all asynchronous boundary crossings into safe mode. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_ASYNC_SAFE_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FREQ_PCIE_MHZ</id> - <description> - The frequency of a processor's PCI-e bus in MHz. - This is the same for all PCI-e busses in the system. - Provided by the MRW. - </description> - <simpleType><uint32_t></uint32_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_PCIE_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>NOMINAL_FREQ_MHZ</id> + <attribute> <description> The nominal core frequency in MHz. This is the same for all cores in the system. Data is provided by MVPD #V. </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> <hwpfToHbAttrMap> - <id>ATTR_FREQ_CORE_NOMINAL_MHZ</id> - <macro>DIRECT</macro> + <id>ATTR_FREQ_CORE_NOMINAL_MHZ</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> + <id>NOMINAL_FREQ_MHZ</id> + <persistency>volatile</persistency> + <readable></readable> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <writeable></writeable> + </attribute> -<attribute> - <id>ULTRA_TURBO_FREQ_MHZ</id> + <attribute> <description> The ultra turbo frequency in MHz. This is the same for all cores in the system. Data is provided by MVPD #V and is calculated as the minimum of the ultra turbo frequencies. </description> - <simpleType><uint32_t></uint32_t></simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_ULTRA_TURBO_NOMINAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SOCKET_POWER_NOMINAL</id> - <description> - The socket power in nominal mode. - Controls how much power can be used. - This is the same for all cores in the system. - Data is provided by MVPD #V. - </description> - <simpleType><uint32_t></uint32_t></simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SOCKET_POWER_NOMINAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SOCKET_POWER_TURBO</id> - <description> - The socket power in turbo mode. - Controls how much power can be used. - This is the same for all cores in the system. - Data is provided by MVPD #V. - </description> - <simpleType><uint32_t></uint32_t></simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SOCKET_POWER_TURBO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MNFG_FLAGS</id> - <description> - Provides the manufacturing flags. This is a bitfield. - Multiple flags can be set at once. Use MNFG_FLAG_BIT - to decode. Expected use-case is for FSP to write this - attribute based on the MNFG component flags and for - HWSV/Hostboot to read it. - </description> - <simpleType> - <uint64_t> - <default>0x0000000000000000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MNFG_FLAGS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>MNFG_FLAG</id> - <description>Enumeration indicating the mnfg flags - that are set by the user. The values can be - combined using a bitwise 'OR'. The values will - need to be kept in sync with the FAPI - enumerator values. Also the enumeration type - is used by the ATTR_MNFG_FLAGS attribute. Should - note that the MNFG_FLAG values are of type uint32_t - </description> - <enumerator> - <!-- Use default mfg error thresholds and reporting values --> - <name>THRESHOLDS</name> - <value>0x00000001</value> - </enumerator> - <enumerator> - <!-- Enable AVP execution --> - <name>AVP_ENABLE</name> - <value>0x00000002</value> - </enumerator> - <enumerator> - <!-- Enable HDAT AVPs** --> - <name>HDAT_AVP_ENABLE</name> - <value>0x00000004</value> - </enumerator> - <enumerator> - <!-- All SRCs are terminating (CEC hardware/procedural) --> - <name>SRC_TERM</name> - <value>0x00000008</value> - </enumerator> - <enumerator> - <!-- Enable IPL memory diagnostics to report memory CE --> - <name>IPL_MEMORY_CE_CHECKING</name> - <value>0x00000010</value> - </enumerator> - <enumerator> - <!-- Enable Fast Background Scrub --> - <name>FAST_BACKGROUND_SCRUB</name> - <value>0x00000020</value> - </enumerator> - <enumerator> - <!-- Test DRAM Repairs --> - <name>TEST_DRAM_REPAIRS</name> - <value>0x00000040</value> - </enumerator> - <enumerator> - <!-- Disable Dram Repairs --> - <name>DISABLE_DRAM_REPAIRS</name> - <value>0x00000080</value> - </enumerator> - <enumerator> - <!-- Enable exhaustive pattern test --> - <name>ENABLE_EXHAUSTIVE_PATTERN_TEST</name> - <value>0x00000100</value> - </enumerator> - <enumerator> - <!-- Enable standard pattern test --> - <name>ENABLE_STANDARD_PATTERN_TEST</name> - <value>0x00000200</value> - </enumerator> - <enumerator> - <!-- Enable minimum pattern test --> - <name>ENABLE_MINIMUM_PATTERN_TEST</name> - <value>0x00000400</value> - </enumerator> - <enumerator> - <!-- Disable Fabric eRepair --> - <name>DISABLE_FABRIC_eREPAIR</name> - <value>0x00000800</value> - </enumerator> - <enumerator> - <!-- Disable Memory eRepair --> - <name>DISABLE_MEMORY_eREPAIR</name> - <value>0x00001000</value> - </enumerator> - <enumerator> - <!-- Fabric deploy lane spares --> - <name>FABRIC_DEPLOY_LANE_SPARES</name> - <value>0x00002000</value> - </enumerator> - <enumerator> - <!-- DMI deploy lane spares --> - <name>DMI_DEPLOY_LANE_SPARES</name> - <value>0x00004000</value> - </enumerator> - <enumerator> - <!-- Forcibly run PSI diagnostics --> - <name>PSI_DIAGNOSTIC</name> - <value>0x00008000</value> - </enumerator> - <enumerator> - <!-- Brazos Wrap Config --> - <name>BRAZOS_WRAP_CONFIG</name> - <value>0x00010000</value> - </enumerator> - <enumerator> - <!-- FSP is responsible for updating Processor SBE Image --> - <name>FSP_UPDATE_SBE_IMAGE</name> - <value>0x00020000</value> - </enumerator> - <enumerator> - <!-- Update both sides of SBE Image if update is needed --> - <name>UPDATE_BOTH_SIDES_OF_SBE</name> - <value>0x00040000</value> - </enumerator> -</enumerationType> - -<!-- Support for pm_hwp_attributes.xml --> - -<attribute> - <id>PROC_DPLL_DIVIDER</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_DPLL_DIVIDER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_POWER_PROXY_TRACE_TIMER</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_POWER_PROXY_TRACE_TIMER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PPT_TIMER_MATCH_VALUE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PPT_TIMER_MATCH_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PPT_TIMER_TICK</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PPT_TIMER_TICK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_AISS_TIMEOUT</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_AISS_TIMEOUT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PSTATE_STEPSIZE</id> - <description> - PROC_CHIP Attribute - -Used to setup the PMC voltage controller - -Producer: proc_build_pstate_tables.C - -Consumer: OCC pstate_init() - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PSTATE_STEPSIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_EXTERNAL_VRM_STEPDELAY_RANGE</id> - <description> - PROC_CHIP Attribute - -A 4 bit field selects one of the the upper 16bit of a 19bit counter (16+3) incremented in the nest/4 domain - -Consumer: proc_pm.scominit - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_EXTERNAL_VRM_STEPDELAY_VALUE</id> - <description> - PROC_CHIP Attribute - -Consumer: proc_pm.scominit - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PMC_HANGPULSE_DIVIDER</id> - <description> - PROC_CHIP Attribute - -Producer: proc_pm_init - -Consumer: proc_pm.scominit - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PMC_HANGPULSE_DIVIDER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PVSAFE_PSTATE</id> - <description> - PROC_CHIP Attribute -Pstate that is invoked in the PMC voltage controller upon the loss of the OCC Heartbeat.. - -Producer: proc_pm_init.C - -Consumer: proc_pm.scominit - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PVSAFE_PSTATE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_FRAME_SIZE</id> - <description> - PROC_CHIP Attribute - -Supported values: 0x20 (32d) - -Chip Select assertion duration is spi_frame_size + 2 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_FRAME_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_IN_DELAY_FRAME1</id> - <description> - PROC_CHIP Attribute - -Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_IN_DELAY_FRAME1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_IN_DELAY_FRAME2</id> - <description> - PROC_CHIP Attribute - -Supported values: 0x00 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_IN_DELAY_FRAME2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_CLOCK_POLARITY</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_CLOCK_POLARITY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_CLOCK_PHASE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_CLOCK_PHASE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_CLOCK_DIVIDER</id> - <description> - PROC_CHIP Attribute -For a 2.4GHz nest clock, this means that the SPI clk can be theoretically adjusted between 600MHz and 0.29MHz (cycle time 1.66ns...3.41us, in 1.66ns steps). However, a practical range is 0.5...25MHz. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_CLOCK_DIVIDER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS</id> - <description> - PROC_CHIP Attribute -Consumer: proc_pmc_init - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE</id> - <description> - PROC_CHIP Attribute - -Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time - -0x00000: Wait 1 SPI Clock -0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses - -For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_INTER_RETRY_DELAY_VALUE</id> - <description> - PROC_CHIP Attribute - -Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time - -0x0000: Wait 1 SPI Clock -0x0001 - 0xFFFF: value = number of ~100ns_hang_pulses - -For values greater than 0x00000, the actual delay is 1 SPI Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 SPI clock cycle. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_INTER_RETRY_DELAY</id> - <description> - PROC_CHIP Attribute -Consumer: proc_pmc_init - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_INTER_RETRY_DELAY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_CRC_GEN_ENABLE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_CRC_GEN_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_CRC_CHECK_ENABLE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_CRC_CHECK_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_MAJORITY_VOTE_ENABLE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_MAX_RETRIES</id> - <description> - PROC_CHIP Attribute - -0x00: No retry -0x01 to 0x1F: 1 to 31 respectively - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_MAX_RETRIES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_CRC_POLYNOMIAL_ENABLES</id> - <description> - PROC_CHIP Attribute - -An 8 bit mask vector to enable XORs in the CRC generation and checking LFSRs at the respective bit position. MSB (x^8) is omitted since it is always enabled, so the mask layout is (x^7,x^6,x^5,x^4,x^3,x^2,x^1,1) - -Planned CRC8 polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 -Value to enable planned polynomial: 0b1101_0101 (=0xD5) - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_OCC_HEARTBEAT_TIME</id> - <description> - PROC_CHIP Attribute -Consumer: OCC FW - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_OCC_HEARTBEAT_TIME</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SLEEP_WINKLE_REQUEST_TIMEOUT</id> - <description> - PROC_CHIP Attribute - -Consumer: proc_pmc_init.C. Will be translated to a DYNAMIC ATTRIBUTE for use by proc_pm..scominit as a multiple of PM hang pulses.. Counter starts at 0, is increased with every tp_pmc_hang_pulse as long as PORE is busy and set the PMC local FIR bit 19 when count = threshold. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SLEEP_WINKLE_REQUEST_TIMEOUT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SLEEP_ENTRY</id> - <description> - PROC_CHIP Attribute - -Set Assisted if power off serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency - -Producer: MRWB - -Consumer: proc_pm_init and proc_pcbs_init - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SLEEP_ENTRY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SLEEP_EXIT</id> - <description> - PROC_CHIP Attribute - -Set to Assisted if power on serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency -Must be set to Assisted if ATTR_PM_SLEEP_TYPE=Deep as this necessary for restore. - -Setting to Hardware is a test mode for Fast only. - -Producer: MRWB - -Consumer: proc_pm_init and proc_pcbs_init. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SLEEP_EXIT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SLEEP_TYPE</id> - <description> - PROC_CHIP Attribute -Selects which voltage level to place the Core domain PFETs upon Sleep entry. 0 = Vret (Fast Sleep Mode), 1 = Voff (Deep Sleep Mode) - -Producer: MRWB - -Consumer: proc_pm_init and proc_pcbs_init - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SLEEP_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_WINKLE_TYPE</id> - <description> - PROC_CHIP Attribute -Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode) - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_WINKLE_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERUP_CORE_DELAY0</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERUP_CORE_DELAY1</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERUP_CORE_DELAY0_VALUE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERUP_CORE_DELAY1_VALUE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</id> - <description> - PROC_CHIP Attribute - -0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0; - -1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1 - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERDOWN_CORE_DELAY0</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERDOWN_CORE_DELAY1</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERDOWN_CORE_DELAY0_VALUE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERDOWN_CORE_DELAY1_VALUE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</id> - <description> - PROC_CHIP Attribute - -0 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY0; - -1 in the bit position: use ATTR_PM_PFET_POWERUP_CORE_DELAY1 - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERUP_ECO_DELAY0</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERUP_ECO_DELAY1</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERUP_ECO_DELAY0_VALUE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERUP_ECO_DELAY1_VALUE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</id> - <description> - PROC_CHIP Attribute - -0 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY0; - -1 in the bit position: use ATTR_PM_PFET_POWERUP_ECO_DELAY1 - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERDOWN_ECO_DELAY0</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERDOWN_ECO_DELAY1</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERDOWN_ECO_DELAY0_VALUE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERDOWN_ECO_DELAY1_VALUE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PSTATE0_FREQUENCY</id> - <description> - PROC_CHIP Attribute - -Producer: proc_build_gpstate.C - -Consumers: proc_pcbs_init.C, proc_pcbs_lpst_init.C, - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PSTATE0_FREQUENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_IVRMS_ENABLED</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_IVRMS_ENABLED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SAFE_PSTATE</id> - <description> - PROC_CHIP Attribute - -Valid Values:-128 thru 127 - -Producer: proc_pm_init.C - -DYNAMIC_ATTRIBUTE - -Consumer: proc_pcbs_init.C - -Establishes the Pstate that the core chiplet will take on if: -psafe less-than-or-equal PMSR[global_actual_pstate] -AND any of the following conditions are true: -Loss of OCC Heartbeat if occ_heartbeat_en is set -PMGP0[force_safe_mode] is set - -If psafe greater-than PMSR[global_actual_pstate], the global_actual_pstate is forced. - -The value of Psafe needs to be at or below the nominal Pstate to make sure safe operation of all chiplets. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SAFE_PSTATE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NEST_LEAKAGE_PERCENT</id> - <description> - SYSTEM Attribute - Nest leakage percentage used to calculate the Core leakage. Will - eventually be read into OCC Pstate Parameter Block so the OCC can - see it for it's calculations. - - Valid Values: 0% thru 100% - Producer: Machine Readable Workbook - Consumer: OCC Firmware - </description> - <simpleType> - <uint8_t> - <default>60</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_NEST_LEAKAGE_PERCENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_ENABLE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_FULL_CSB_PSTATE</id> - <description> - PROC_CHIP Attribute -Defines the Pstate for the point at which clock sector buffers should be at full strength. This is to support Vmin operation. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_FULL_CSB_PSTATE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_LFRLOW_PSTATE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_LFRLOW_PSTATE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_LFRUPPER_PSTATE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_LFRUPPER_PSTATE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_HFRLOW_PSTATE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_HFRLOW_PSTATE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_HFRHIGH_PSTATE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_HFRHIGH_PSTATE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIPSS_FRAME_SIZE</id> - <description> - PROC_CHIP Attribute - -Supported values: 0x10 (16d), - -Chip Select assertion duration is spi_frame_size + 2 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIPSS_FRAME_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIPSS_OUT_COUNT</id> - <description> - PROC_CHIP Attribute - -Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size are ignored. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIPSS_OUT_COUNT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIPSS_IN_DELAY</id> - <description> - PROC_CHIP Attribute - -Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size result in the input never being captured - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIPSS_IN_DELAY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIPSS_IN_COUNT</id> - <description> - PROC_CHIP Attribute - -Supported values: 0x000 to spi_frame_size. The actual number of bits captured is spi_frame_size - spi_in_delay - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIPSS_IN_COUNT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIPSS_CLOCK_POLARITY</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIPSS_CLOCK_POLARITY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIPSS_CLOCK_PHASE</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIPSS_CLOCK_PHASE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIPSS_CLOCK_DIVIDER</id> - <description> - PROC_CHIP Attribute - </description> - <simpleType> - <uint16_t></uint16_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIPSS_CLOCK_DIVIDER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id> - <description> - PROC_CHIP Attribute - Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time - 0x00000: Wait 1 PSS Clock - 0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses - For values greater than 0x00000, the actual delay is 1 PSS Clock + the - time delay designated by the value defined. Max. delay at - 0x1FFFF: 13.1ms + 1 PSSI clock cycle. - Producer: proc_pm_init - Consumer: proc_pss_init - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PSTATES_ENABLED</id> - <description> - Indicator that all relevant attributes and required data for - Pstates to be enabled is present and valid - FALSE=0, TRUE=1 - Producer: p9_build_pstate_datablock - Consumers: p9_pm_pstate_gpe_init - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PSTATES_ENABLED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>RESCLK_ENABLED</id> - <description> - Indicator that all relevant attributes and required data for - Resonant Clocking to be enabled is present and valid - FALSE=0, TRUE=1 - Producer: p9_build_pstate_datablock - Consumers: p9_hcode_image_build -> - PGPE Header - CME Header - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_RESCLK_ENABLED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VDM_ENABLED</id> - <description> - Voltage Droop Monitors (VDM) to be enabled is present and valid - FALSE=0, TRUE=1 - Producer: p9_build_pstate_datablock - Consumers: p9_hcode_image_build -> - SGPE Header - CME Header - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_ENABLED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IVRM_ENABLED</id> - <description> - Indicator that all relevant attributes and required data for - Internal Voltage Regulator Macros (IVRMs) to be enabled is present and valid - FALSE=0, TRUE=1 - Producer: p9_build_pstate_datablock - Consumers: p9_hcode_image_build -> - PGPE Header - CME Header - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_IVRM_ENABLED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>WOF_ENABLED</id> - <description> - Indicator that all relevent attributes and required data for - WOF to be enabled is present and valid - FALSE=0, TRUE=1 - Producer: p9_build_pstate_datablock - Consumers: p9_hcode_image_build -> - PGPE Header - CME Header - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> <hwpfToHbAttrMap> - <id>ATTR_WOF_ENABLED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIPSS_INTER_FRAME_DELAY</id> - <description> - PROC_CHIP Attribute - -Consumer: proc_pm_init - -Produces ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIPSS_INTER_FRAME_DELAY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PBAX_RCV_RESERV_TIMEOUT</id> - <description> - PROC_CHIP Attribute -Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received under the following conditions: - Data Hi packet accepted and timeout waiting for Data Lo packet. - Reservation aquired and timeout waiting for Data Hi packet. - -00000 Data Timeout is Disabled -00001 divided hang pulse = PBAX hang pulse -00010 divided hang pulse = PBAX hang pulse/2 -00011 divided hang pulse = PBAX hang pulse/3 -. . . -11111 divided hang pulse = PBAX hang pulse/31 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PBAX_RCV_RESERV_TIMEOUT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE</id> - <description> - PROC_CHIP Attribute -Mode bit to count overcommit retries for the send retry threshold when sending PBAX commands on the powerbus. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PBAX_SND_RETRY_THRESHOLD</id> - <description> - PROC_CHIP Attribute -Defines the maximum number of retry attempts by the Send Engine for any phase of the PBAX transaction set before the operation is dropped and status bit are set. This does not count PowerBus overcommit retries unless snd_retry_count_overcom bit is set. - -0x00 : No Timeout -0x01 : 1 attempt -0x02 : 2 attempts -.etc. -0xFF : 255 attempts - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PBAX_SND_RETRY_THRESHOLD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PBAX_SND_RESERV_TIMEOUT</id> - <description> - PROC_CHIP Attribute -Divider for the 1us PBAX hang pulse. A hang is detected after two divided hang pulses are received after attempting to acquire a reservation with the PBAX Receive engine before declaring a Send Reservation Timeout error. - -00000 Send Reservation Timeout is Disabled -00001 divided hang pulse = PBAX hang pulse -00010 divided hang pulse = PBAX hang pulse/2 -00011 divided hang pulse = PBAX hang pulse/3 -. . . -11111 divided hang pulse = PBAX hang pulse/31 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PBAX_SND_RESERV_TIMEOUT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPWUP_FSP</id> - <description> - EX_CHIPLET Attribute - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPWUP_FSP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPWUP_OCC</id> - <description> - EX_CHIPLET Attribute - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPWUP_OCC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPWUP_PHYP</id> - <description> - EX_CHIPLET Attribute - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPWUP_PHYP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SLW_CONTROL_VECTOR_OFFSET</id> - <description> - Stores the offset in SLW image of this control vector for later use by scripts to control error injection. - This value is added to the contents of PBABAR2 for given chip to calculated the memory address for this vector per chip. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SLW_CONTROL_VECTOR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- End pm_hwp_attributes.xml --> - - -<!-- Support for pm_plat_attributes.xml --> - -<attribute> - <id>EXTERNAL_VRM_STEPSIZE</id> - <description> - SYSTEM Attribute - Step size (binary in microvolts) to take upon external VRM voltage - transitions. The value set here must take into account where internal - VRMs are enabled or not as, when they are enabled, the step size must - account for the tracking (eg PFET strength recalculation) for the step. - - Consumer: proc_build_pstate_tables.C, proc_pmc_init.C -config - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EXTERNAL_VRM_STEPSIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<attribute> - <id>EXTERNAL_VRM_TRANSITION_START_NS</id> - <description> - Delay (binary in nanoseconds) from the time the VRM receives the write - voltage command until the voltage actually moves. This value is used for - both increasing and decreasing transitions as part of the overall voltage - transition time calculation. - Firmware provides a default value of 8000ns (eg 8us)) if this attribute is - zero. Note: the smallest possible delay is limited to 1ns. - - Consumer: p9_pstate_parameter_block -> - Pstate Parameter Block (PSPB) for PGPE - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EXTERNAL_VRM_TRANSITION_START_NS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>EXTERNAL_VRM_TRANSITION_RATE_INC_UV_PER_US</id> - <description> - Transition rate (binary in microVolts per microsecond) of the VRM for an - increasing voltage transition. This is used as part of the overall voltage - transition time calculation - Firmware provides a default value of 10000 uV/us (eg 10mV/us) if this - attribute is zero. Note: the fastest possible rate is limited to 1uV/us. - - Consumer: p9_pstate_parameter_block -> - Pstate Parameter Block (PSPB) for PGPE - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EXTERNAL_VRM_TRANSITION_RATE_INC_UV_PER_US</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EXTERNAL_VRM_TRANSITION_RATE_DEC_UV_PER_US</id> - <description> - Transition rate (binary in microVolts per microsecond) of the VRM for an - decreasing voltage transition. This is used as part of the overall voltage - transition time calculation - Firmware provides a default value of 10000 uV/us (eg 10mV/us) if this - attribute is zero. Note: the fastest possible rate is limited to 1uV/us. - - Consumer: p9_pstate_parameter_block -> - Pstate Parameter Block (PSPB) for PGPE - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EXTERNAL_VRM_TRANSITION_RATE_DEC_UV_PER_US</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EXTERNAL_VRM_TRANSITION_STABILIZATION_TIME_NS</id> - <description> - Time (binary in nanoseconds) to allow the voltage rail to stabilize before - considering the transition to be fully complete. This value is used for - both increasing and decreasing transitions as part of the overall voltage - transition time calculation. - Firmware provides a default value of 5000ns (5us) if this attribute is zero. - Note: the smallest delay is limited to 1ns. - - Consumer: p9_pstate_parameter_block -> - Pstate Parameter Block (PSPB) for PGPE - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EXTERNAL_VRM_TRANSITION_STABILIZATION_TIME_NS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>EXTERNAL_VRM_STEPDELAY</id> - <description> - SYSTEM Attribute - Step delay (binary in microseconds) after a voltage change - - Consumer: proc_pmc_init -config - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EXTERNAL_VRM_STEPDELAY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_FREQUENCY</id> - <description> - SYSTEM Attribute - SPI Clock Frequency (binary in MHz) - - Consumer: proc_pm_effective - - Produces ATTR_PM_SPIVID_CLOCK_DIVIDER - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_FREQUENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPIVID_PORT_ENABLE</id> - <description> - PROC_CHIP Attribute - Defines the configuration of the SPIVID ports from the target. - - NONE means that no VRM is attached. - - PORTxNONRED means that the indicated port is used in a non-redundant - configuration. - - REDUNDANT means that all three are connected and considered redundant. - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPIVID_PORT_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SAFE_FREQUENCY</id> - <description> - Frequency (binary in KHz) indicating the frequency that the cores will be moved - to in the event of the loss of the OCC Heartbeat. This value needs to be the maximum - of the DpoMin frequency for proper PowerBus operation and the PowerSave value for - the present part. - - Provided by the Machine Readable Workbook after system characterization. - - The value is translated to the Pstate space. - - Producer: Machine Readable Workbook - - Consumers: p8_build_gpstate_table.C - - DYNAMIC_ATTRIBUTE: ATTR_PM_SAFE_PSTATE - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SAFE_FREQUENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> - <description> - SYSTEM Attribute - Frequency (binary in MHz) for the point at which clock sector buffers - should be at full strength. This is to support Vmin operation. - Setting cannot overlap the Low or High bands. - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> - <description> - SYSTEM Attribute - Frequency (binary in MHz)) for the lower end of the Low Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> - <description> - SYSTEM Attribute - Frequency (binary in MHz) for the upper end of the Low Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> - <description> - SYSTEM Attribute - Frequency (binary in MHz) for the lower end of the High Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> - <description> - SYSTEM Attribute - Frequency (binary in MHz)) for the upper end of the High Frequency - Resonant band - - Provided by the Machine Readable Workbook after system characterization. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PBAX_NODEID</id> - <description> - DEPRECATED!!! Use PBAX_GROUPID instead - PROC_CHIP Attribute - Receive PBAX Nodeid. Value that indicates this PBA's PBAX Node affinity. - This is matched to pbax_nodeid of the PMISC Address phase. - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PBAX_NODEID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PBAX_GROUPID</id> - <description> - PROC_CHIP Attribute - Receive PBAX Nodeid. Value that indicates this PBA's PBAX Node affinity. - This is matched to pbax_nodeid of the PMISC Address phase. - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PBAX_GROUPID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PBAX_CHIPID</id> - <description> - PROC_CHIP Attribute - Receive PBAX Chipid. Value that indicates this PBA's PBAX Chipid within - the PBAX node. Is matched to pbax_chipid of the Address phase if - pbax_type=unicast. - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PBAX_CHIPID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PBAX_BRDCST_ID_VECTOR</id> - <description> - PROC_CHIP Attribute - Receive PBAX Broadcast Group. Vector that is indexed when decoded PMISC - pbax_type=broadcast with the decoded PMISC pbax_chipid value. If the - bit in this vector at the decoded bit location is a 1, then this receive - engine will participate in the broadcast operation. - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PBAX_BRDCST_ID_VECTOR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FREQ_CORE_MAX</id> - <description> - SYSTEM Attribute - Maximum frequency (binary in MHz) that any processor in the system will - run. Used to define the top end of the PState range in the frequency space. - From this, the ATTR_PROCPM_PSTATE0_FREQUENCY is computed using - ATTR_SYSTEM_REFCLK_FREQUENCY to determine the step size. - - Consumers: proc_build_gpstate_table.C (among others) - - Data is is provided by MVPD #V and is calculated as the minimum - of the turbo frequencies - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_CORE_MAX</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- End pm_plat_attributes.xml --> - -<attribute> - <id>OVERRIDE_MVPD_NOM_FREQ_MHZ</id> - <description>Module VPD #V keyword Nominal Frequency in MHZ -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_NOM_FREQ_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_V_NEST_NOM_VOLTAGE</id> - <description>Module VPD #V keyword V-nest nominal voltage -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_V_NEST_NOM_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_I_NEST_NOM_CURRENT</id> - <description>Module VPD #V keyword I-nest nominal current -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure</description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_I_NEST_NOM_CURRENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_V_CS_NOM_VOLTAGE</id> - <description> - Module VPD #V keyword V-cs nominal voltage -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_V_CS_NOM_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_I_CS_NOM_CURRENT</id> - <description> - Module VPD #V keyword I-cs nominal current -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_I_CS_NOM_CURRENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_PS_FREQ_MHZ</id> - <description> - Module VPD #V keyword PowerSave Frequency in MHZ -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_PS_FREQ_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_V_NEST_PS_VOLTAGE</id> - <description> - Module VPD #V keyword V-nest powersave voltage -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_V_NEST_PS_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_I_NEST_PS_CURRENT</id> - <description> - Module VPD #V keyword I-nest powersave current -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_I_NEST_PS_CURRENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_V_CS_PS_VOLTAGE</id> - <description> - Module VPD #V keyword V-cs powersave voltage -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_V_CS_PS_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_I_CS_PS_CURRENT</id> - <description> - Module VPD #V keyword I-cs powersave current -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_I_CS_PS_CURRENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_TURBO_FREQ_MHZ</id> - <description> - Module VPD #V keyword turbo frequency in MHZ -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_TURBO_FREQ_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_V_NEST_TURBO_VOLTAGE</id> - <description> - Module VPD #V keyword V-nest turbo voltage -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_V_NEST_TURBO_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_I_NEST_TURBO_CURRENT</id> - <description> - Module VPD #V keyword I-nest turbo current -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_I_NEST_TURBO_CURRENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_V_CS_TURBO_VOLTAGE</id> - <description> - Module VPD #V keyword V-cs turbo voltage -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_V_CS_TURBO_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_I_CS_TURBO_CURRENT</id> - <description> - Module VPD #V keyword I-cs turbo current -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_I_CS_TURBO_CURRENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>OVERRIDE_MVPD_FVMIN_FREQ_MHZ</id> - <description> - Module VPD #V keyword fvmin frequency MHZ -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_FVMIN_FREQ_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_V_NEST_FVMIN_VOLTAGE</id> - <description> - Module VPD #V keyword V-nest fvmin voltage -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_V_NEST_FVMIN_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_I_NEST_FVMIN_CURRENT</id> - <description> - Module VPD #V keyword I-nest fvmin current -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_I_NEST_FVMIN_CURRENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_V_CS_FVMIN_VOLTAGE</id> - <description> - Module VPD #V keyword V-cs fvmin voltage -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_V_CS_FVMIN_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_I_CS_FVMIN_CURRENT</id> - <description> - Module VPD #V keyword I-cs fvmin current -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_I_CS_FVMIN_CURRENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_LAB_FREQ_MHZ</id> - <description> - Module VPD #V keyword lab frequency MHZ -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_LAB_FREQ_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_V_NEST_LAB_VOLTAGE</id> - <description> - Module VPD #V keyword V-nest lab voltage -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_V_NEST_LAB_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_I_NEST_LAB_CURRENT</id> - <description> - Module VPD #V keyword I-nest lab current -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_I_NEST_LAB_CURRENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_V_CS_LAB_VOLTAGE</id> - <description> - Module VPD #V keyword V-cs lab voltage -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_V_CS_LAB_VOLTAGE</id> - <macro>DIRECT</macro> + <id>ATTR_ULTRA_TURBO_NOMINAL</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OVERRIDE_MVPD_I_CS_LAB_CURRENT</id> - <description> - Module VPD #V keyword I-cs lab current -consumer: p8_build_pstate_datablock, others -firmware notes: Used as override attribute for pstate procedure - </description> + <id>ULTRA_TURBO_FREQ_MHZ</id> + <persistency>volatile</persistency> + <readable></readable> <simpleType> - <uint32_t></uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OVERRIDE_MVPD_I_CS_LAB_CURRENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_CONFIG</id> - <description>PCIE IOP lane configuration - creator: platform - consumer: proc_pcie_scominit - firmware notes: - Encoded PCIE IOP lane configuration - </description> - <simpleType><uint8_t></uint8_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_CONFIG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_PHB_ACTIVE</id> - <description>PCIE PHB valid mask - creator: platform - consumer: proc_pcie_scominit - firmware notes: - Bit mask defining set of active/valid PHBs - bit0=PHB0, bit1=PHB1, bit2=PHB2, bit3=PHB3 - </description> - <simpleType><uint8_t></uint8_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PHB_ACTIVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>AVDD_ID</id> + <attribute> <description> Memory AVDD voltage domain ID. All memory buffers in the same AVDD voltage domain will share the same ID. IDs are arbitrarily assigned, used for correlation between HB + HWSV, and are generated by genHwsvMrwXml.pl </description> + <id>AVDD_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>VDD_ID</id> + <attribute> <description> Memory VDD voltage domain ID. All memory buffers in the same VDD voltage domain will share the same ID. IDs are arbitrarily assigned, used for correlation between HB + HWSV, and are generated by genHwsvMrwXml.pl </description> + <id>VDD_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>VCS_ID</id> + <attribute> <description> Memory VCS voltage domain ID. All memory buffers in the same VCS voltage domain will share the same ID. IDs are arbitrarily assigned, used for correlation between HB + HWSV, and are generated by genHwsvMrwXml.pl </description> + <id>VCS_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>VPP_ID</id> + <attribute> <description> Memory VPP voltage domain ID. All memory buffers in the same VPP voltage domain will share the same ID. IDs are arbitrarily assigned, used for correlation between HB + HWSV, and are generated by genHwsvMrwXml.pl </description> + <id>VPP_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>VDDR_ID</id> + <attribute> <description>Voltage Memory Rail Manager ID. Currently HB only needs to configured the Vddr voltage rail manager during the IPL. The ID is an arbitary value and needed as correlation token between HB and HWSV. It will be generated by the genHwsvMrwXml.pl. </description> + <id>VDDR_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> - + </attribute> -<attribute> - <id>NEST_VDDR_ID</id> + <attribute> <description> Nest VDDR Voltage Rail ID. The ID is an arbitrary value and is needed as correlation token between HB and HWSV. It will be generated by the genHwsvMrwXml.pl </description> + <id>NEST_VDDR_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>NEST_VIO_ID</id> + <attribute> <description> Nest VIO Voltage Rail ID. The ID is an arbitrary value and is needed as correlation token between HB and HWSV. It will be generated by the genHwsvMrwXml.pl </description> + <id>NEST_VIO_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>NEST_VDD_ID</id> + <attribute> <description> Nest VDD Voltage Rail ID. The ID is an arbitrary value and is needed as correlation token between HB and HWSV. It will be generated by the genHwsvMrwXml.pl </description> + <id>NEST_VDD_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>NEST_VDN_ID</id> + <attribute> <description> Nest VDN Voltage Rail ID. The ID is an arbitrary value and is needed as correlation token between HB and HWSV. It will be generated by the genHwsvMrwXml.pl </description> + <id>NEST_VDN_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>NEST_VCS_ID</id> + <attribute> <description> Nest VCS Voltage Rail ID. The ID is an arbitrary value and is needed as correlation token between HB and HWSV. It will be generated by the genHwsvMrwXml.pl </description> - <simpleType> - <uint16_t> - <default>0</default> - </uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<!-- Add attributes for sbe_config_update --> -<attribute> - <id>ASYNC_NEST_FREQ_MHZ</id> - <description> - The asynchronous nest frequency - </description> - <simpleType> - <uint32_t> - <default>2000</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_ASYNC_NEST_FREQ_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CHIP_REGIONS_TO_ENABLE</id> - <description> - Called to get data to customize an IPL or SLW image with data indicating - which chip regions the SBE should enable - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CHIP_REGIONS_TO_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>BOOT_FREQ_MHZ</id> - <description> - EQ Boot frequency in MHZ. - </description> - <simpleType> - <uint32_t> - <default>2400</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_BOOT_FREQ_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EX_GARD_BITS</id> - <description> - Vector to communicate the guarded EX chiplets to SBE - One Guard bit per EX chiplet, bit location aligned to chiplet ID - (bit 16: EX00, bit 17: EX01, bit 18: EX02 ... bit 31: EX15) - Guarded EX chiplets are marked by a '1'. - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EX_GARD_BITS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> -<id>PIB_I2C_REFCLOCK</id> -<description> - i2c reference clock for the system. - default is 0x4 => I2C speed = ~1Mhz per Andreas Koenig -</description> - <simpleType> - <uint32_t> - <default>0x4</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PIB_I2C_REFCLOCK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_ADU_UNTRUSTED_BAR_BASE_ADDR</id> - <description> - ADU Untrusted BAR base address (secure mode) - creator: platform - firmware notes: - 64-bit address representing BAR RA - </description> - <simpleType> - <uint64_t> - <default>0x0000000000000000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_ADU_UNTRUSTED_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> -<id>PIB_I2C_NEST_PLL</id> -<description> - i2c pll for the system - default is 0x26 (For PIB @500 MHz (2 GHz nest)) for - I2C speed = ~1Mhz per Andreas Koenig. -</description> - <simpleType> - <uint32_t> - <default>0x026</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PIB_I2C_NEST_PLL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_ADU_UNTRUSTED_BAR_SIZE</id> - <description> - ADU Untrusted BAR size (secure mode) - creator: platform - firmware notes: - mask applied to RA 14:43 - </description> - <simpleType> - <uint64_t> - <default>0x0000000000000000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_ADU_UNTRUSTED_BAR_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> -<id>SBE_IMAGE_OFFSET</id> -<description> - HostBoot image for SBE, offset to account for ECC - Default is calculated from Hostboot base image of 0x03f67000 -</description> - <simpleType> - <uint32_t> - <default>0xfff78000</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_IMAGE_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SBE_IMAGE_MINIMUM_VALID_EXS</id> - <description> - The minimum number of valid EXs that is required to be used when - customizing a SBE image. The customization will fail if it cannot - create an image with at least this many EXs. - </description> - <simpleType> - <uint32_t> - <default>3</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_IMAGE_MINIMUM_VALID_EXS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PSI_UNTRUSTED_BAR0_BASE_ADDR</id> - <description> - PSI Untrusted BAR0 base address (secure mode) - creator: platform - firmware notes: - 64-bit address representing BAR RA - </description> - <simpleType> - <uint64_t> - <default>0x0000000000000000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PSI_UNTRUSTED_BAR0_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> -<id>BOOT_VOLTAGE</id> -<description> - Boot Voltage for system. - 0:2 -> port enables (3b - system design based: - port 0 for non-redundant systems (100); all ports for non-redundant (111)) - 3 -> Unused - - current recommended default = 1000b - 4:7 -> phase enables (4b - defined by the system power design) - - current recommended default = 0000b - 8:15 -> VDD voltage (1B in VRM-11 encoded form - 6.25mV increments) - note: VPD is in 5mV increments - - current recommended default = 0x52 - 16:23 -> VCS voltage (1B in VRM-11 encoded form - 6.25mV increments) - note: VPD is in 5mV increments - -current recommended default = 0x4a - 24:31 -> Unused = 0x00 -</description> - <simpleType> - <uint32_t> - <default>0x80524a00</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_BOOT_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PSI_UNTRUSTED_BAR0_SIZE</id> - <description> - PSI Untrusted BAR0 size (secure mode) - creator: platform - firmware notes: - mask applied to RA 14:43 - </description> - <simpleType> - <uint64_t> - <default>0x0000000000000000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PSI_UNTRUSTED_BAR0_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PSI_UNTRUSTED_BAR1_BASE_ADDR</id> - <description> - PSI Untrusted BAR1 base address (secure mode) - creator: platform - firmware notes: - 64-bit address representing BAR RA - </description> - <simpleType> - <uint64_t> - <default>0x0000000000000000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PSI_UNTRUSTED_BAR1_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PSI_UNTRUSTED_BAR1_SIZE</id> - <description> - PSI Untrusted BAR1 size (secure mode) - creator: platform - firmware notes: - mask applied to RA 14:43 - </description> - <simpleType> - <uint64_t> - <default>0x0000000000000000</default> - </uint64_t> - </simpleType> + <id>NEST_VCS_ID</id> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PSI_UNTRUSTED_BAR1_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_SECURITY_SETUP_VECTOR</id> - <description> - Secureboot 64-bit proc_sbe_security_setup_vector used - by proc_sbe_security_setup.S. 0s are an unsecure SBE image - creator: platform - firmware notes: - 64-bit proc_sbe_security_setup_vector - </description> + <readable></readable> <simpleType> - <uint64_t> - <default>0x8000000080000000</default> - </uint64_t> + <uint16_t> + <default>0</default> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_SECURITY_SETUP_VECTOR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<!-- ===== Attributes supporting memory_attributes.xml HWPF Attributes ===== --> -<attribute> - <id>MSS_VDDR_PROGRAM</id> + <attribute> <description>VDDR memory programming type 0 = POWERON - domain is programmed as part of regular power on sequence, 1 = STATIC - domain needs to be programmed, no special computation needed, 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic </description> + <hasStringConversion></hasStringConversion> + <id>MSS_VDDR_PROGRAM</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t><default>0</default></uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hasStringConversion/> -</attribute> -<attribute> - <id>MSS_VPP_PROGRAM</id> + </attribute> + + <attribute> <description>VPP memory programming type 0 = POWERON - domain is programmed as part of regular power on sequence, 1 = STATIC - domain needs to be programmed, no special computation needed, 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic </description> + <hasStringConversion></hasStringConversion> + <id>MSS_VPP_PROGRAM</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t><default>0</default></uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hasStringConversion/> -</attribute> -<attribute> - <id>MSS_VCS_PROGRAM</id> + </attribute> + + <attribute> <description>VCS memory programming type 0 = POWERON - domain is programmed as part of regular power on sequence, 1 = STATIC - domain needs to be programmed, no special computation needed, 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic </description> + <hasStringConversion></hasStringConversion> + <id>MSS_VCS_PROGRAM</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t><default>0</default></uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hasStringConversion/> -</attribute> -<attribute> - <id>MSS_AVDD_PROGRAM</id> + </attribute> + + <attribute> <description>AVDD memory programming type 0 = POWERON - domain is programmed as part of regular power on sequence, 1 = STATIC - domain needs to be programmed, no special computation needed, 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic </description> + <hasStringConversion></hasStringConversion> + <id>MSS_AVDD_PROGRAM</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t><default>0</default></uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hasStringConversion/> -</attribute> -<attribute> - <id>MSS_VDD_PROGRAM</id> + </attribute> + + <attribute> <description>VDD memory programming type 0 = POWERON - domain is programmed as part of regular power on sequence, 1 = STATIC - domain needs to be programmed, no special computation needed, 2 = DYNAMIC - domain needs to be programmed, uses dynamic vid logic </description> + <hasStringConversion></hasStringConversion> + <id>MSS_VDD_PROGRAM</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t><default>0</default></uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hasStringConversion/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_VDDR_MILLIVOLTS</id> + <attribute> <description> DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts @@ -7314,21 +2140,20 @@ firmware notes: Used as override attribute for pstate procedure consumer: mss_eff_cnfg, others firmware notes: none </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_VDDR</id> - <macro>DIRECT</macro> + <id>ATTR_MSS_VOLT_VDDR</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> + <id>MSS_VOLT_VDDR_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_VPP_MILLIVOLTS</id> <!-- VPP_BASE --> + <attribute> <description> DRAM VPP Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4 @@ -7336,44 +2161,36 @@ firmware notes: Used as override attribute for pstate procedure consumer: mss_eff_cnfg, others firmware notes: none </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_VPP</id> - <macro>DIRECT</macro> + <id>ATTR_MSS_VOLT_VPP</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> + <id>MSS_VOLT_VPP_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_VCS_MILLIVOLTS</id> + <attribute> <description> Computed in mss_volt C code - in millivolts creator: mss_volt consumer: mss_eff_cnfg, others firmware notes: none </description> + <id>MSS_VOLT_VCS_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -<!-- TODO RTC:157672 - <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_VCS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> ---> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_VDD_MILLIVOLTS</id> + <attribute> <description> DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts @@ -7381,23 +2198,16 @@ firmware notes: Used as override attribute for pstate procedure consumer: mss_eff_cnfg, others firmware notes: none </description> + <id>MSS_VOLT_VDD_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -<!-- TODO RTC:157672 - <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_VDD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> ---> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_AVDD_MILLIVOLTS</id> + <attribute> <description> DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts @@ -7405,25 +2215,16 @@ firmware notes: Used as override attribute for pstate procedure consumer: mss_eff_cnfg, others firmware notes: none </description> + <id>MSS_VOLT_AVDD_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -<!-- TODO RTC:157672 - <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_AVDD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> ---> -</attribute> - + <writeable></writeable> + </attribute> -<!-- Calculated dynamic voltages --> -<attribute> - <id>MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id> + <attribute> <description> DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts @@ -7431,23 +2232,16 @@ firmware notes: Used as override attribute for pstate procedure consumer: mss_eff_cnfg, others firmware notes: none </description> + <id>MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -<!-- TODO RTC:157672 - <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_VDDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> ---> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_VPP_OFFSET_MILLIVOLTS</id> <!-- VPP_BASE --> + <attribute> <description> DRAM VPP Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts. 0V - DDR3, 2.5V - DDR4 @@ -7455,46 +2249,32 @@ firmware notes: Used as override attribute for pstate procedure consumer: mss_eff_cnfg, others firmware notes: none </description> + <id>MSS_VOLT_VPP_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -<!-- TODO RTC:157672 - <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_VPP_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> ---> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id> + <attribute> <description> Computed in mss_volt C code - in millivolts creator: mss_volt consumer: mss_eff_cnfg, others firmware notes: none </description> + <id>MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -<!-- TODO RTC:157672 - <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_VCS_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> ---> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id> + <attribute> <description> DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts @@ -7502,23 +2282,16 @@ firmware notes: Used as override attribute for pstate procedure consumer: mss_eff_cnfg, others firmware notes: none </description> + <id>MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -<!-- TODO RTC:157672 - <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_VDD_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> ---> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id> + <attribute> <description> DRAM Voltage, each voltage rail would need to have a value. Computed in mss_volt C code - in millivolts @@ -7526,7154 +2299,240 @@ firmware notes: Used as override attribute for pstate procedure consumer: mss_eff_cnfg, others firmware notes: none </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -<!-- TODO RTC:157672 - <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_AVDD_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> ---> -</attribute> -<!-- end of Dynamic voltage --> - - -<attribute> - <id>MSS_FREQ</id> - <description> - Frequency of this memory channel in MT/s (Mega Transfers per second), - comprising of three DIMMs. - Computed in mss_freq - creator: mss_freq - consumer: mss_eff_cnfg, others - firmware notes: none - MT1866 = 1866, - MT2133 = 2133, - MT2400 = 2400, - MT2666 = 2666 - </description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_FREQ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_DIMM_MFG_ID_CODE</id> - <description>Manufacturer ID Code RCD: bits(31:16), Module: bits(15:0)</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DIMM_MFG_ID_CODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_RANKS_CONFIGED</id> - <description>DIMM ranks configured. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_NUM_RANKS_PER_DIMM</id> - <description> - Number of ranks in each DIMM. - Used in various locations and is computed in mss_eff_cnfg. - values are 0,1,2, 4 up to 32 - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_MFG_ID</id> - <description> - DRAM Manufacturer ID Code - Decodes SPD Byte 350 and 351 - creator: mss_eff_cnfg - consumer: power_thermal::decoder - </description> - <simpleType> - <uint16_t> - </uint16_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_MFG_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_WIDTH</id> - <description> - DRAM Device Width: X4, X8, X16, X32. - Used in various locations and is computed in mss_eff_cnfg. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - X4 = 4, X8 = 8, X16 = 16, X32 = 32 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_WIDTH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_RANK_MIX</id> - <description> - DRAM Device Rank Mix - Used in various locations and is computed in mss_eff_cnfg. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - SYMMETRICAL = 0, ASYMMETICAL = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_RANK_MIX</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>EFF_PRIMARY_RANK_GROUP0</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_PRIMARY_RANK_GROUP0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_PRIMARY_RANK_GROUP1</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_PRIMARY_RANK_GROUP1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_PRIMARY_RANK_GROUP2</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_PRIMARY_RANK_GROUP2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_PRIMARY_RANK_GROUP3</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_PRIMARY_RANK_GROUP3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SECONDARY_RANK_GROUP0</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SECONDARY_RANK_GROUP0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SECONDARY_RANK_GROUP1</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SECONDARY_RANK_GROUP1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SECONDARY_RANK_GROUP2</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SECONDARY_RANK_GROUP2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SECONDARY_RANK_GROUP3</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SECONDARY_RANK_GROUP3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_TERTIARY_RANK_GROUP0</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_TERTIARY_RANK_GROUP0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_TERTIARY_RANK_GROUP1</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_TERTIARY_RANK_GROUP1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_TERTIARY_RANK_GROUP2</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_TERTIARY_RANK_GROUP2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_TERTIARY_RANK_GROUP3</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_TERTIARY_RANK_GROUP3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_QUATERNARY_RANK_GROUP0</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_QUATERNARY_RANK_GROUP0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_QUATERNARY_RANK_GROUP1</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_QUATERNARY_RANK_GROUP1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_QUATERNARY_RANK_GROUP2</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_QUATERNARY_RANK_GROUP2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_QUATERNARY_RANK_GROUP3</id> - <description> - RankGroup. Used in various locations and is computed in mss_eff_cnfg_rank_group. - creator: mss_eff_cnfg_rank_group - consumer: various - firmware notes: none - INVALID = 255 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_QUATERNARY_RANK_GROUP3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- TODO RTC 87603. These termination data EFF attributes have corresponding - VPD attributes that come from CVPD. When all HWPs are using the VPD - versions, these EFF versions can be deleted --> - -<attribute> - <id>EFF_DRAM_RON</id> - <description> - DRAM Ron. - Used in various locations and comes from the MT keyword of the VPD - OHM48 is for DDR4. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_RON</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_WR_VREF</id> - <description> - DRAM Write Vref. - Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. - creator: VPD(MT) or mss_eff_cnfg_termination - consumer: various.C and initfile - firmware notes: none - This is the nominal value - This is for DDR3 - VDD420 = 420, - VDD425 = 425, - VDD430 = 430, - VDD435 = 435, - VDD440 = 440, - VDD445 = 445, - VDD450 = 450, - VDD455 = 455, - VDD460 = 460, - VDD465 = 465, - VDD470 = 470, - VDD475 = 475, - VDD480 = 480, - VDD485 = 485, - VDD490 = 490, - VDD495 = 495, - VDD500 = 500, - VDD505 = 505, - VDD510 = 510, - VDD515 = 515, - VDD520 = 520, - VDD525 = 525, - VDD530 = 530, - VDD535 = 535, - VDD540 = 540, - VDD545 = 545, - VDD550 = 550, - VDD555 = 555, - VDD560 = 560, - VDD565 = 565, - VDD570 = 570, - VDD575 = 575 - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_WR_VREF</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_WRDDR4_VREF</id> - <description>DRAM Write Vref for DDR4. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_WRDDR4_VREF</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_DRV_IMP_DQ_DQS</id> - <description>Centaur DQ and DQS Drive Impedance. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_DRV_IMP_ADDR</id> - <description>Centaur Address Drive Impedance. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_DRV_IMP_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_DRV_IMP_CNTL</id> - <description>Centaur Control Drive Impedance. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_DRV_IMP_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_DRV_IMP_CLK</id> - <description>Centaur Clock Drive Impedance. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_DRV_IMP_CLK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_DRV_IMP_SPCKE</id> - <description>Centaur Spare Clock Drive Impedance. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_DRV_IMP_SPCKE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_RCV_IMP_DQ_DQS</id> - <description>Centaur DQ and DQS Receiver Impedance. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_RCV_IMP_DQ_DQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_SLEW_RATE_DQ_DQS</id> - <description>Centaur DQ and DQS Slew Rate. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_SLEW_RATE_DQ_DQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_SLEW_RATE_ADDR</id> - <description>Centaur Address Slew Rate. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_SLEW_RATE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_SLEW_RATE_CLK</id> - <description>Centaur Clock Slew Rate. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_SLEW_RATE_CLK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_SLEW_RATE_SPCKE</id> - <description>Centaur Spare Clock Slew Rate. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_SLEW_RATE_SPCKE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_SLEW_RATE_CNTL</id> - <description>Centaur Control Slew Rate. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_SLEW_RATE_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_RD_VREF</id> - <description>Centaur Read Vref. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_RD_VREF</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- TODO RTC 87603 down to here --> - -<attribute> - <id>EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO</id> - <description>Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_DRV_IMP_CLK_SCHMOO</id> - <description>Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_DRV_IMP_CLK_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_DRV_IMP_SPCKE_SCHMOO</id> - <description>Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_DRV_IMP_SPCKE_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_DRV_IMP_CNTL_SCHMOO</id> - <description>Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_DRV_IMP_CNTL_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO</id> - <description>Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO</id> - <description>Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_SLEW_RATE_CLK_SCHMOO</id> - <description>Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_SLEW_RATE_CLK_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_SLEW_RATE_SPCKE_SCHMOO</id> - <description>Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_SLEW_RATE_ADDR_SCHMOO</id> - <description>Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_SLEW_RATE_ADDR_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_SLEW_RATE_CNTL_SCHMOO</id> - <description>Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_WR_VREF_SCHMOO</id> - <description> - Enables for which VREF to use on the WR Schmoo. - The LSB corresponds to the highest WR Vref - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_WR_VREF_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_WRDDR4_VREF_SCHMOO</id> - <description> - Enables for which VREF to use on the WR Schmoo. - The LSB corresponds to the highest WR Vref - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_WRDDR4_VREF_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_RD_VREF_SCHMOO</id> - <description>Enables for which VREF value can be used in timing adjustments. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_RD_VREF_SCHMOO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_SIZE</id> - <description> - DIMM Size, in GB Used in various locations and is computed in mss_eff_cnfg. - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_BANKS</id> - <description>Number of DRAM banks. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_BANKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_ROWS</id> - <description>Number of DRAM rows. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_ROWS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_COLS</id> - <description>Number of DRAM columns. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_COLS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TRRD</id> - <description>DRAM Row ACT to Row ACT Delay. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRRD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>EFF_DRAM_TRFI</id> - <description>Refresh Interval. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRFI</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TWTR</id> - <description>DRAM Internal Write to Read Delay. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TWTR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TRTP</id> - <description> - Internal Read to Precharge Delay. - From the DDR4 spec (79-4A). - Each memory channel will have a value. - creator: mss_eff_cnfg_timing - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array> 2 </array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRTP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TRRD_DLR</id> - <description> - Minimum Activate to Activate Delay Time (different logical ranks) - in nck (number of clock cycles). - For 3DS, The tRRD_S time to a different logical rank is defined as tRRD_dlr. - Each memory channel will have a value. - creator: eff_confg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array> 2 </array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRRD_DLR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TRFC_DLR</id> - <description> - Minimum Refresh Recovery Delay Time (different logical ranks) - in nck (number of clock cyles). - Selected tRFC value (tRFC_dlr1, tRFC_dlr2, or tRFC_dlr4) - depends on MRW attribute that selects fine refresh mode (x1, x2, x4). - For 3DS, The tRFC time to different logical ranks are defined as tRFC_dlr - creator: eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array> 2 </array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRFC_DLR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TFAW_DLR</id> - <description> - Minimum Four Activate Window Delay Time - in nck (number of clock cycles). - For 3DS, the tFAW time to different logical ranks are defined as tFAW_dlr - Each memory channel will have a value. - creator: eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array> 2 </array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TFAW_DLR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TXS</id> - <description> - Exit Self-Refresh to commands not requiring a locked DLL. - In nck (number of clock cycles). - Each memory channel will have a value. - creator: eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array> 2 </array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TXS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_CL</id> - <description> - CAS Latency. - Each memory channel will have a value. - creator: mss_freq - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_CL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_AL</id> - <description> - Additive Latency. - Used in various locations and is computed in mss_eff_cnfg_timing. - Each memory channel will have a value. - creator: mss_eff_cnfg_timing - consumer: various - firmware notes: none - DISABLE = 0, CL_MINUS_1 = 1, CL_MINUS_2 = 2 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_AL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_CWL</id> - <description> - CAS Write Latency. - Used in various locations and is computed in mss_eff_cnfg_timing. - Each memory channel will have a value. - creator: mss_eff_cnfg_timing - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_CWL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_RBT</id> - <description> - Read Burst Type. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - SEQUENTIAL = 0, INTERLEAVE = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_RBT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TM</id> - <description> - Test Mode. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - NORMAL= 0, TEST = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_DLL_RESET</id> - <description> - DLL Reset. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - NO = 0, YES = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_DLL_RESET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_WR</id> - <description>DRAM Write Recovery. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_WR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_DLL_PPD</id> - <description> - DLL Precharge PD. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - SLOWEXIT = 0, FASTEXIT = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_DLL_PPD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_DLL_ENABLE</id> - <description> - DLL Enable. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - ENABLE = 0, DISABLE = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_DLL_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TDQS</id> - <description> - TDQS. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array> 2 </array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TDQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TREFI</id> - <description> - Average Refresh Interval (tREFI) - in nck (number of clock cycles). - This depends on MRW attribute that selects fine refresh mode (x1, x2, x4). - From DDR4 spec (79-4A). - - For 3DS, the tREFI time to the same logical rank is defined as - tRFC_slr1, tRFC_slr2, or tRFC_slr4. - </description> - <simpleType> - <uint16_t> - </uint16_t> - <array> 2 </array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TREFI</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_WR_LVL_ENABLE</id> - <description> - Write Level Enable. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - DISABLE = 0, ENABLE = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_WR_LVL_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_OUTPUT_BUFFER</id> - <description> - DRAM Qoff. - Enables or disables DRAM output. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - ENABLE = 0, DISABLE = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_OUTPUT_BUFFER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_PASR</id> - <description> - Partial Array Self-Refresh. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - FULL = 0, - FIRST_HALF = 1, - FIRST_QUARTER = 2, - FIRST_EIGHTH = 3, - LAST_THREE_FOURTH = 4, - LAST_HALF = 5, - LAST_QUARTER = 6, - LAST_EIGHTH = 7 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_PASR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_ASR</id> - <description> - Auto Self-Refresh. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - SRT = 0, ASR = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_ASR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_SRT</id> - <description> - Self-Refresh Temperature Range. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - NORMAL = 0, EXTEND = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_SRT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_MPR_LOC</id> - <description> - Multi Purpose Register Location. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_MPR_LOC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_MPR_MODE</id> - <description> - Multi Purpose Register Mode. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - DISABLE = 0, ENABLE = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_MPR_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_RCD_CNTL_WORD_0_15</id> - <description>DIMM RCD Control Word. Initialized and used by HWPs.</description> - <simpleType> - <uint64_t> - </uint64_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_RCD_MIRROR_MODE</id> - <description> - RCD Mirroring. Used in mss_dram_init and is computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_RCD_MIRROR_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SCHMOO_MODE</id> - <description> - Specifies the schmoo mode to use during draminit_train_adv. Initialized and used by HWPs. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SCHMOO_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SCHMOO_ADDR_MODE</id> - <description> - Specifies the schmoo mode to use during draminit_train_adv. Initialized and used by HWPs. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SCHMOO_ADDR_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SCHMOO_TEST_VALID</id> - <description> - Specifies the schmoo test to run during draminit_train_adv. Initialized and used by HWPs. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SCHMOO_TEST_VALID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SCHMOO_PARAM_VALID</id> - <description> - Specifies the schmoo parameters to use during draminit_train_adv. Initialized and used by HWPs. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SCHMOO_PARAM_VALID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SCHMOO_WR_EYE_MIN_MARGIN</id> - <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SCHMOO_RD_EYE_MIN_MARGIN</id> - <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id> - <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SCHMOO_RD_GATE_MIN_MARGIN</id> - <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id> - <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_MEMCAL_INTERVAL</id> - <description> - Specifies the memcal interval in clocks. Initialized and used by HWPs. - DISABLE = 0 - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_MEMCAL_INTERVAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_ZQCAL_INTERVAL</id> - <description> - Specifies the zqcal interval in clocks. Initialized and used by HWPs. - DISABLE = 0 - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_ZQCAL_INTERVAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_IBM_TYPE</id> - <description>Specifies the memory topology type. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_IBM_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_NUM_DROPS_PER_PORT</id> - <description>Specifies the number of DIMM dimensions that are valid per port. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_NUM_DROPS_PER_PORT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_STACK_TYPE</id> - <description>Specifies the DRAM package type. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_STACK_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_NUM_MASTER_RANKS_PER_DIMM</id> - <description>Specifies the number of master ranks per DIMM. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_NUM_PACKAGES_PER_RANK</id> - <description>Specifies the number of DRAM packages per rank. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_NUM_PACKAGES_PER_RANK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_PRIM_DIE_COUNT</id> - <description>Specifies the number of DRAM dies per package. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_PRIM_DIE_COUNT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> - <description> - This is the throttled N commands per window - of M DRAM clocks setting for cfg_nm_n_per_port. - Initialized and used by HWPs. - </description> - <simpleType> - <uint16_t> - </uint16_t> - <array>2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MEM_M_DRAM_CLOCKS</id> - <description> - This is the throttled M DRAM clocks setting for cfg_nm_m. - creator: mss_eff_cnfg - consumer: mc_config - firmware notes: none - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MEM_M_DRAM_CLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id> - <description> - This is the throttle numerator setting for cfg_nm_n_per_slot - </description> - <simpleType> - <uint16_t> - </uint16_t> - <array>2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_DIMM_THERMAL_LIMIT</id> - <description> - DIMM Max Power based on a thermal limit - Decoded from ATTR_MSS_MRW_THERMAL_POWER_LIMIT - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DIMM_THERMAL_LIMIT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_NUM_DIES_PER_PACKAGE</id> - <description>Specifies the number of DRAM dies per package. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_NUM_DIES_PER_PACKAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MEM_THROTTLE_NUMERATOR_PER_MBA</id> - <description>DIMM throttle numerator. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MEM_THROTTLE_DENOMINATOR</id> - <description>DIMM throttle denominator. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MEM_THROTTLE_DENOMINATOR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> - <description>This is the throttle numerator setting for cfg_nm_n_per_chip. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MEM_WATT_TARGET</id> - <description> - Total memory power limit in cW for the dimms on the memory channel pair. - Used to compute the throttles on the channel and/or dimms. - creator: unknown. - consumer: mss_eff_config. - firmware notes: none. - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MEM_WATT_TARGET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_POWER_SLOPE</id> - <description>DIMM Power slope value. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_POWER_SLOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MASTER_PWR_SLOPE</id> - <description>Master Power slope value for dimm. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MASTER_PWR_SLOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_SUPPLIER_PWR_SLOPE</id> - <description>Supplier Power slope value for dimm. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_SUPPLIER_PWR_SLOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_POWER_SLOPE2</id> - <description>DIMM Power slope value. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_POWER_SLOPE2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_POWER_INT</id> - <description>DIMM Power intercept value. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_POWER_INT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MASTER_PWR_INTERCEPT</id> - <description> - Master Power intercept value for dimm - Initialized and used by HWPs. - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MASTER_PWR_INTERCEPT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_SUPPLIER_PWR_INTERCEPT</id> - <description> - Supplier Power intercept value for dimm - Initialized and used by HWPs. - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_SUPPLIER_PWR_INTERCEPT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_POWER_INT2</id> - <description>Supplier Power intercept value for dimm</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_POWER_INT2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_TOTAL_POWER_SLOPE</id> - <description>Master Total Power slope value for dimm</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_TOTAL_POWER_SLOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_TOTAL_POWER_SLOPE2</id> - <description>Supplier Total Power slope value for dimm</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_TOTAL_POWER_SLOPE2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_TOTAL_POWER_INT</id> - <description>Master Total Power intercept value for dimm</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_TOTAL_POWER_INT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_TOTAL_POWER_INT2</id> - <description>Supplier Total Power intercept value for dimm</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_TOTAL_POWER_INT2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_DIMM_MAXBANDWIDTH_GBS</id> - <description>DIMM Max Bandwidth in GBs output from thermal procedures. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DIMM_MAXBANDWIDTH_GBS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_DIMM_MAXBANDWIDTH_MRS</id> - <description>DIMM Max Bandwidth in MRs output from thermal procedures Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DIMM_MAXBANDWIDTH_MRS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_CHANNEL_MAXBANDWIDTH_GBS</id> - <description>Channel Max Bandwidth in GBs. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_GBS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id> - <description>Pair Max Bandwidth in GBs output from thermal procedures. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_CHANNEL_MAXBANDWIDTH_MRS</id> - <description>Channel Max Bandwidth MRs. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_MRS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id> - <description>Channel Pair Max Bandwidth MRs output from thermal procedures. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_DIMM_MAXPOWER</id> - <description>DIMM Max Power output from thermal procedures. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,2</array><!-- [drop][port] --> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DIMM_MAXPOWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_CHANNEL_MAXPOWER</id> - <description>Channel Max Power output. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_CHANNEL_MAXPOWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_CHANNEL_PAIR_MAXPOWER</id> - <description>Channel Pair Max Power output from thermal procedures. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_CHANNEL_PAIR_MAXPOWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> - <description> - Runtime throttled N commands per - M DRAM clocks setting for cfg_nm_n_per_port. - Initialized and used by HWPs. - </description> - <simpleType> - <uint16_t> - </uint16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_RUNTIME_MEM_M_DRAM_CLOCKS</id> - <description> - Runtime for M DRAM clocks setting for cfg_nm_m - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_RUNTIME_MEM_M_DRAM_CLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id> - <description> - Runtime throttle numerator setting for cfg_nm_n_per_slot - </description> - <simpleType> - <uint16_t> - </uint16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA</id> - <description>Runtime throttle numerator setting for cfg_nm_n_per_mba. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR</id> - <description>Runtime throttle denominator setting for cfg_nm_m. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> - <description>Runtime throttle numerator setting for cfg_nm_n_per_chip. Initialized and used by HWPs.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_ZSERIES</id> - <description>Determines if the code is Zseries type or P Series. The platform determines this and this attribute is mostly used in the initfiles so that we can share the same initialization code with the zSeries team</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_ZSERIES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- Note: This looks incorrect because memory_attributes.xml says it is platInit (therefore we should set it up to a sensible value), - but recent discussions have concluded that a HWP will fill this in, this implementation is correct, memory_attributes.xml will eventually change. --> -<attribute> - <id>MSS_NWELL_MISPLACEMENT</id> - <description>Set by the platform depending on DD1 vs DD1.01. If true, then SI settings affected by the NWELL problem are adjusted. Used in eff_config</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_NWELL_MISPLACEMENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_INTERLEAVE_ENABLE</id> - <description> - Used in the setting of groups. It is a bit vector. If the value - BITWISE_AND 0x01 = 0x01 then groups of 1 are enabled, - if the value BITWISE_AND 0x02 = 0x02, then groups of 2 are possible, - if the value BITWISE_AND 0x04 = 0x04, then group of 3 are possible, - if the value BITWISE_AND 0x08 = 0x08, then groups of 4 are possible, - if the value BITWISE_AND 0x20 = 0x20, then groups of 6 are possible, - if the value BITWISE_AND 0x80 = 0x80, then groups of 8 are possible. - If no groups can formed according to this input, then an error will - be thrown. - Provided by the MRW - This attribute is based on Machine-Type-Model (MTM) and is setup by - the service processor. - </description> - <simpleType> - <uint8_t> - <default>0xAF</default><!-- Maximum interleaving --> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_INTERLEAVE_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_INTERLEAVE_GRANULARITY</id> - <description> - Determines the stride covered by each granule in an interleaving - group. The default stride -- 128B -- is the only value intended for - production FW use. All other combinations are for experimental - performance evaluation. - - Regardless of this attribute value, groups of size 1, 3, and 6 - will be forced to 128B stride based on the logic capabilities. - - 128_B = 0x00, - 256_B = 0x01, - 512_B = 0x02, - 1_KB = 0x03, - 2_KB = 0x04, - 4_KB = 0x05, - 8_KB = 0x06, - 16_KB = 0x07, - 32_KB = 0x08 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_INTERLEAVE_GRANULARITY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MBA_ADDR_INTERLEAVE_BIT</id> - <description>sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. valid values are 23 through 32.</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MBA_CACHELINE_INTERLEAVE_MODE</id> - <description>centaur interleave mode. 1 = 256-BIT, 0 = 128-BIT.</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_CACHE_ENABLE</id> - <description> - Specifies if a Memory Buffer chip L4 cache is enabled or disabled - For good memory buffer chips, L4 is enabled - Firmware can set to disabled for a particular chip if the cache is - not functional - 1 = enabled, 0 = disabled. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_CACHE_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_PREFETCH_ENABLE</id> - <description> - Value of on or off. Determines if prefetching enabled or not. - See chapter 7 of the Centaur Workbook. - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_PREFETCH_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_CLEANER_ENABLE</id> - <description> - Value of on or off. - Determines if the cleaner of the L4 cache (write modified entries to memory on idle cycles) - enabled or not. See chapter 7 of the Centaur Workbook. - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_CLEANER_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_LAB_OVERRIDE_FOR_MEM_PLL</id> - <description>override the default Centaur MEM PLL settings with user-specified scan chain data. 1 = ON, 0 = OFF.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_LAB_OVERRIDE_FOR_MEM_PLL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MEM_MC_IN_GROUP</id> - <description>A 8 bit vector that would be a designation of which MC are involved in the group. Initialized and used by HWPs.</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>8</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MEM_MC_IN_GROUP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MCS_GROUP_32</id> - <description> - Data Structure from eff grouping to setup bars to help determine - different groups - Non-Mirroring array[0-7] [0.17]: 0-- Port size; 1-- No of ports in group; 2-- Total group size of non-mirroring; - 3-- Base address; 4-11-- PortID number in group; - 12-- Alt Memory valid(0); 13-- Alt Memory valid (1); - 14-- Alt Group size (0); 15-- Alt Group size(1); - 16-- Alt Base address (0); 17-- Alt Base address (1); - - 13-- Alternate Group Size; 14-- Alternate Base address - Mirroring array[8-15] [0:17]: 0-- Port size; 1-- No of ports in group; 2-- Total group size of mirroring; - 3-- Base address; 4-11-- PortID number; - 12-- Alt Memory valid(0); 13-- Alt Memory valid (1); - 14-- Alt Group size (0); 15-- Alt Group size(1); - 16-- Alt Base address (0); 17-- Alt Base address (1); - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>16,18</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MCS_GROUP_32</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id> - <description> - A bit vector (per Dean's request) specifying if a DIMM is functional. - DIMM attributes, such as SIZE, are qualified by this bit vector. - The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional. - 0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional. - A fully populated system would have the value of 0xCC. - Used in various locations and is computed in mss_eff_cnfg. - Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none - This factors in functionality - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_CAL_STEP_ENABLE</id> - <description> - A bit map of vector denoting valid steps to run (0 is left most bit) - [0] DRAM_ZQCAL - [1] DB_ZQCAL (LRDIMM) - [2] MREP (LRDIMM) - [3] MRD - Coarse (LRDIMM) - [4] MRD - Fine (LRDIMM) - [5] WR_LEVEL - [6] INITIAL_PAT_WR - [7] WR_VREF_LATCH - [8] DWL (LRDIMM) - [9] MWD - Coarse (LRDIMM) - [10] MWD - Fine (LRDIMM) - [11] HWL (LRDIMM) - [12] DQS_ALIGN - [13] RDCLK_ALIGN - [14] READ_CTR_2D_VREF - [15] READ_CTR - [16] WRITE_CTR_2D_VREF - [17] WRITE_CTR - [18] COARSE_WR - [19] COARSE_RD - [20]:[31] Reserved for future use - - COARSE_WR and COARSE_RD will be consumed together to form COARSE_LVL. - - WRITE_CTR will be run, even if only WRITE_CTR_2D_VREF is enabled, - as the WR 2D VREF HW cal depends upon WRITE_CTR 1D to function. - - Note: LRDIMM steps will only be enabled for LRDIMMs and won't run on RDIMMs. - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_CAL_STEP_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MEM_IPL_COMPLETE</id> - <description>A numerical number indicating if the memory procedures are complete. written by mss_setup_bars when the bars are now functional in the processor. </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MEM_IPL_COMPLETE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_SLEW_RATE_DATA</id> - <description> - The 4 bit result of running the slew calibration algorithm at various rates and impedances. - The first dimension is port, the second is the impedance of 24,30,34, and 40 Ohms. - The 3rd dimension is the rate: 3,4,5 or 6 V/ns. - Computed and sent to the correct data blocks in phy_reset. - Also used in advanced training - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2, 4, 4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_SLEW_RATE_DATA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_SLEW_RATE_ADR</id> - <description> - The 4 bit result of running the slew calibration algorithm at various rates and impedances. - The first dimension is the port. The second is the impedance of 15, 20, 30 and 40 Ohms. - The 3rd dimension is the rate:3, 4,5 or 6 V/ns. - Computed and sent to the correct data blocks in phy_reset. - Also used in advanced training - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2, 4, 4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_SLEW_RATE_ADR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>ECID</id> - <description> - Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1 - Created from running proc_getecid.C for processors - Created from running mss_get_cen_ecid.C for centaurs - </description> - <simpleType> - <uint64_t> - </uint64_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_ECID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>C1_HAS_POWER</id> - <description> - Indicates core 1 has power and has valid latch state that could be scanned - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_C1_HAS_POWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>C0_HAS_POWER</id> - <description> - Indicates core 0 has power and has valid latch state that could be scanned - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_C0_HAS_POWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L3_HAS_POWER</id> - <description> - Indicates L3 has power and has valid latch state that could be scanned - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L3_HAS_POWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L2_HAS_POWER</id> - <description> - Indicates L2 has power and has valid latch state that could be scanned - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L2_HAS_POWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>C1_PC_HAS_CLOCKS</id> - <description> - Indicates the core pervasive unit in core 1 has clocks running and scommable - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_C1_PC_HAS_CLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>C0_PC_HAS_CLOCKS</id> - <description> - Indicates the core pervasive unit in core 0 has clocks running and scommable - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_C0_PC_HAS_CLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>C1_EXEC_HAS_CLOCKS</id> - <description> - Indicates the execution units in core 1 have clocks running and scommable - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_C1_EXEC_HAS_CLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>C0_EXEC_HAS_CLOCKS</id> - <description> - Indicates the execution units in core 0 have clocks running and scommable - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_C0_EXEC_HAS_CLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L3_HAS_CLOCKS</id> - <description> - Indicates the L3 region has clocks running and scommable - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L3_HAS_CLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>L2_HAS_CLOCKS</id> - <description> - Indicates the L2 region has clocks running and scommable - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L2_HAS_CLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OBUS_RATIO_VALUE</id> - <description> - Holds Obus ratio value - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OBUS_RATIO_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CME_LOCAL_FIRMASK</id> - <description> - The FIR mask value that has to be restored to the CME FIR - register. This value will be stored during the reset phase when the - FIRMASK will be cleared as part of the cleanup action. - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CME_LOCAL_FIRMASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>QUAD_PPM_ERRMASK</id> - <description> - The error mask value that has to be restored to the PPM - ERRMASK register for the Quad. This value will be stored during the - reset phase when the ERRMASK will be cleared as part of the - cleanup action. - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_QUAD_PPM_ERRMASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CORE_PPM_ERRMASK</id> - <description> - The error mask value that has to be restored to the PPM - ERRMASK register for the CORE. This value will be stored during the - reset phase when the ERRMASK will be cleared as part of the - cleanup action. - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CORE_PPM_ERRMASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SPD_OVERRIDE_ENABLE</id> - <description> - Set equal to 1 to activate the use of ATTR_SPD_OVERRIDE. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SPD_OVERRIDE_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SPD_OVERRIDE</id> - <description> - Byte-for-byte override for the bucket of data that would - normally come from SPD. If ATTR_SPD_OVERRIDE_ENABLE!=0 then - the value of this attribute will be returned to callers of - fapi2::getSPD() instead of the actual SPD contents. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>512</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SPD_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_OVERRIDE_MW_ENABLE</id> - <description> - Set equal to 1 to activate the use of ATTR_VPD_OVERRIDE_MW. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_OVERRIDE_MW_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_OVERRIDE_MW</id> - <description> - Byte-for-byte override for the bucket of MW data that would - normally come from VPD. If ATTR_VPD_OVERRIDE_MW_ENABLE!=0 then - the value of this attribute will be returned to callers of - fapi2::getVPD() instead of the actual VPD contents. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>255</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_OVERRIDE_MW</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_OVERRIDE_MR_ENABLE</id> - <description> - Set equal to 1 to activate the use of ATTR_VPD_OVERRIDE_MR. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_OVERRIDE_MR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_OVERRIDE_MR</id> - <description> - Byte-for-byte override for the bucket of MR data that would - normally come from VPD. If ATTR_VPD_OVERRIDE_MR_ENABLE!=0 then - the value of this attribute will be returned to callers of - fapi2::getVPD() instead of the actual VPD contents. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>255</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_OVERRIDE_MR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_OVERRIDE_MT_ENABLE</id> - <description> - Set equal to 1 to activate the use of ATTR_VPD_OVERRIDE_MT. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_OVERRIDE_MT_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_OVERRIDE_MT</id> - <description> - Byte-for-byte override for the bucket of MT data that would - normally come from VPD. If ATTR_VPD_OVERRIDE_MT_ENABLE!=0 then - the value of this attribute will be returned to callers of - fapi2::getVPD() instead of the actual VPD contents. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>255</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_OVERRIDE_MT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_OVERRIDE_DQ_ENABLE</id> - <description> - Set equal to 1 to activate the use of ATTR_VPD_OVERRIDE_DQ. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_OVERRIDE_DQ_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_OVERRIDE_DQ</id> - <description> - Byte-for-byte override for the bucket of DQ data that would - normally come from VPD. If ATTR_VPD_OVERRIDE_DQ_ENABLE!=0 then - the value of this attribute will be returned to callers of - fapi2::getVPD() instead of the actual VPD contents. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>160</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_OVERRIDE_DQ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_OVERRIDE_CK_ENABLE</id> - <description> - Set equal to 1 to activate the use of ATTR_VPD_OVERRIDE_CK. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_OVERRIDE_CK_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_OVERRIDE_CK</id> - <description> - Byte-for-byte override for the bucket of CK data that would - normally come from VPD. If ATTR_VPD_OVERRIDE_CK_ENABLE!=0 then - the value of this attribute will be returned to callers of - fapi2::getVPD() instead of the actual VPD contents. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_OVERRIDE_CK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--TOOD RTC: 151938 Make sure that these are set up by parseMRW script--> -<attribute> - <id>MSS_MRW_SUPPORTED_FREQ</id> - <description> - List of memory frequencies supported by the current system. - </description> - <simpleType> - <uint32_t> - <default>1866,2133,2400,2667</default> - </uint32_t> - <array>4</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_SUPPORTED_FREQ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MEMVPD_POS</id> - <description> - The position of the MCS target's VPD selector data, relative to the EEPROM - that contains its data. The VPD defition supports up to 16 values per - EEPROM. - For systems with an EEPROM per chip, this value should be equivalent to - ATTR_CHIP_UNIT_POS. - For systems with a single EEPROM for all chips, the value should follow - the physical position in such a way to fit within the 16 available slots. - </description> - <simpleType> - <uint8_t> - <default>0xFF</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MEMVPD_POS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <no_export/> -</attribute> - -<attribute> - <id>PBA_LFIR</id> - <description> - The attribute stores the Local FIR value of PBA taken - during the reset phase. - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PBA_LFIR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OCC_LFIR</id> - <description> - The attribute stores the Local FIR value of OCC taken - during the reset phase. - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_OCC_LFIR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_ALLOW_SINGLE_PORT</id> - <description> - When this value is true, then mss_eff config will allow a single port to have one dimm - and will allow ports to have different sizes. Used in eff_config - </description> - <simpleType> - <uint8_t> - <default>0</default> - <array>2</array> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_ALLOW_SINGLE_PORT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- TODO RTC 87603. These phase rotator EFF attributes have corresponding - VPD attributes that come from CVPD. When all HWPs are using the VPD - versions, these EFF versions can be deleted --> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CLK_P0</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CLK_P1</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CLK_P0</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CLK_P1</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A0</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A1</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A2</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A3</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A4</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A5</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A6</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A7</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A8</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A9</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A10</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A11</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A12</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A13</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A14</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_A15</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_BA0</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_BA1</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_BA2</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_CASN</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_RASN</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_CMD_WEN</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_PAR</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_PAR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M_ACTN</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M_ACTN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE0</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE1</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE2</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE3</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN0</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN1</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN2</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN3</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CNTL_ODT0</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M0_CNTL_ODT1</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE0</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE1</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE2</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE3</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN0</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN1</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN2</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN3</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CNTL_ODT0</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CEN_PHASE_ROT_M1_CNTL_ODT1</id> - <description>Phase rotator value that comes from termination on the CDIMM VPD</description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- TODO RTC 87603 down to here --> - -<attribute> - <id>MSS_DQS_SWIZZLE_TYPE</id> - <description> - DQS Swizzle type is set by the platform to describe what kind of DQS connection is being used for register acceses. - Type 0 is normal, type 1 is for systems with wiring like glacier 1, type 2 is for Pallmeto. - Additional types maybe defined if new boards have even different DQS swizzle features - </description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - <array>2</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DQS_SWIZZLE_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MCS_GROUP</id> - <description>Data Structure from eff grouping to setup bars to help determine different groups - Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address - // Mirroring [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address -Measured in GB</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>16,16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MCS_GROUP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CKE_MAP</id> - <description>Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CKE_MAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SPCKE_MAP</id> - <description>Rank to Spare CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SPCKE_MAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_SPARE</id> - <description> - Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. - creator: mss_eff_cnfg consumer: various firmware notes: load from spd - OBSOLETE: Use ATTR_VPD_DIMM_SPARE - NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_SPARE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_PSRO</id> - <description>Set by the centaur mss_get_cen_ecid function used diagnostic and chip characterization reporting</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_PSRO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- ===== End Attributes supporting memory_attributes.xml HWPF Attributes ===== --> - -<attribute> - <id>EI_BUS_TX_LANE_INVERT</id> - <description> - This attribute represents the polarity of a differential wire pair on the DMI and A buses. - creator: platform (generated based on MRW data) - See defintion in common_attributes.xml for more information. - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EI_BUS_TX_LANE_INVERT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <no_export/> -</attribute> - -<attribute> - <id>PROC_PERV_BNDY_PLL_CHIPLET_ID</id> - <description>Chiplet ID for ring image for perv_bndy_pll ring containing filter plls and xb_pll,nest_pll - creator: platform - firmware notes: - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PERV_BNDY_PLL_CHIPLET_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PB_BNDY_DMIPLL_CHIPLET_ID</id> - <description>Chiplet ID for ring image for pb_bndy_dmipll ring - creator: platform - firmware notes: - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PB_BNDY_DMIPLL_CHIPLET_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_AB_BNDY_PLL_CHIPLET_ID</id> - <description>Chiplet ID for ring image for ab_bndy_pll ring - creator: platform - firmware notes: - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_AB_BNDY_PLL_CHIPLET_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCI_BNDY_PLL_CHIPLET_ID</id> - <description>Chiplet ID for ring image for pci_bndy_pll ring - creator: platform - firmware notes: - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCI_BNDY_PLL_CHIPLET_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PERV_BNDY_PLL_SCAN_SELECT</id> - <description>Scan select for ring image for perv_bndy_pll ring containing filter plls and xb_pll,nest_pll - creator: platform - firmware notes: - </description> - <simpleType> - <uint32_t> - <default>0x00100008</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PERV_BNDY_PLL_SCAN_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PB_BNDY_DMIPLL_SCAN_SELECT</id> - <description>Scan select for ring image for pb_bndy_dmipll ring - creator: platform - firmware notes: - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PB_BNDY_DMIPLL_SCAN_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_AB_BNDY_PLL_SCAN_SELECT</id> - <description>Scan select for ring image for ab_bndy_pll ring - creator: platform - firmware notes: - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_AB_BNDY_PLL_SCAN_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCI_BNDY_PLL_SCAN_SELECT</id> - <description>Scan select for ring image for pci_bndy_pll ring - creator: platform - firmware notes: - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCI_BNDY_PLL_SCAN_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- ===== Supporting poreve_memory_attributes.xml ===== --> - -<attribute> - <id>SBE_SEEPROM_I2C_ADDRESS_BYTES</id> - <description> - The number of address bytes required to address the SEEPROM memory - device that contains SBE IPL code. This will vary by device based on - the device capacity, and must be either 1, 2, 3 or 4. - </description> - <simpleType> - <uint8_t> - <default>2</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_SEEPROM_I2C_ADDRESS_BYTES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SBE_SEEPROM_I2C_DEVICE_ADDRESS</id> - <description> - sbe seeprom iic device address - </description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SBE_SEEPROM_I2C_PORT</id> - <description> - SBE seeprom iic port - </description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> + <id>MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_SEEPROM_I2C_PORT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PNOR_I2C_ADDRESS_BYTES</id> - <description> - The number of address bytes required to address the PNOR memory device - via the pseudo-I2C (LPC, ECCAX) controller. This will vary by device - based on the device capacity, and must be either 0, 1, 2, 3 or 4. - - This attribute will be set to 0 for chips with no PNOR attached - (PoreVe will never run on these chips). - - Provided by the Machine Readable Workbook - </description> - <simpleType> - <uint8_t> - <default>4</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PNOR_I2C_ADDRESS_BYTES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- ===== End supporting poreve_memory_attributes.xml ===== --> - -<!-- Support for sync_attributes.xml --> -<attribute> - <id>SYNC_BETWEEN_STEPS</id> - <description> - Attribute to enable targetting attribute sync when in istep mode. - 1 = sync will occur following each substep when ipl'ing in single step mode - 0 = sync will not be done after each step - </description> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SYNC_BETWEEN_STEPS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<!-- End support for sync_attributes.xml --> - -<!-- Support for proc_select_boot_master --> - -<enumerationType> - <id>PROC_SELECT_BOOT_MASTER</id> - <description>Enumeration indicating which chip should be used as the PROC_SELECT_BOOT_MASTER</description> - <enumerator> - <name>PRIMARY</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SECONDARY</name> - <value>2</value> - </enumerator> -</enumerationType> - -<attribute> - <id>PROC_SELECT_BOOT_MASTER</id> - <description> - Specifies which chip should be used as the boot master - Initialized by the platform. - PRIMARY - the primary master is used for the BOOT - SECONDARY - the alternate master is used for the BOOT - Platforms are expected to set this to PRIMARY in normal operation - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_SELECT_BOOT_MASTER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<enumerationType> - <id>PROC_SELECT_SEEPROM_IMAGE</id> - <description>Enumeration indicating which SEEPROM image should be used for the boot master</description> - <enumerator> - <name>FIRST</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SECOND</name> - <value>2</value> - </enumerator> -</enumerationType> - -<attribute> - <id>PROC_SELECT_SEEPROM_IMAGE</id> - <description> - Specifies which SEEPROM image should be used for the boot master. - FIRST - the first image was selected - SECOND - the second image was selected - Platforms are expected to set this to FIRST in normal operation - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_SELECT_SEEPROM_IMAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>PROC_SELECT_BOOT_SEEPROM_IMAGE</id> - <description>Enumeration indicating which SEEPROM image should be used to boot a processor</description> - <enumerator> - <name>FIRST</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SECOND</name> - <value>2</value> - </enumerator> -</enumerationType> - -<attribute> - <id>PROC_SELECT_BOOT_SEEPROM_IMAGE</id> - <description> - Specifies which SEEPROM image should be used to boot a processor - FIRST - the first image was selected - SECOND - the second image was selected - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_SELECT_BOOT_SEEPROM_IMAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>ENABLED_THREADS</id> + <attribute> <description> Bitmask of threads to enable for each processor, Zero means enable all architected threads </description> + <id>ENABLED_THREADS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint64_t> - </uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MAX_PROC_CHIPS_PER_NODE</id> + <attribute> <description> System attribute. The max proc chips per node available in the system. </description> + <id>MAX_PROC_CHIPS_PER_NODE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> + </attribute> -<attribute> - <id>MAX_EXS_PER_PROC_CHIP</id> + <attribute> <description> System attribute. The max EX units per proc chip available in the system. </description> + <id>MAX_EXS_PER_PROC_CHIP</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MAX_DIMMS_PER_MBA_PORT</id> + <attribute> <description> System attribute. The max DIMMs per MBA Port available in the system. </description> + <id>MAX_DIMMS_PER_MBA_PORT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MAX_MBA_PORTS_PER_MBA</id> + <attribute> <description> System attribute. The max MBA ports per MBA available in the system. </description> + <id>MAX_MBA_PORTS_PER_MBA</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MAX_MBAS_PER_MEMBUF_CHIP</id> + <attribute> <description> System attribute. The max MBAS per membuf available in the system. </description> + <id>MAX_MBAS_PER_MEMBUF_CHIP</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MAX_CHIPLETS_PER_PROC</id> + <attribute> <description> System attribute. The max chiplets per proc available in the system. </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> + <id>MAX_CHIPLETS_PER_PROC</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MAX_MCS_PER_SYSTEM</id> - <description> - System attribute. - The max MCS units available in the system. - </description> + <readable></readable> <simpleType> - <uint8_t> - <default>4</default> - </uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> + </attribute> -<attribute> - <id>MAX_DMI_PER_PROC</id> + <attribute> <description> System attribute. - The max DMI units per proc available in the system. + The max MCS units available in the system. </description> - <simpleType> - <uint8_t> - <default>8</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>TEST_NEGATIVE_FCN</id> - <description>Attribute to test signed attribute - functionality in the system</description> - <simpleType> - <int8_t> - <default>-6</default> - </int8_t> - </simpleType> + <id>MAX_MCS_PER_SYSTEM</id> <persistency>non-volatile</persistency> - <writeable/> - <readable/> -</attribute> - -<!-- Note: This attribute is only used by FSP --> -<attribute> - <id>DMI_REFCLOCK_SWIZZLE</id> - <description> - Defines Murano/Venice/Naples FSI GP8 refclock enable field bit offset (0:7) associated with this MCS chip unit. - </description> + <readable></readable> <simpleType> <uint8_t> - <default>0</default> + <default>4</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_DMI_REFCLOCK_SWIZZLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <no_export/> -</attribute> - -<attribute> - <id>EI_BUS_TX_MSBSWAP</id> - <description> - Source: MRW: Downstream MSB Swap and Upstream MSB Swap - Usage: TX_MSBSWAP initfile setting for DMI and A buses - - This attribute represents whether or not a single clock group bus such as DMI and A bus was wired by the board designer using a feature - called MSB Swap where lane 0 of the TX chip wires to lane n-1 on the RX chip where 'n' is the width of the bus. A basic description - of this capability is that the board designer can save layers on the board wiring by crossing the wiring between the two chips in - a prescribed manner. In a non-MSB Swapped bus Lane 0 on the TX chip wires to lane 0 on the RX chip, lane 1 to lane 1 and so on. - If a bus is MSB Swapped then lane 0 of the TX chip wires to lane 'n-1' of the RX chip, lane 1 to lane 'n-2', etc. Random or - arbitrary wiring of TX to RX lanes on different chips is NOT ALLOWED. - - The Master Chip of two connected chips is defined as the chip with the smaller value of (100*Node + Pos). - The Slave Chip of two connected chips is defined as the chip with the larger value of (100*Node + Pos). - The Downstream direction is defined as the direction from the Master chip to the Slave chip. - The Upstream direction is defined as the direction from the Slave chip to the Master chip. - - The Downstream TX_MSBSWAP from the MRW is a uint8 value. 0x01 means the Downstream bus is wired msb to lsb etc. and - 0x00 means the bus is wired normally, msb to msb, lsb to lsb (lane0 to lane0). - - The Upstream TX_MSBSWAP from the MRW is a uint8 value. 0x01 means the Upstream bus is wired msb to lsb etc. and - 0x00 means the bus is wired normally, msb to msb, lsb to lsb (lane0 to lane0). - - It is up to the platform code to set up each ATTR_EI_BUS_TX_MSBSWAP value for the correct target endpoints. - - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EI_BUS_TX_MSBSWAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_FREQ_OVERRIDE</id> - <description> - FOR LAB USE ONLY: Frequency override of this memory channel in MT/s - comprising of up to three DIMMs. - Set by config file or an attribute writing program. - Consumed by mss_freq. - The default of AUTO means mss_freq will find the best frequencies given the DIMMs plugged in and other rules. - Otherwise, this is the system frequency. - firmware notes: Platforms should initialize this attribute to AUTO (0) - </description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_FREQ_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- mcbist attributes --> -<attribute> - <id>MCBIST_PATTERN</id> - <description>Enables mcbist data pattern selection.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_PATTERN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_TEST_TYPE</id> - <description>Enables mcbist test type selection.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_TEST_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_PRINTING_DISABLE</id> - <description>MCBIST support for printing</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_PRINTING_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_DATA_ENABLE</id> - <description>MCBIST support for enabling data</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_DATA_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_USER_RANK</id> - <description>MCBIST support for rank selection</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_USER_RANK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_USER_BANK</id> - <description>MCBIST support for bank selection</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_USER_BANK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SCHMOO_MULTIPLE_SETUP_CALL</id> - <description>MCBIST for multiple setup</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SCHMOO_MULTIPLE_SETUP_CALL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_ADDR_MODES</id> - <description>Can choose mcbist address mode for full,half or quarter addressing mode.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_ADDR_MODES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_RANK</id> - <description> Defines the rank for the Mcbist </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_RANK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_START_ADDR</id> - <description>Defines the start address for the Mcbist address range</description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_START_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_END_ADDR</id> - <description>Defines the end address for the Mcbist address range</description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_END_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_ERROR_CAPTURE</id> - <description>Enables error capture; basically a flag.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_ERROR_CAPTURE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_MAX_TIMEOUT</id> - <description>Define mcbist Max timeout</description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_MAX_TIMEOUT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_PRINT_PORT</id> - <description>Enable which port prints are required.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_PRINT_PORT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_STOP_ON_ERROR</id> - <description>Flag to stop Mcbist on Error.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_STOP_ON_ERROR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_DATA_SEED</id> - <description>Define data seed for the random data pattern or test</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_DATA_SEED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_ADDR_INTER</id> - <description>The address interleave map with user cases or deafult cases of BANK_RANK,RANK_BANK,BANK_ONLY,RANK_ONLYRANKS_DIMM0,RANKS_DIMM1,USER_PATTERN.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_ADDR_INTER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_ADDR_NUM_ROWS</id> - <description>User defined constraint for limiting number of rows for addressing.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_ADDR_NUM_ROWS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_ADDR_NUM_COLS</id> - <description>User defined constraint for limiting number of columns for addressing.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_ADDR_NUM_COLS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_ADDR_RANK</id> - <description>User defined constraint for limiting number of ranks for addressing.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_ADDR_RANK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_ADDR_BANK</id> - <description>User defined constraint for limiting number of banks for addressing.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_ADDR_BANK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_ADDR_SLAVE_RANK_ON</id> - <description>If slave ranks exists;Restrict usage or enable addressing on them as well.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_ADDR_SLAVE_RANK_ON</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_ADDR_STR_MAP</id> - <description>To Define custom addressing map ; Input by user.</description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_ADDR_STR_MAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_ADDR_RAND</id> - <description>Flag for Addressing to go sequential manner or random.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_ADDR_RAND</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_REFCLOCK_ENABLE</id> - <description>PCIE refclock enable valid mask - PCIE refclock enable valid mask - creator: platform - consumer: p9_pcie_scominit - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_REFCLOCK_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>PROC_PBIEX_ASYNC_SEL</id> - <description>Enumeration indicating which _PBIEX_ASYNC_SEL should be use</description> - <enumerator> - <name>SEL0</name> - <value>0</value> - </enumerator> - <enumerator> - <name>SEL1</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SEL2</name> - <value>2</value> - </enumerator> -</enumerationType> - -<attribute> - <id>PROC_PBIEX_ASYNC_SEL</id> - <description>Selector for ATTR_PROC_EX_FUNC_L3_DELTA_DATA value to be returned by platform. - creator: proc_build_smp - firmware notes: - </description> - <simpleType><uint8_t></uint8_t></simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PBIEX_ASYNC_SEL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_DCM_INSTALLED</id> - <description> - PROC_CHIP Attribute - If true, the chip is installed on a Dual Chip Module - Provided by the Machine Readable Workbook - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_DCM_INSTALLED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<!-- === Attributes supporting erepair_thresholds.xml HWPF Attributes === --> -<attribute> - <id>X_EREPAIR_THRESHOLD_FIELD</id> - <description> - This attribute represents the eRepair threshold value of X-Bus used - in the field. - creator: platform (generated based on MRW data) - See defintion in erepair_thresholds.xml for more information. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_X_EREPAIR_THRESHOLD_FIELD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>A_EREPAIR_THRESHOLD_FIELD</id> - <description> - This attribute represents the eRepair threshold value of A-Bus used - in the field. - creator: platform (generated based on MRW data) - See defintion in erepair_thresholds.xml for more information. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_A_EREPAIR_THRESHOLD_FIELD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DMI_EREPAIR_THRESHOLD_FIELD</id> - <description> - This attribute represents the eRepair threshold value of DMI-Bus used - in the field. - creator: platform (generated based on MRW data) - See defintion in erepair_thresholds.xml for more information. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_DMI_EREPAIR_THRESHOLD_FIELD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>X_EREPAIR_THRESHOLD_MNFG</id> - <description> - This attribute represents the eRepair threshold value of X-Bus used - by Manufacturing. - creator: platform (generated based on MRW data) - See defintion in erepair_thresholds.xml for more information. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_X_EREPAIR_THRESHOLD_MNFG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>A_EREPAIR_THRESHOLD_MNFG</id> - <description> - This attribute represents the eRepair threshold value of A-Bus used - by Manufacturing. - creator: platform (generated based on MRW data) - See defintion in erepair_thresholds.xml for more information. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_A_EREPAIR_THRESHOLD_MNFG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DMI_EREPAIR_THRESHOLD_MNFG</id> - <description> - This attribute represents the eRepair threshold value of DMI-Bus used - by Manufacturing. - creator: platform (generated based on MRW data) - See defintion in erepair_thresholds.xml for more information. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_DMI_EREPAIR_THRESHOLD_MNFG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<!-- ===== End Attributes supporting erepair_thresholds.xml HWPF Attributes ===== --> - -<!-- Mem PLL attributes ===== --> -<attribute> - <id>MEMB_TP_BNDY_PLL_SCAN_SELECT</id> - <description>Scan select for ring image for Centaur tp_bndy_pll ring - creator: platform - firmware notes: - </description> - <simpleType> - <uint32_t> - <default>0x00100008</default> - </uint32_t> - </simpleType> - <readable/> - <persistency>non-volatile</persistency> - <hwpfToHbAttrMap> - <id>ATTR_MEMB_TP_BNDY_PLL_SCAN_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA</id> - <description>Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_mba</description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> - <description>Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_chip</description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>MSS_MRW_THERMAL_MEMORY_POWER_LIMIT</id> - <description> - Machine Readable Workbook Thermal Memory Power Limit - Used to calculate throttles to be at or under the power limit - Per DIMM basis - Consumers: eff_config_thermal and bulk_pwr_throttles - </description> - <simpleType> - <uint64_t> - <default>0xffffe000000006a4,0,0,0,0,0,0,0,0,0</default> - </uint64_t> - <array>10</array> - </simpleType> + <attribute> + <description>Attribute to test signed attribute + functionality in the system</description> + <id>TEST_NEGATIVE_FCN</id> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_LPASR</id> - <description> - Low Power Auto Self-Refresh. - This is for DDR4 MRS2. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_LPASR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_MPR_PAGE</id> - <description> - MPR Page Selection This is for DDR4 MRS3. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_MPR_PAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_GEARDOWN_MODE</id> - <description> - Gear Down Mode. - This is for DDR4 MRS3. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_GEARDOWN_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_PER_DRAM_ACCESS</id> - <description> - Per DRAM accessibility. - This is for DDR4 MRS3. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none</description> + <readable></readable> <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_PER_DRAM_ACCESS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_TEMP_READOUT</id> - <description> - Temperature sensor readout. - This is for DDR4 MRS3. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_TEMP_READOUT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_FINE_REFRESH_MODE</id> - <description>Fine refresh mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_FINE_REFRESH_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CRC_WR_LATENCY</id> - <description> - write latency for CRC and DM. This is for DDR4 MRS3. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CRC_WR_LATENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_MPR_RD_FORMAT</id> - <description> - MPR READ FORMAT. - This is for DDR4 MRS3. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_MPR_RD_FORMAT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_MAX_POWERDOWN_MODE</id> - <description> - Max Power down mode. - This is for DDR4 MRS4. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_MAX_POWERDOWN_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_TEMP_REF_RANGE</id> - <description>Temp ref range. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none</description> - <simpleType> - <uint8_t></uint8_t> + <int8_t> + <default>-6</default> + </int8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_TEMP_REF_RANGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_TEMP_REF_MODE</id> - <description> - Temp controlled ref mode. This is for DDR4 MRS4. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_TEMP_REF_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>EFF_TEMP_REFRESH_MODE</id> - <description> - Temp controlled ref mode. This is for DDR4 MRS4. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_TEMP_REFRESH_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_INT_VREF_MON</id> - <description> - Internal Vref Monitor. - This is for DDR4 MRS4. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_INT_VREF_MON</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_INTERNAL_VREF_MONITOR</id> - <description> - Internal Vref Monitor. - This is for DDR4 MRS4. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_INTERNAL_VREF_MONITOR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CS_CMD_LATENCY</id> - <description> - CS to CMD/ADDR Latency. - This is for DDR4 MRS4. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CS_CMD_LATENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_SELF_REF_ABORT</id> - <description> - Self Refresh Abort. - This is for DDR4 MRS4. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_SELF_REF_ABORT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_RD_PREAMBLE_TRAIN</id> - <description> - Read Pre amble Training Mode. This is for DDR4 MRS4. - Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_RD_PREAMBLE_TRAIN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_RD_PREAMBLE</id> - <description> - Read Pre amble. This is for DDR4 MRS4. - Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_RD_PREAMBLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_WR_PREAMBLE</id> - <description> - Write Pre amble. This is for DDR4 MRS4. - Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_WR_PREAMBLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CA_PARITY_LATENCY</id> - <description> - C/A Parity Latency Mode. This is for DDR4 MRS5. - Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CA_PARITY_LATENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CRC_ERROR_CLEAR</id> - <description> - CRC Error Clear. - This is for DDR4 MRS5. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CRC_ERROR_CLEAR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CA_PARITY_ERROR_STATUS</id> - <description> - C/A Parity Error Status. This is for DDR4 MRS5. - Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CA_PARITY_ERROR_STATUS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_ODT_INPUT_BUFF</id> - <description> - ODT Input Buffer during power down. This is for DDR4 MRS5. - Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_ODT_INPUT_BUFF</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CA_PARITY</id> - <description> - CA Parity Persistance Error. This is for DDR4 MRS5. - Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CA_PARITY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DATA_MASK</id> - <description> - Data Mask. This is for DDR4 MRS5. - Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DATA_MASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_WRITE_DBI</id> - <description> - Write DBI. This is for DDR4 MRS5. - Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_WRITE_DBI</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_READ_DBI</id> - <description> - Read DBI. This is for DDR4 MRS5. - Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_READ_DBI</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_VREF_DQ_TRAIN_VALUE</id> - <description> - vrefdq_train value. This is for DDR4 MRS6. - Computed in mss_eff_cnfg. Each memory channel will have a value. - Creator: mss_eff_cnfg - Consumer:various - Firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_VREF_DQ_TRAIN_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VREF_DQ_TRAIN_VALUE</id> - <description> - vrefdq_train value. This is for DDR4 MRS6. - Computed in mss_eff_cnfg. Each memory channel will have a value. - Creator: mss_eff_cnfg - Consumer:various - Firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_VREF_DQ_TRAIN_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>EFF_VREF_DQ_TRAIN_RANGE</id> - <description> - vrefdq_train range. This is for DDR4 MRS6. - Computed in mss_eff_cnfg. Each memory channel will have a value. - Creator: mss_eff_cnfg - Consumer:various - Firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_VREF_DQ_TRAIN_RANGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VREF_DQ_TRAIN_RANGE</id> - <description> - vrefdq_train range. This is for DDR4 MRS6. - Computed in mss_eff_cnfg. Each memory channel will have a value. - Creator: mss_eff_cnfg - Consumer:various - Firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_VREF_DQ_TRAIN_RANGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_VREF_DQ_TRAIN_ENABLE</id> - <description> - vrefdq_train enable. This is for DDR4 MRS6. - Computed in mss_eff_cnfg. Each memory channel will have a value. - Creator: mss_eff_cnfg - Consumer:various - Firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_VREF_DQ_TRAIN_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VREF_DQ_TRAIN_ENABLE</id> - <description> - vrefdq_train enable. This is for DDR4 MRS6. - Computed in mss_eff_cnfg. Each memory channel will have a value. - Creator: mss_eff_cnfg - Consumer:various - Firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_VREF_DQ_TRAIN_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>TCCD_L</id> - <description>tccd_l. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_TCCD_L</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_WRITE_CRC</id> - <description> - Write CRC control for DDR4 in MRS2. - Set in mss_eff_cnfg. - Each memory channel will have a value. - Creator: mss_eff_cnfg - Consumer:various - Firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_WRITE_CRC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_2N_MODE_ENABLED</id> - <description>Describes if this MBA is in 2N address mode. The DIMM attributes associated with this MBA describes if this mode is needed for SI. The MR Keyword of the VPD gives and indication of the value needed. Set by eff_config and consumed in the mba_def.initfile.</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_2N_MODE_ENABLED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_DIMM_POWER_TEST_REV</id> - <description>The power test revision number that is saved when data is saved on an ISDIMM. If the power test changes, then a difference indicates that the power test needs to be rerun. This attribute needs to stick around between IPLs</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DIMM_POWER_TEST_REV</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>FRU_ID</id> + <attribute> <description>FRU ID attribute used to report FRU information to the BMC for each fru in the system.</description> - <simpleType><uint32_t><default>0</default></uint32_t></simpleType> + <global></global> + <id>FRU_ID</id> <persistency>non-volatile</persistency> - <readable/> - <global/> -</attribute> + <readable></readable> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + </attribute> -<attribute> - <id>BMC_FRU_ID</id> + <attribute> <description>BMC FRU ID attribute to report the system firmware levels to the BMC.</description> - <simpleType><uint32_t><default>0</default></uint32_t></simpleType> + <id>BMC_FRU_ID</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + <simpleType> + <uint32_t> + <default>0</default> + </uint32_t> + </simpleType> + </attribute> -<attribute> - <id>CENTAUR_ECID_FRU_ID</id> + <attribute> <description>FRU ID attribute for centaur ECID data. This fru ID is used to report the ECID data to the BMC and make it available for systems which have then centaur chips soldered to the backplane.</description> - <simpleType><uint32_t></uint32_t></simpleType> + <id>CENTAUR_ECID_FRU_ID</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + </attribute> -<attribute> - <id>PLCK_IPL_ATTR_OVERRIDES_EXIST</id> + <attribute> <description> Set to 1 by HWSV to indicate that attribute overrides exist in a PLCK IPL (not an IPL by steps). This is read by Hostboot to determine if it needs to request the attribute overrides from HWSV before starting its IPL. </description> - <simpleType><uint8_t><default>0x00</default></uint8_t></simpleType> + <id>PLCK_IPL_ATTR_OVERRIDES_EXIST</id> <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>DUMMY_PERSISTENCY</id> - <description>Cached value to test persistency</description> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t> + <default>0x00</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_DUMMY_PERSISTENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>IS_INTER_ENCLOSURE_BUS</id> + <attribute> <description>Indicate an inter-enclosure bus at this endpoint target. 0 = No, 1 = Yes </description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - </simpleType> + <id>IS_INTER_ENCLOSURE_BUS</id> <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>PEER_PATH</id> - <description>Entity path of the peer target of an Abus - </description> - <nativeType> - <name>EntityPath</name> - </nativeType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>PROC_OCC_SANDBOX_SIZE</id> - <description> The amount of memory a user can reserve to store OCC sandbox - functions. - Used by p9_mss_eff_grouping. - </description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_OCC_SANDBOX_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_OCC_SANDBOX_BASE_ADDR</id> - <description>OCC sandbox base address allocated - </description> - <simpleType><uint64_t></uint64_t></simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_OCC_SANDBOX_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MEM_MIRROR_PLACEMENT_POLICY</id> - <description>Define placement policy/scheme for non-mirrored/mirrored memory - layout - creator: platform - consumer: opt_memmap - firmware notes: - NORMAL = non-mirrored start: 0, mirrored start: 512TB - FLIPPED = mirrored start: 0, non-mirrored start: 512TB - SELECTIVE = non-mirrored/mirrored start (interleaved): 0 - DRAWER = non-mirrored start: 1TB*drawer, mirrored start: 512TB+(1TB*drawer/2) - </description> + <readable></readable> <simpleType> <uint8_t> - <!-- Normal --> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MEM_MIRROR_PLACEMENT_POLICY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_AS_MMIO_BAR_BASE_ADDR</id> - <description>AS MMIO BAR base address value - creator: platform - consumer: proc_setup_bars - firmware notes: - 64-bit address representing BAR RA - NOTE: BAR register covers RA 14:51 - </description> - <simpleType> - <uint64_t> - <default>0</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_AS_MMIO_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_AS_MMIO_BAR_ENABLE</id> - <description>AS MMIO BAR enable - creator: platform - consumer: proc_setup_bars - firmware notes: none - </description> - <simpleType> - <uint8_t> - <!-- Disabled --> - <default>0</default> + <default>0</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_AS_MMIO_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_AS_MMIO_BAR_SIZE</id> - <description>AS MMIO BAR size value - creator: platform - consumer: proc_setup_bars - firmware notes: none - </description> - <simpleType> - <uint64_t> - <!-- 2_MB --> - <default>0x0000000000200000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_AS_MMIO_BAR_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>RISK_LEVEL</id> - <description> - HWP/Init "risk level" enabled. Used by HB to pass to HB driven HWPs. - FALSE = 0x0,TRUE = 0x1 - Override Attribute - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_RISK_LEVEL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_FREQ_BIAS_PERCENTAGE</id> - <description> - Percentage to increase/decrease MEM frequency. two's complement number. - Measured in 100's. So the value of 100 is one percent increase. - This frequency change comes from changing multipliers and dividers to - get the desired frequency. The supported frequencies come from - Tim Diemoz. - Creator: platform set this to 0. Users can set this to a valid value. - VALID Values: (TBD % to TBD %) (Tuleta) (TBD % to TBD %) (Glacier) - Set by: PLL settings written by Dave Cadigan - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_FREQ_BIAS_PERCENTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MRW_MEM_SENSOR_CACHE_ADDR_MAP</id> - <description>Machine Readable Workbook value detailing the wiring of the - 8 dimm temperature sensors for non custom dimms, in DIMM A0, - A1,B0,B1,C0,C1,D0,D1 order. One nibble per sensor where - bit0 (MSB) is the i2c bus the sensor is attached to - (0 for master, 1 for spare) and bits 1:3 are for A2,A1,A0 - of the sensor i2c address (where A2 is MSB) + <attribute> + <description>Entity path of the peer target of an Abus </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> + <id>PEER_PATH</id> + <nativeType> + <name>EntityPath</name> + </nativeType> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <readable></readable> <no_export/> -</attribute> - -<attribute> - <id>CDIMM_SENSOR_MAP_PRIMARY</id> - <description> - Custom DIMM Sensor Map for Primary I2C Port (1 byte of data): - 0x00 No sensors attached - 0x01 DIMM sensor 0 attached - 0x02 DIMM sensor 1 attached - 0x04 DIMM sensor 2 attached - 0x08 DIMM sensor 3 attached - 0x10 DIMM sensor 4 attached - 0x20 DIMM sensor 5 attached - 0x40 DIMM sensor 6 attached - 0x80 DIMM sensor 7 attached - Comes from the VPD MW Keyword - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CDIMM_SENSOR_MAP_PRIMARY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CDIMM_SENSOR_MAP_SECONDARY</id> - <description> - Custom DIMM Sensor Map for Secondary I2C Port (1 byte of data): - 0x00 No sensors attached - 0x01 DIMM sensor 0 attached - 0x02 DIMM sensor 1 attached - 0x04 DIMM sensor 2 attached - 0x08 DIMM sensor 3 attached - 0x10 DIMM sensor 4 attached - 0x20 DIMM sensor 5 attached - 0x40 DIMM sensor 6 attached - 0x80 DIMM sensor 7 attached - Comes from the VPD MW Keyword - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CDIMM_SENSOR_MAP_SECONDARY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_ADDRESS_MIRRORING</id> - <description> - Address mirroring on the DIMM by rank, up to 4 ranks. - 0x08 means rank 0 is mirrored - 0x04 means rank 1 is mirrored - 0x02 means rank 2 is mirrored - 0x01 means rank 3 is mirrored - Comes from EFF config reading the VPD_DRAM_ADDRESS_MIRRORING from the - AM keyword of the VPD. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_ADDRESS_MIRRORING</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_BLUEWATERFALL_BROKEN</id> - <description> - Set by the platform depending on DD1.0X vs DD1.03 or newer. If true, - then draminit_train will modify dqs_clk_ps and gate to work around the - issue. Set in get ecid which determines if we are at 1.03 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_BLUEWATERFALL_BROKEN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>CDM_POLICIES</id> + <attribute> <description> Cec Degraded Mode Policy flags Use the CDM_POLICIES enum to decode. If the appropriate bit is 1 then the policy mode is enabled, and those type of Guard records are disabled. </description> + <id>CDM_POLICIES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - <default>0x00</default> - </uint8_t> + <uint8_t> + <default>0x00</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <writeable/> - <readable/> -</attribute> - -<enumerationType> - <id>CDM_POLICIES</id> - <description>Enumeration of CDM_POLICIES flags</description> - <enumerator> - <description> - MFG_Guard policy: - Used in MFG only to prevent and disable the following: - . Storing or creation of new Guard records from Diagno`stic or other - faults through error logs. This is all domains, CEC - processor/memory, VPD, FSP, etc. - . Storing or creation of Manual Guard record from user. - NOTE: this does not stop FCO. - . Using an already stored System or Manual Guard record from - deconfiguring resources. This is all domains, CEC - processor/memory, VPD, FSP, etc. - </description> - <name>MANUFACTURING_DISABLED</name> - <value>0x01</value> - </enumerator> - <enumerator> - <description> - Predictive_Guard policy: - Used in Field or development to prevent and disable the following: - . Storing or creation of new Guard records from diagnostics or other - faults through error logs with the error_type of Predictive. - . Using an already stored System Guard record with error_type of - Predictive from deconfiguring resources. - </description> - <name>PREDICTIVE_DISABLED</name> - <value>0x02</value> - </enumerator> -</enumerationType> + <writeable></writeable> + </attribute> -<attribute> - <id>FIELD_CORE_OVERRIDE</id> + <attribute> <description>Field Core Override (FCO) is the override value for the number of functional cores allowed on the system. FCO is used when customers order a system with N cores but they only want @@ -14683,33 +2542,33 @@ Measured in GB</description> to error. A value of 0 means all cores allowed; </description> + <id>FIELD_CORE_OVERRIDE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>HOSTSVC_PLID</id> + <attribute> <description> Value of the next PLID that host service should send </description> + <id>HOSTSVC_PLID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0x89000000</default> - </uint32_t> + <uint32_t> + <default>0x89000000</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>RUN_MAX_MEM_PATTERNS</id> + <attribute> <description> Policy indicating whether to perform the maximum amount of memory pattern testing possible or not. @@ -14717,2520 +2576,645 @@ Measured in GB</description> possible. Set to 0x00 to perform the default amount of memory pattern testing. </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <id>RUN_MAX_MEM_PATTERNS</id> <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>EFF_RLO</id> - <description>Gives the RLO value to use for this port. This comes from the MR Keyword of the VPD gives and indication of the value. It will be writable until it comes from VPD. The value is a positive integer number.</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_RLO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_WLO</id> - <description>Read Latency Offset value that is used in the phy. This value comes from the MR keyword of the VPD</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_WLO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_GPO</id> - <description>Global Phy Offset value that is used in setting up the phy. This value comes from the MR keyword of the VPD</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_GPO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CKE_PRI_MAP</id> - <description>Contains the CKE MAP for the DIMM being plugged in. It comes from the MT keyword but is not on a port basis --- meaning this Attribute may be split: with 16 bits associated with port A data and 16 bits with B. This value goes directly into the MBA01 Rank-to-primary-CKE mapping table register bits 0:31 (MBA01_MBAREF1Q) register. This attribute is writeable until it comes from the VPD</description> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CKE_PRI_MAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_CKE_PWR_MAP</id> - <description>Contains the CKE Power Domain mapping tables for the DIMM being plugged in. It comes from the MT keyword but is not on a port basis --- meaning this Attribute may be split: with 32 bits associated with port A data and 32 bits with B. This value goes directly into the MBA01 Rank-to-CKE power domain mapping table bits 0:33 (MBA01_MBARPC1Q) register. This attribute is writeable until it comes from the VPD</description> - <simpleType> - <uint64_t> - <default>0</default> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_CKE_PWR_MAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_RDTAG</id> - <description>Read Tag value that is used in setting up the phy. It is expected that this value will come from the VPD</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_RDTAG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_TSYS_ADR</id> - <description>TSYS for all address blocks in the MBA pair. This value comes from the MR keyword of the VPD</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_TSYS_ADR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_TSYS_DP18</id> - <description>TSYS for all DP18 blocks in the MBA pair. This value comes from the MR keyword of the VPD</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_TSYS_DP18</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DQ_WR_OFFSET</id> - <description>DQ write offset value that is used in setting up the phy's phase rotators before WR_LVL, 0x40 is HW Default. It is expected that this value will come from the VPD</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DQ_WR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_BUFFER_LATENCY</id> - <description> - Additional buffer latency in the case of RDIMMs and LRDIMMs. - It is expected that this value will come from the VPD - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_BUFFER_LATENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>LRDIMM_MR12_REG</id> - <description> - LRDIMM MR1,2 register. - DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks. - Eff config should set this up. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_LRDIMM_MR12_REG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>LRDIMM_ADDITIONAL_CNTL_WORDS</id> - <description> - LRDIMM additional RCD control words as set by DIMM SPD: - F[3,4]RC0A, F[3,4]RC0B, F[5,6]RC0A, F[5,6]RC0B, F[7,8]RC0A, F[7,8]RC0B, F[9,10]RC0A, F[9,10]RC0B, - F[1]RC8, F[3]RC9, F[3]RC8, F[1]RC0B, F[1]RC0C, F[1]RC0D, F[1]RC0E, F[1]RC0F. - Eff config should set this up - </description> - <simpleType> - <uint64_t> - </uint64_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>LRDIMM_RANK_MULT_MODE</id> - <description> - LRDIMM rank multiplication mode. - Will be set at an MBA level with one policy to be used - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_LRDIMM_RANK_MULT_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SPWUP_IGNORE_XSTOP_FLAG</id> - <description>Flag storage to have the Special Wakeup procedure ignore a checkstop condition.</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CPM_INFLECTION_POINTS</id> - <description>Structure to communicate the CPM inflection points from the CPM code to the Pstate code - Datablock consisting of: - 8 Inflection Point frequency entries (binary in ATTR_FREQ_PROC_REFCLOCK_KHZ / ATTR_PROC_DPLL_DIVIDER units) - 1 ValidRanges entry - the number of valid inflection points in the previous locations (unit origin) - 1 pMax frequency entry - the maximum allowed boosted frequency (binary in ATTR_FREQ_PROC_REFCLOCK_KHZ / ATTR_DPLL_DIVIDER units) - 6 spare entries - Producer: p8_cpm_cal_load - Consumer: p8_pstate_datablock - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - <array>16</array> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CPM_INFLECTION_POINTS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>LAB_USE_JTAG_MODE</id> - <description>This attribute controls how the procedures operate in JTAG mode under an environment called cronus flex. For normal operation, this attribute should be set to FALSE. Platforms should initialize this attribute to FALSE.</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <attribute> + <description>Type of Master, ACTING_MASTER or MASTER_CANDIDATE or + NOT_MASTER</description> + <hasStringConversion></hasStringConversion> + <id>PROC_MASTER_TYPE</id> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_LAB_USE_JTAG_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_CONTROL_SWITCH</id> - <description>This attribute enables control switches in the memory code. This is a one hot vector: Bit 7 controls the Bad Bit Mask function in draminit_training. The platform should initialize this to BBM_ON except if ATTR_LAB_USE_JTAG_MODE == TRUE, then the platform should set this attribute to BBM_ OFF.</description> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_CONTROL_SWITCH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- -<attribute> - <id>MSS_DRAM_ACTIVATE_POWER_PERCENT</id> - <description>DRAM Activation power percentage to determine the ras and cas weights for throttle controls - will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on the left(big endian)) - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DRAM_ACTIVATE_POWER_PERCENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> ---> - -<attribute> - <id>MSS_THROTTLE_CONTROL_RAS_WEIGHT</id> - <description> - RAS weight to use for memory throttle control - - set in thermal procedures - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_THROTTLE_CONTROL_CAS_WEIGHT</id> - <description> - CAS weight to use for memory throttle control - - set in thermal procedures - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_MIRROR_BASES_ACK</id> - <description>Mirrored memory base addresses - creator: mss_setup_bars - consumer: consumer: opt_mem_map - Mem opt map uses this for the bases of the mirror ranges. - (max number based on Venice design) - </description> - <simpleType> - <uint64_t></uint64_t> - <array>4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_MIRROR_BASES_ACK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_MIRROR_SIZES_ACK</id> - <description>Size of mirrored memory region up to a power of 2 - creator: mss_setup_bars - consumer: opt_mem_map - Mem opt map uses this to stack mirror ranges. The real amount of memory behind the mirror group maybe less than the number reported here if there are memory holes - </description> - <simpleType> - <uint64_t></uint64_t> - <array>4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_MIRROR_SIZES_ACK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_MEM_BASES_ACK</id> - <description>Non-mirrored memory base addresses - creator: mss_setup_bars - consumer: opt_mem_map - Mem opt map uses this for the bases of the non-mirror ranges. - (max number based on Venice design) - </description> - <simpleType> - <uint64_t></uint64_t> - <array>8</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_MEM_BASES_ACK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_MEM_SIZES_ACK</id> - <description>Size of non-mirrored memory regions up to a power of 2 - creator: mss_setup_bars - consumer: opt_mem_map - Mem opt map uses this to stack mirror ranges. The real amount of memory behind the mirror group maybe less than the number reported here if there are memory holes - </description> - <simpleType> - <uint64_t></uint64_t> - <array>8</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_MEM_SIZES_ACK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_RANDOM_SEED_VALUE</id> - <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint8_t> + <default>NOT_MASTER</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_RANDOM_SEED_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + <no_export/> + </attribute> -<attribute> - <id>MCBIST_RANDOM_SEED_TYPE</id> - <description>Controls the MCBIST engine in the centaur chip. The value will be set in mss_eff_config_shmoo.</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <attribute> + <description>MBA DRAM data bus utilization percent to use to determine cfg_nm_n_per_mba</description> + <id>MSS_DATABUS_UTIL_PER_MBA</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_RANDOM_SEED_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_BOOT_VOLTAGE_VID</id><!-- deprecated --> - <description> - Proc Boot Voltage - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_BOOT_VOLTAGE_VID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DISABLE_I2C_ACCESS</id> - <description> - Set to skip physical access to i2c interface in SBE execution. - Consumed by SBE hooks to permit skipping of selected code when - running on a test platform (i.e., wafer) which does not have a physical - SEEPROM connected. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_DISABLE_I2C_ACCESS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_REFCLOCK_RCVR_TERM</id> - <description> - Defines system specific value of processor refclock receiver termination (FSI GP4 bits 8:9) - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_REFCLOCK_RCVR_TERM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PCI_REFCLOCK_RCVR_TERM</id> - <description> - Defines system specific value of PCI refclock receiver termination (FSI GP4 bits 10:11) - </description> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PCI_REFCLOCK_RCVR_TERM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DD1_SLOW_PCI_REF_CLOCK</id> - <description> - Valid only for Nimbus DD1 - If set (=1), run the PCI Ref clock at 94MHz in order to enable - experimental GEN4 support. - If not set (=0), run the PCI Ref clock at 100MHz - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/><!-- SBE requirement only --> - <hwpfToHbAttrMap> - <id>ATTR_DD1_SLOW_PCI_REF_CLOCK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MEMB_DMI_REFCLOCK_RCVR_TERM</id> + <attribute> <description> - Defines system specific value of DMI refclock receiver termination (FSI GP4 bits 8:9) + Holds the effective EC of the system. Effective EC is the lowest EC + among all the functional procs in the system. Some cards may "downbin" + the effective ECs of their contained processors, which could lower the + effective EC of the system beyond what would occur when considering + processor ECs alone </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <id>EFFECTIVE_EC</id> <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MEMB_DMI_REFCLOCK_RCVR_TERM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MEMB_DDR_REFCLOCK_RCVR_TERM</id> - <description> - Defines system specific value of DDR refclock receiver termination (FSI GP4 bits 10:11) - </description> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t> + <default>0x10</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MEMB_DDR_REFCLOCK_RCVR_TERM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MEM_FILTER_PLL_SOURCE</id> - <description> - Defines source of MEM filter PLL input (FSI GP4 bit 23) - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <attribute> + <description>MRU ID attribute for chip/unit class</description> + <id>MRU_ID</id> <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MEM_FILTER_PLL_SOURCE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MULTI_SCOM_BUFFER_MAX_SIZE</id> - <description>To represent different sizes of Multiscom Buffer. - It can take 11 different values - MULTI_SCOM_BUFFER_SIZE_1KB = 0x0000000000000400, - MULTI_SCOM_BUFFER_SIZE_2KB = 0x0000000000000800, - MULTI_SCOM_BUFFER_SIZE_4KB = 0x0000000000001000, - MULTI_SCOM_BUFFER_SIZE_8KB = 0x0000000000002000, - MULTI_SCOM_BUFFER_SIZE_16KB = 0x0000000000004000, - MULTI_SCOM_BUFFER_SIZE_32KB = 0x0000000000008000, - MULTI_SCOM_BUFFER_SIZE_64KB = 0x0000000000010000, - MULTI_SCOM_BUFFER_SIZE_128KB = 0x0000000000020000, - MULTI_SCOM_BUFFER_SIZE_256KB = 0x0000000000040000, - MULTI_SCOM_BUFFER_SIZE_512KB = 0x0000000000080000, - MULTI_SCOM_BUFFER_SIZE_1MB = 0x0000000000100000 - </description> + <readable></readable> <simpleType> - <uint64_t> - <default>0x0000000000001000</default> - </uint64_t> + <uint32_t> + <default>0x00</default> + </uint32_t> </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MULTI_SCOM_BUFFER_MAX_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>MULTI_SCOM_BUFFER_MAX_SIZE_BIT</id> - <description>Enumeration indicating the multi scome - buffer size. The values can be combined using a - bitwise 'OR'. The values will need to be kept - in sync with the FAPI enumerator values. Also - the enumeration type is used by the - ATTR_MULTI_SCOM_BUFFER_MAX_SIZE. Should - note that the MULTI_SCOM_BUFFER_MAX_SIZE values - are of type uint32_t - </description> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_1KB</name> - <value>0x00000400</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_2KB</name> - <value>0x00000800</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_4KB</name> - <value>0x00001000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_8KB</name> - <value>0x00002000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_16KB</name> - <value>0x00004000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_32KB</name> - <value>0x00008000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_64KB</name> - <value>0x00010000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_128KB</name> - <value>0x00020000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_256KB</name> - <value>0x00040000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_512KB</name> - <value>0x00080000</value> - </enumerator> - <enumerator> - <name>MULTI_SCOM_BUFFER_SIZE_1MB</name> - <value>0x00100000</value> - </enumerator> -</enumerationType> + <no_export/> + </attribute> -<attribute> - <id>DMI_DFE_OVERRIDE</id> + <attribute> <description> - Defines where to apply DMI bus DFE override settings for HW244323. + Bitmask indicating what role this chip has in tod topology </description> + <id>TOD_ROLE</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_DMI_DFE_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>CPM_TURBO_BOOST_PERCENT</id> + <attribute> <description> - Percent of Boost Above Turbo for CPMs - (binary in 0.1 percent steps) - - Used in generating extra Pstate tables beyond those that would result from - #V data. - - Producer: DEF file as this is CCIN based - - Consumers: p8_build_gpstate_table.C, p8_cpm_cal_load.C - - Platform default: 0 + The amount of mainstore that PHYP needs to preserve per node + during MPIPL. </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> + <id>HB_RSV_MEM_SIZE_MB</id> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CPM_TURBO_BOOST_PERCENT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_UNDERVOLTING_FRQ_MINIMUM</id> - <description> - Override for Minimum frequency for which undervolting is allowed. - - If value = 0, the value of VPD CPMin data point is passed to OCC FW via - Pstate SuperStructure. - - If value != 0, this value will be passed to OCC FW via Pstate SuperStructure - as the floor frequency for enabled CPMs. - - Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. - - Consumer: OCC FW; OCC Lab Tools - - Provided by the Machine Readable Workbook. - </description> + <readable></readable> <simpleType> - <uint8_t></uint8_t> + <uint32_t> + <default>256</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_UNDERVOLTING_FRQ_MINIMUM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>PM_UNDERVOLTING_FREQ_MAXIMUM</id> + <attribute> <description> - Override for Maximum frequency for which undervolting is allowed. - - If value = 0, the value of VPD Turbo data point is passed to OCC FW via - Pstate SuperStructure. - - If value != 0, this value will be passed to OCC FW via Pstate SuperStructure - as the ceiling frequency for enabled CPMs. - - Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. - - Consumer: OCC FW; OCC Lab Tools - - Provided by the Machine Readable Workbook. + Indicates if system should consider abus logic when deconfiguring in + _deconfigureAssocProc(), will be overwritten on multi-node system </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> + <id>DO_ABUS_DECONFIG</id> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_UNDERVOLTING_FREQ_MAXIMUM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_WINKLE_ENTRY</id> - <description>Setting depends on di/dt charateristics of the system. - - Set Assisted if power off serialization is needed and WINKLE_TYPE=Fast; - Set to Hardware if the system can handle the unrelated powering off between cores. - Hardware setting decreases entry latency - - Producer: MRWB - - Consumer: p8_poreslw_init.C - </description> + <readable></readable> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + <default>1</default> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_WINKLE_ENTRY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_WINKLE_EXIT</id> - <description>Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_WINKLE_TYPE. - - Set to Assisted if power on serialization is needed and WINKLE_TYPE=Fast; Set to Hardware if the system - can handle the unrelated powering off between cores. Hardware setting decreases entry latency. - Must be set to Assisted if ATTR_PM_WINKLE_TYPE=Deep as this necessary for restore. - - Setting to Hardware is a test mode for Fast only. - - Producer: MRWB + </attribute> - Consumer: p8_poreslw_init.C - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> + <attribute> + <description>Memory AVDD voltage domain offset in mV.</description> <hwpfToHbAttrMap> - <id>ATTR_PM_WINKLE_EXIT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>PROC_MASTER_TYPE</id> - <description> - Enumeration indicating the role of proc as master/alt_master/not_master - </description> - <enumerator> - <name>ACTING_MASTER</name> - <value>0</value> - </enumerator> - <enumerator> - <name>MASTER_CANDIDATE</name> - <value>1</value> - </enumerator> - <enumerator> - <name>NOT_MASTER</name> - <value>2</value> - </enumerator> - <default>NOT_MASTER</default> -</enumerationType> - -<attribute> - <id>PROC_MASTER_TYPE</id> - <description>Type of Master, ACTING_MASTER or MASTER_CANDIDATE or - NOT_MASTER</description> - <simpleType> - <uint8_t> - <default>NOT_MASTER</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <hasStringConversion/> - <readable/> - <writeable/> - <no_export/> -</attribute> - -<attribute> - <id>MSS_DATABUS_UTIL_PER_MBA</id> - <description>MBA DRAM data bus utilization percent to use to determine cfg_nm_n_per_mba</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>MSS_DATABUS_UTIL</id> - <description> - DRAM data bus utilization percent to use to determine ATTR_MSS_THROTTLED_N_COMMANDS - creator: f/w - consumer: mss_utils_to_throttle - </description> - <simpleType> - <uint32_t></uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DATABUS_UTIL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_THROTTLED_N_COMMANDS</id> - <description> - Throttled N commands (address operations) that are - allowed within a window of M DRAM clocks. - Nimbus workbook (Power and Thermal Controls). - creator: mss_utils_to_throttle - </description> - <simpleType> - <uint32_t></uint32_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_THROTTLED_N_COMMANDS</id> + <id>ATTR_MSS_AVDD_OFFSET</id> <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_MAC</id> - <description> - Maximum Activate Count. Used in various locations and is computed in mss_eff_cnfg. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint16_t></uint16_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_MAC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_MODULE_BUS_WIDTH</id> - <description> - Module Memory Bus Width. - Used in various locations and is evaluated in mss_eff_cnfg. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_MODULE_BUS_WIDTH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - - - -<attribute> - <id>MSS_UTIL_N_PER_MBA</id> - <description>cfg_nm_n_per_mba throttle N value that was calculated from MSS_DATABUS_UTIL_PER_MBA</description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_UTIL_N_PER_MBA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFFECTIVE_EC</id> - <description> - Holds the effective EC of the system. Effective EC is the lowest EC - among all the functional procs in the system. Some cards may "downbin" - the effective ECs of their contained processors, which could lower the - effective EC of the system beyond what would occur when considering - processor ECs alone - </description> - <simpleType> - <uint8_t> - <default>0x10</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>PROC_PBA_UNTRUSTED_BAR_BASE_ADDR</id> - <description>PBA Untrusted BAR base address (secure mode) - creator: platform - firmware notes: - 64-bit address representing BAR RA - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PBA_UNTRUSTED_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PBA_UNTRUSTED_BAR_SIZE</id> - <description>PBA Untrusted BAR size (secure mode) - creator: platform - firmware notes: - mask applied to RA 23:43 - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PBA_UNTRUSTED_BAR_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<attribute> - <id>MRU_ID</id> - <description>MRU ID attribute for chip/unit class</description> - <simpleType> - <uint32_t> - <default>0x00</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>MSS_INIT_STATE</id> - <description>How far into the ipl istep the centaur has been brought up</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_INIT_STATE</id> - <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id> - <description>Machine Readable Workbook DIMM power curve percent uplift for this system</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE</id> - <description> - Machine Readable Workbook DIMM power - curve percent uplife idle for this system - </description> + <id>MEM_AVDD_OFFSET_MILLIVOLTS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint8_t> + <uint32_t> <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MRW_MEM_THROTTLE_DENOMINATOR</id> - <description>Machine Readable Workbook throttle value for denominator cfg_nm_m</description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MRW_MEM_THROTTLE_DENOMINATOR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_MAX_DRAM_DATABUS_UTIL</id> - <description>Machine Readable Workbook value for maximum dram data bus utilization in centi percent (c%). Used to determine memory throttle values.</description> - <simpleType> - <uint32_t> - <default>0x00002328</default> - </uint32_t> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>RECONFIGURE_LOOP</id> - <description> - Used to inidicate if a reconfigure loop is needed. - Hostboot clears and sets this during istep dispatching. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> + <attribute> + <description> System attribute array that defines the reconfig loop test cases + consumer: istep dispatcher reconfigLoopTestRunner function + This array is loaded with data via attribute override. The attribute is + then read and then overlayed onto a test case structure. + </description> + <id>RECONFIG_LOOP_TESTS</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_RECONFIGURE_LOOP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>RECONFIGURE_LOOP</id> - <description>Enumeration of RECONFIGURE_LOOP flags</description> - <!-- add enumerators (single bits) for anything that needs a reconfigure loop --> - <enumerator> - <description> - Indicates HW has been deconfigured - </description> - <name>DECONFIGURE</name> - <value>0x01</value> - </enumerator> - <enumerator> - <description> - Indicates a bad DQ bit was set in the BadDqBitmap - </description> - <name>BAD_DQ_BIT_SET</name> - <value>0x02</value> - </enumerator> - <enumerator> - <description> - An RCD parity error has been detected - </description> - <name>RCD_PARITY_ERROR</name> - <value>0x04</value> - </enumerator> -</enumerationType> - -<attribute> - <id>PM_SYSTEM_IVRM_VPD_MIN_LEVEL</id> - <description>Version level of #M that represents the minimum for IVRM characterized parts. - If this value is non-zero and the #M version level is less than this value, IVRMs are disabled. - If the #M version is greater than or equal to this value, the IVRMs are allowed to be enable from a level of part perspective. - Producer: MRWB - Consumer: p8_build_pstate_datablock.C - </description> + <readable></readable> <simpleType> - <uint8_t></uint8_t> + <array>5</array> + <uint64_t></uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SYSTEM_IVRM_VPD_MIN_LEVEL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>PM_SLW_DEEP_WINKLE_EXIT_GOOD_HALT_ADDR</id> + <attribute> <description> - Stores the offset in SLW image of the halt point for a good Deep Winkle Exit transition. - This is value may used by FAPI code to check that the SLW engine achieved an expected state. + Indicates whether reconfigure loop tests are enabled. + This attribute is set via attribute override </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> + <id>RECONFIG_LOOP_TESTS_ENABLE</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SLW_DEEP_WINKLE_EXIT_GOOD_HALT_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SLW_DEEP_SLEEP_EXIT_GOOD_HALT_ADDR</id> - <description> - Stores the offset in SLW image of the halt point for a good Deep Sleep Exit transition. - This is value may used by FAPI code to check that the SLW engine achieved an expected state. - </description> + <readable></readable> <simpleType> - <uint32_t></uint32_t> + <uint8_t></uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SLW_DEEP_SLEEP_EXIT_GOOD_HALT_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_EFF_VPD_VERSION</id> - <description> - The lowest VPD Version of the DIMMs attached to the MBA. Comes directly (in ASCII) of the VINI VZ keyword - </description> - <simpleType> - <uint32_t></uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> + <attribute> + <description>Memory VDD voltage domain offset in mV.</description> <hwpfToHbAttrMap> - <id>ATTR_MSS_EFF_VPD_VERSION</id> - <macro>DIRECT</macro> + <id>ATTR_MSS_VDD_OFFSET</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DISABLE_SCRUB_AFTER_PATTERN_TEST</id> - <description> - 1 = disable scrub after memdiags pattern test. 0 = scrub after memdiags pattern test. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> + <id>MEM_VDD_OFFSET_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_DISABLE_SCRUB_AFTER_PATTERN_TEST</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PCBS_FSM_TRACE_EN</id> - <description> - Overridable attribute to allow for PCBS FSM tracing by Power Management procedures - </description> + <readable></readable> <simpleType> - <uint8_t></uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PCBS_FSM_TRACE_EN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>PM_GLOBAL_FIR_TRACE_EN</id> - <description> - Overridable attribute to allow for Global checkstop and recoverable FIR tracing by Power Management procedures - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> + <attribute> + <description>Memory VCS voltage domain offset in mV.</description> <hwpfToHbAttrMap> - <id>ATTR_PM_GLOBAL_FIR_TRACE_EN</id> - <macro>DIRECT</macro> + <id>ATTR_MSS_VCS_OFFSET</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE</id> - <description>Value of on or off. On is 256 bit interleave. Off, the translation is on 128 bit interleave mode. See centaur workbook chapter 5.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> + <id>MEM_VCS_OFFSET_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MRW_STRICT_MBA_PLUG_RULE_CHECKING</id> - <description> - The MRW for a system should set this to TRUE for systems that must obey plug rules. Lab environments should default this to off and allow the user to override using normal methods to test. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MRW_STRICT_MBA_PLUG_RULE_CHECKING</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT</id> - <description>This dial sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. Valid values are 23 through 32. See Centaur Spec Chapter 5 for details. Used in the intifile </description> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id> - <description>At a system level, this attribute controls if interleaving is required, requested or never. The MRW.</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> + <attribute> + <description>Memory VPP voltage domain offset in mV.</description> <hwpfToHbAttrMap> - <id>ATTR_MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id> - <macro>DIRECT</macro> + <id>ATTR_MSS_VPP_OFFSET</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_HWP_ATTR_VERSION</id> - <description>Defines HWP version to be checked inside HWPs to determine if new code should be loaded/skipped/modified/etc.</description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> + <id>MEM_VPP_OFFSET_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_HWP_ATTR_VERSION</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>REDUNDANT_CLOCKS</id> - <description> - 1 = System has redundant clock oscillators - 0 = System does not have redundant clock oscillators - From the Machine Readable Workbook - </description> + <readable></readable> <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_REDUNDANT_CLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_NEST_CAPABLE_FREQUENCIES</id> - <description> - The NEST frequencies the memory chip can run at computed by the mss_freq. - The possibilities are ORed together. The platform uses these value and - the MRW to determine what frequency to boot the fabric (nest) if it can. - There are two values: 8G and 9.6G - </description> - <simpleType> - <uint64_t> - </uint64_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_NEST_CAPABLE_FREQUENCIES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MRW_HW_MIRRORING_ENABLE</id> - <description> - 0 : HW mirroring is disabled. - 1 : HW mirroring is enabled. - Provided by the MRW. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> + <attribute> + <description>Memory VDDR voltage domain offset in mV.</description> <hwpfToHbAttrMap> - <id>ATTR_MRW_HW_MIRRORING_ENABLE</id> - <macro>DIRECT</macro> + <id>ATTR_MSS_VDDR_OFFSET</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>TOD_ROLE</id> - <description> - Enumeration indicating what role this chip has in tod topology - </description> - <enumerator> - <name>NON_MASTER</name> - <value>0</value> - </enumerator> - <enumerator> - <name>PRIMARY</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SECONDARY</name> - <value>2</value> - </enumerator> - <default>NON_MASTER</default> -</enumerationType> - -<attribute> - <id>TOD_ROLE</id> - <description> - Bitmask indicating what role this chip has in tod topology - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> + <id>MEM_VDDR_OFFSET_MILLIVOLTS</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>MNFG_DMI_MIN_EYE_WIDTH</id> - <description> - System attribute. - 6 bit rx_min_eye_width value for DMI bus interfaces during system - manufacturing; used for both centaur and p8 - creator: platform - firmware notes: Attribute value is in the Machine Readable Workbook - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MNFG_DMI_MIN_EYE_WIDTH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MNFG_DMI_MIN_EYE_HEIGHT</id> - <description> - System attribute. - 8 bit rx_min_eye_height value for DMI bus interfaces during system - manufacturing; used for both centaur and p8 - creator: platform - firmware notes: Attribute value is in the Machine Readable Workbook - </description> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MNFG_DMI_MIN_EYE_HEIGHT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MNFG_ABUS_MIN_EYE_WIDTH</id> - <description> - System attribute - 6 bit rx_min_eye_width value for A bus interfaces during system - manufacturing - creator: platform - firmware notes: Attribute value is in the Machine Readable Workbook + <attribute> + <description>Units: uV/Membuf </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> <hwpfToHbAttrMap> - <id>ATTR_MNFG_ABUS_MIN_EYE_WIDTH</id> - <macro>DIRECT</macro> + <id>ATTR_MSS_AVDD_SLOPE_ACTIVE</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MNFG_ABUS_MIN_EYE_HEIGHT</id> - <description> - System attribute - 8 bit rx_min_eye_height value for A bus interfaces during system - manufacturing - creator: platform - firmware notes: Attribute value is in the Machine Readable Workbook - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> + <id>MSS_CENT_AVDD_SLOPE_ACTIVE</id> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MNFG_ABUS_MIN_EYE_HEIGHT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MNFG_XBUS_MIN_EYE_WIDTH</id> - <description> - System attribute - 6 bit rx_min_eye_width value for X bus interfaces during system - manufacturing - creator: platform - firmware notes: Attribute value is in the Machine Readable Workbook - </description> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MNFG_XBUS_MIN_EYE_WIDTH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>HB_RSV_MEM_SIZE_MB</id> - <description> - The amount of mainstore that PHYP needs to preserve per node - during MPIPL. + <attribute> + <description>Units: uV/Membuf </description> - <simpleType> - <uint32_t> - <default>256</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id> - <description>Used for Custom DIMMs to not enable the reading of the dimm temperature sensor on the master i2c bus</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> <hwpfToHbAttrMap> - <id>ATTR_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE</id> - <description>Used for Custom DIMMs to not enable the reading of the dimm temperature sensor on the spare i2c bus</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE</id> - <macro>DIRECT</macro> + <id>ATTR_MSS_AVDD_SLOPE_INACTIVE</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DO_ABUS_DECONFIG</id> - <description> - Indicates if system should consider abus logic when deconfiguring in - _deconfigureAssocProc(), will be overwritten on multi-node system - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> + <id>MSS_CENT_AVDD_SLOPE_INACTIVE</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MEM_AVDD_OFFSET_MILLIVOLTS</id> - <description>Memory AVDD voltage domain offset in mV.</description> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_AVDD_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<!-- For reconfig loop testing --> -<attribute> - <id>RECONFIG_LOOP_TESTS</id> - <description> System attribute array that defines the reconfig loop test cases - consumer: istep dispatcher reconfigLoopTestRunner function - This array is loaded with data via attribute override. The attribute is - then read and then overlayed onto a test case structure. - </description> - <simpleType> - <uint64_t></uint64_t> - <array>5</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>RECONFIG_LOOP_TESTS_ENABLE</id> - <description> - Indicates whether reconfigure loop tests are enabled. - This attribute is set via attribute override + <attribute> + <description>Units: mV </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>MEM_VDD_OFFSET_MILLIVOLTS</id> - <description>Memory VDD voltage domain offset in mV.</description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VDD_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MEM_VCS_OFFSET_MILLIVOLTS</id> - <description>Memory VCS voltage domain offset in mV.</description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_VCS_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MEM_VPP_OFFSET_MILLIVOLTS</id> - <description>Memory VPP voltage domain offset in mV.</description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPP_OFFSET</id> - <macro>DIRECT</macro> + <id>ATTR_MSS_AVDD_SLOPE_INTERCEPT</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MEM_VDDR_OFFSET_MILLIVOLTS</id> - <description>Memory VDDR voltage domain offset in mV.</description> + <id>MSS_CENT_AVDD_INTERCEPT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VDDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>MSS_CENT_AVDD_SLOPE_ACTIVE</id> + <attribute> <description>Units: uV/Membuf </description> + <id>MSS_CENT_VDD_SLOPE_ACTIVE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_AVDD_SLOPE_ACTIVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_CENT_AVDD_SLOPE_INACTIVE</id> + <attribute> <description>Units: uV/Membuf </description> + <id>MSS_CENT_VDD_SLOPE_INACTIVE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_AVDD_SLOPE_INACTIVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_CENT_AVDD_INTERCEPT</id> + <attribute> <description>Units: mV </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> + <id>MSS_CENT_VDD_INTERCEPT</id> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_AVDD_SLOPE_INTERCEPT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_CENT_VDD_SLOPE_ACTIVE</id> - <description>Units: uV/Membuf - </description> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_CENT_VDD_SLOPE_INACTIVE</id> + <attribute> <description>Units: uV/Membuf </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> + <id>MSS_CENT_VCS_SLOPE_ACTIVE</id> <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>MSS_CENT_VDD_INTERCEPT</id> - <description>Units: mV - </description> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_CENT_VCS_SLOPE_ACTIVE</id> + <attribute> <description>Units: uV/Membuf </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> <id>MSS_CENT_VCS_SLOPE_INACTIVE</id> - <description>Units: uV/Membuf - </description> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_CENT_VCS_INTERCEPT</id> + <attribute> <description>Units: mV </description> + <id>MSS_CENT_VCS_INTERCEPT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_VPP_SLOPE</id> + <attribute> <description>Units: uV/DRAM </description> + <id>MSS_VOLT_VPP_SLOPE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_VPP_INTERCEPT</id> + <attribute> <description>Units: mV </description> + <id>MSS_VOLT_VPP_INTERCEPT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_VPP_SLOPE_POST_DRAM_INIT</id> + <attribute> <description>Units: uV/DRAM </description> + <id>MSS_VOLT_VPP_SLOPE_POST_DRAM_INIT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_VPP_INTERCEPT_POST_DRAM_INIT</id> + <attribute> <description>Units: mV </description> + <id>MSS_VOLT_VPP_INTERCEPT_POST_DRAM_INIT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_DDR3_VDDR_SLOPE</id> + <attribute> <description>Units: 1/Amps </description> + <id>MSS_VOLT_DDR3_VDDR_SLOPE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_DDR3_VDDR_INTERCEPT</id> + <attribute> <description>Units: mV </description> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MRW_DDR3_VDDR_MAX_LIMIT</id> + <attribute> <description>Maximum voltage limit for the dynamic VID DDR3 VDDR voltage setpoint. In mV. </description> + <id>MRW_DDR3_VDDR_MAX_LIMIT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id> + <attribute> <description>Units: 1/Amps </description> + <id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id> + <attribute> <description>Units: mV </description> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> + <attribute> <description>Maximum voltage limit for the dynamic VID DDR3 VDDR voltage setpoint. In mV. </description> + <id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_DDR4_VDDR_SLOPE</id> + + <attribute> <description>Units: 1/Amps </description> + <id>MSS_VOLT_DDR4_VDDR_SLOPE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_DDR4_VDDR_INTERCEPT</id> + <attribute> <description>Units: mV </description> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MRW_DDR4_VDDR_MAX_LIMIT</id> + <attribute> <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage setpoint. In mV. </description> + <id>MRW_DDR4_VDDR_MAX_LIMIT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id> + <attribute> <description>Units: 1/Amps </description> + <id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id> + <attribute> <description>Units: mV </description> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> + <attribute> <description>Maximum voltage limit for the dynamic VID DDR4 VDDR voltage setpoint. In mV. </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>MSS_VOLT_OVERRIDE</id> - <description> - Possible DRAM voltage override. - Firmware notes: Default should be NONE (0x00). - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VOLT_COMPLIANT_DIMMS</id> - <description> - Compliant Voltages. Created to call out non-compliant dimms - if they exist in the system. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VOLT_COMPLIANT_DIMMS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VDDR_OVERIDE_SPD</id> - <description> - Possible VDDR voltage override. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VDDR_OVERIDE_SPD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>MSS_MRW_POWER_CONTROL_REQUESTED</id> - <description> - Enumeration defining the type of power control requested - </description> - <enumerator> - <name>OFF</name> - <value>0</value> - </enumerator> - <enumerator> - <name>POWER_DOWN</name> - <value>1</value> - </enumerator> - <enumerator> - <name>STR</name> - <value>2</value> - </enumerator> - <enumerator> - <name>PD_AND_STR</name> - <value>3</value> - </enumerator> - <default>OFF</default> -</enumerationType> - -<attribute> - <id>MSS_MRW_POWER_CONTROL_REQUESTED</id> - <description> - Memory power control settings programmed during IPL - Used by OCC when exiting idle powersave mode - Producer: MRW - - 0x00 = OFF - 0x01 = POWER_DOWN - 0x02 = STR - 0x03 = PD_AND_STR - </description> - <simpleType> - <uint8_t> - <default>OFF</default> - </uint8_t> - </simpleType> + <id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_POWER_CONTROL_REQUESTED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>MSS_MRW_IDLE_POWER_CONTROL_REQUESTED</id> - <description> - Enumeration defining the type of power control requested - </description> - <enumerator> - <name>OFF</name> - <value>0</value> - </enumerator> - <enumerator> - <name>POWER_DOWN</name> - <value>1</value> - </enumerator> - <enumerator> - <name>STR</name> - <value>2</value> - </enumerator> - <enumerator> - <name>PD_AND_STR</name> - <value>3</value> - </enumerator> - <default>NONE</default> -</enumerationType> - - -<attribute> - <id>MSS_MRW_IDLE_POWER_CONTROL_REQUESTED</id> - <description> - Memory power control settings for IDLE powersave mode - Used by OCC when entering idle powersave mode - Producer: MRW - - 0x00 = OFF - 0x01 = POWER_DOWN - 0x02 = STR - 0x03 = PD_AND_STR - </description> + <readable></readable> <simpleType> - <uint8_t> - <default>OFF</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PFET_WORKAROUND_RUN_FLAG</id> - <description> - Flag to store that the work-around for HW250017 as been run so that during any resets it is skipped. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PFET_WORKAROUND_RUN_FLAG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_OCC_LFIR_MASK</id> - <description> - Upon an UE event, PRD may update some fir masks in occ domain. To avoid this update getting lost during occ reset, which could eventually cause multiple occ resets, this attribute is added to be the storage to remember the OCC_LFIR_MASK in the RESET phase so that reset procedures can later overlay this updated settings with the default instalation in INIT phase. See details in SW260003. - Producer/Consumer: p8_pm_occ_firinit.C - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_OCC_LFIR_MASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PBA_FIR_MASK</id> - <description> - Upon an UE event, PRD may update some fir masks in occ domain. To avoid this update getting lost during occ reset, which could eventually cause multiple occ resets, this attribute is added to be the storage to remember the PBA_FIR_MASK in the RESET phase so that reset procedures can later overlay this updated settings with the default instalation in INIT phase. See details in SW260003. - Producer/Consumer: p8_pm_pba_firinit.C - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PBA_FIR_MASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_PMC_LFIR_MASK</id> - <description> - Upon an UE event, PRD may update some fir masks in occ domain. To avoid this update getting lost during occ reset, which could eventually cause multiple occ resets, this attribute is added to be the storage to remember the PMC_LFIR_MASK in the RESET phase so that reset procedures can later overlay this updated settings with the default instalation in INIT phase. See details in SW260003. - Producer/Consumer: p8_pm_pmc_firinit.C - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_PMC_LFIR_MASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_FIRINIT_DONE_ONCE_FLAG</id> - <description> - Due to SW260003, a flag is needed to remember if we executed the p8_pm_firinit procedures at least once. - Producer/Consumer: p8_pm_firinit.C - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_FIRINIT_DONE_ONCE_FLAG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SLEEP_ENABLE</id> - <description>Control HW response to execution of PPC sleep instruction - if OFF, treat sleep as nap - if ON, treat sleep as sleep - Producer: Hostboot - Consumer: p8_slw_build.C - </description> - <simpleType> - <uint8_t> - <default>0x0</default> - </uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SLEEP_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>I2C_SWITCHES</id> - <description>Attribute storing information about which I2C method to use</description> + <attribute> <complexType> - <description>Structure which defines which I2C access method to use at + <description>Structure which defines which I2C access method to use at a point in time. Only applicable if target supports one or more I2C types. Only one bit (of the first two) can ever be set at any one time. </description> - <field> - <name>useFsiI2C</name> - <description>0b0: Do not use FSI I2C at this time. 0b1: Use FSI + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use FSI I2C at this time. 0b1: Use FSI I2C at this time</description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>useHostI2C</name> - <description>0b0: Do not use Host I2C at this time. 0b1: Use + <name>useFsiI2C</name> + <type>uint8_t</type> + </field> + <field> + <bits>1</bits> + <default>0</default> + <description>0b0: Do not use Host I2C at this time. 0b1: Use Host I2C at this time</description> - <type>uint8_t</type> - <bits>1</bits> - <default>0</default> - </field> - <field> - <name>reserved</name> - <description>Reserved for future expansion</description> - <type>uint8_t</type> - <bits>6</bits> - <default>0</default> - </field> + <name>useHostI2C</name> + <type>uint8_t</type> + </field> + <field> + <bits>6</bits> + <default>0</default> + <description>Reserved for future expansion</description> + <name>reserved</name> + <type>uint8_t</type> + </field> </complexType> + <description>Attribute storing information about which I2C method to use</description> + <id>I2C_SWITCHES</id> <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> + <readable></readable> + <writeable></writeable> + </attribute> -<attribute> - <id>OCC_MASTER_CAPABLE</id> + <attribute> <description> This attribute is to determine whether an occ is master capable. An OCC is master capable if it's parent processor is wired to the APSS. </description> - <simpleType> - <uint8_t> - <default>0</default> <!-- false --> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>MSS_DRAMINIT_RESET_DISABLE</id> - <description>A disable switch for resetting the phy delay values at the beginning of calling mss_draminit_training.</description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <id>OCC_MASTER_CAPABLE</id> <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_DRAMINIT_RESET_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>ISDIMM_POWER_CURVE_ALGORITHM_VERSION</id> - <description> - version of algorithm used to calculate ISDIMM power curves - </description> + <readable></readable> <simpleType> - <uint32_t> + <uint8_t> <default>0</default> - </uint32_t> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_ISDIMM_POWER_CURVE_ALGORITHM_VERSION</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <no_export/> + </attribute> -<attribute> - <id>PROC_PCIE_LANE_MASK</id> + <attribute> <description>Effective PCIE Lane Mask Creator: Firmware Purpose: Holds the effective PCIE lane mask of each PEC after taking @@ -17245,19 +3229,18 @@ Measured in GB</description> and lane set 1 value of 0x00FF for PEC0, means the IOP is bifurcated into two x8s. </description> + <id>PROC_PCIE_LANE_MASK</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - </uint16_t> - <array>4</array> + <array>4</array> + <uint16_t></uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> + <writeable></writeable> <no_export/> -</attribute> + </attribute> -<attribute> - <id>PEC_PCIE_IOP_REVERSAL</id> + <attribute> <description>Effective PCIE IOP reversal configuration Creator: Firmware Purpose: Holds the effective PCIE IOP reversal value after taking into @@ -17269,18 +3252,17 @@ Measured in GB</description> index in the array is a mask which specifies which bit to invert in the lane swap settings for the given PEC/lane set. </description> + <id>PEC_PCIE_IOP_REVERSAL</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> - <array>4</array> + <array>4</array> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>PEC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id> + <attribute> <description>Base PCIE IOP reversal configuration Creator: Firmware Purpose: Holds the base PCIE IOP reversal value without considering IOP @@ -17290,17 +3272,16 @@ Measured in GB</description> index in the array is a mask which specifies which bit to invert in the lane swap settings for the given lane set. </description> + <id>PEC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> - <array>4</array> + <array>4</array> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id> + <attribute> <description>Base PCIE IOP swap configuration value Creator: MRW Purpose: Holds the base IOP swap configuration value without considering @@ -17310,16 +3291,16 @@ Measured in GB</description> Data Format: A uint8_t value. The value specifices for the hardware how to swap the PCIE lanes for the given PEC. </description> + <id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t></uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> + </attribute> -<attribute> - <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id> + <attribute> <description>PCIE Lane Mask base configuration Creator: MRW Purpose: Holds the base PCIE lane mask assuming no dynamic IOP @@ -17331,18 +3312,17 @@ Measured in GB</description> means the PEC is a x16. Lane set 0 value of 0xFF00 and lane set 1 value of 0x00FF, means the PEC is split into two x8s. </description> + <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - </uint16_t> - <array>4</array> + <array>4</array> + <uint16_t></uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> + </attribute> -<attribute> - <id>PEC_PCIE_IOP_REVERSAL_BIFURCATED</id> + <attribute> <description>Base PCIE IOP reversal configuration Creator: Firmware Purpose: Holds the PCIE IOP reversal value for cases where the IOP @@ -17352,17 +3332,16 @@ Measured in GB</description> the array is a mask which specifies which bit to invert in the lane swap settings for the given lane set </description> + <id>PEC_PCIE_IOP_REVERSAL_BIFURCATED</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> - <array>4</array> + <array>4</array> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>PEC_PCIE_IOP_SWAP_BIFURCATED</id> + <attribute> <description>Bifurcated PCIE IOP swap configuration value Creator: MRW Purpose: Holds the base IOP swap configuration value for the IOPs in the @@ -17372,15 +3351,15 @@ Measured in GB</description> Data Format: A uint8_t value. The value specifices for the hardware how to swap the PCIE lanes for the given PEC. </description> + <id>PEC_PCIE_IOP_SWAP_BIFURCATED</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t></uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>PEC_PCIE_LANE_MASK_BIFURCATED</id> + <attribute> <description>PCIE Lane Mask bifurcated configuration Creator: MRW Purpose: Holds the PCIE lane mask assuming IOPs are bifurcated. @@ -17390,17 +3369,16 @@ Measured in GB</description> instance, lane set 0 value of 0xFF00 and lane set 1 value of 0x00FF means the IOP is bifurcated into two x8s. </description> + <id>PEC_PCIE_LANE_MASK_BIFURCATED</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - </uint16_t> - <array>4</array> + <array>4</array> + <uint16_t></uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>PROC_PCIE_IS_SLOT</id> + <attribute> <description>Indicates whether PCIE lanes terminate at a pluggable slot Creator: MRW Purpose: Used by FW to know whether the given PCIE lanes terminate at a @@ -17413,85 +3391,32 @@ Measured in GB</description> 1 at a given array index indicates the lanes terminate at a pluggable slot, 0 otherwise. </description> + <id>PROC_PCIE_IS_SLOT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> - <array>4</array> + <array>4</array> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<enumerationType> - <id>CDM_DOMAIN</id> - <description> - Enumeration specifying a target's CEC degraded mode domain - </description> - <enumerator> - <name>NONE</name> - <value>0</value> - </enumerator> - <enumerator> - <name>CPU</name> - <value>1</value> - </enumerator> - <enumerator> - <name>DIMM</name> - <value>2</value> - </enumerator> - <enumerator> - <name>FABRIC</name> - <value>3</value> - </enumerator> - <enumerator> - <name>MEM</name> - <value>4</value> - </enumerator> - <enumerator> - <name>IO</name> - <value>5</value> - </enumerator> - <enumerator> - <name>NODE</name> - <value>6</value> - </enumerator> - <enumerator> - <name>CLOCK</name> - <value>7</value> - </enumerator> - <enumerator> - <name>PSI</name> - <value>8</value> - </enumerator> - <enumerator> - <name>FSP</name> - <value>9</value> - </enumerator> - <enumerator> - <name>ALL</name> - <value>10</value> - </enumerator> - <default>NONE</default> -</enumerationType> + </attribute> -<attribute> - <id>CDM_DOMAIN</id> + <attribute> <description> Specifies a target's CEC degraded mode domain. For example, all DIMMs are part of the DIMM CEC degraded mode domain. </description> + <hasStringConversion></hasStringConversion> + <id>CDM_DOMAIN</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <enumeration> - <id>CDM_DOMAIN</id> - </enumeration> + <enumeration> + <id>CDM_DOMAIN</id> + </enumeration> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hasStringConversion/> -</attribute> + </attribute> -<attribute> - <id>I2C_BUS_SPEED_ARRAY</id> + <attribute> <description>Designates the speed at which a given I2C bus should run. Creator: MRW Purpose: Used by FW to know the fastest possible bus speed that all of @@ -17501,542 +3426,369 @@ Measured in GB</description> number of the bus. The value in the array is the I2C bus speed used for that engine/port combination in KHz. </description> + <id>I2C_BUS_SPEED_ARRAY</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint16_t> - <default> + <array>4,13</array> + <uint16_t> + <default> 0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0,0,0,0</default> - </uint16_t> - <array>4,13</array> + </uint16_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> <no_export/> -</attribute> + </attribute> -<attribute> - <id>ISTEP_PAUSE_ENABLE</id> + <attribute> <description> Used to enable pause/stop in between isteps. This attribute is set via attribute override. </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> + <id>ISTEP_PAUSE_ENABLE</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> -<enumerationType> - <id>SUPPORTED_HOT_PLUG</id> - <description> - Enumeration indication which Hot Plug Controllers are supported by - the current system. - </description> - <enumerator> - <name>NA</name> - <value>0</value> - </enumerator> - <enumerator> - <name>MAX5961</name> - <value>0x01</value> - </enumerator> - <enumerator> - <name>PCA9551</name> - <value>0x02</value> - </enumerator> - <default>NA</default> -</enumerationType> - -<attribute> - <id>HOT_PLUG_POWER_CONTROLLER_INFO</id> - <description>Hot Plug Controller values for a specific processor. - Purpose: Holds information about the hot plug controllers so that a - Hardware procedure is able to turn them on and off. - Data Format: up to 8 Hot Plug Controllers x 7 variables of information - This data is at the processor level. - The needed information and their individual sizes are as follows: - (1) I2C Master processor engine (uint8_t) - (2) I2C Master processor port (uint8_t) - (3) Bus Speed (uint16_t value: 2 uint8_t values: MSB, LSB) - (4) Slave address (uint8_t) - (5) Device type (uint8_t: see SUPPORTED_HOT_PLUG enum) - (6) I2C Master processor node (uint8_t) - (7) I2C Master processor position (uint8_t) - Thus, the information will be 8 bytes. - </description> + <readable></readable> <simpleType> - <uint8_t> - <default>0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - </default> - </uint8_t> - <array>8,8</array> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_HOT_PLUG_POWER_CONTROLLER_INFO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>ISTEP_PAUSE_CONFIG</id> + <attribute> <description> Used to configure the parameters for enabling pause/stop between isteps. This attribute is set via attribute override. </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> + <id>ISTEP_PAUSE_CONFIG</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>OPT_MEMMAP_GROUP_POLICY</id> - <description> - Controls scope of grouping performed in memory map calculations - Possible values defined in FAPI ATTR_OPT_MEMMAP_GROUP_POLICY - </description> + <readable></readable> <simpleType> - <uint8_t><default>0x00</default></uint8_t><!-- CHIP_AS_GROUP --> + <uint64_t></uint64_t> </simpleType> - <readable/> - <persistency>non-volatile</persistency> - <hwpfToHbAttrMap> - <id>ATTR_OPT_MEMMAP_GROUP_POLICY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MFG_TRACE_ENABLE</id> - <description> - Override this to a non-zero value to have the FAPI manufacturing - traces output to the console or go to a fsp trace buffer when - console not enabled. - </description> - <simpleType><uint8_t></uint8_t></simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MFG_TRACE_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>TPM_REQUIRED</id> + <attribute> <description> Setting to require(0x1) or not require(0x0) a functional TPM to boot the system. </description> + <id>TPM_REQUIRED</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PROC_PCIE_NUM_PHB</id> - <description> - creator: platform - Number of PCIe PHB units present on target - Murano/Venice: 3 - Naples: 4 - Nimbus: 6 - Cumulus: 6 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_NUM_PHB</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_NUM_IOP</id> - <description> - creator: platform - Number of PCIe IOP units present on target - Murano/Venice: 2 - Naples: 3 - Nimbus: 3 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_NUM_IOP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_NUM_PEC</id> - <description> - creator: platform - Number of PCIe PEC units present on target - Nimbus: 3 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_NUM_PEC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_NUM_LANES</id> - <description> - creator: platform - Number of PCIe I/O lanes supported by target - Murano: 24 - Venice: 32 - Naples: 40 - Nimbus: 48 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_NUM_LANES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- === start configurable threshold attributes for PRD === --> + </attribute> -<attribute> - <id>MNFG_TH_P8EX_L2_CACHE_CES</id> + <attribute> <description> This attribute represents the Maximum number of L2 Cache CEs allowed during Manufacturing. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_P8EX_L2_CACHE_CES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>1</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_P8EX_L2_DIR_CES</id> + <attribute> <description> This attribute represents the Maximum number of L2 Directory CEs allowed during Manufacturing. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_P8EX_L2_DIR_CES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>1</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_P8EX_L3_CACHE_CES</id> + <attribute> <description> This attribute represents the Maximum number of L3 Cache CEs allowed during Manufacturing. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_P8EX_L3_CACHE_CES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>3</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_P8EX_L3_DIR_CES</id> + <attribute> <description> This attribute represents the Maximum number of L3 Directory CEs allowed during Manufacturing. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_P8EX_L3_DIR_CES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>1</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>FIELD_TH_P8EX_L2_LINE_DELETES</id> + <attribute> <description> This attribute represents the Maximum number of L2 Line Deletes allowed in the Field. creator: platform (generated based on MRW data) </description> + <id>FIELD_TH_P8EX_L2_LINE_DELETES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>6</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>FIELD_TH_P8EX_L3_LINE_DELETES</id> + <attribute> <description> This attribute represents the Maximum number of L3 Line Deletes allowed in the Field. creator: platform (generated based on MRW data) </description> + <id>FIELD_TH_P8EX_L3_LINE_DELETES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>6</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>FIELD_TH_P8EX_L2_COL_REPAIRS</id> + <attribute> <description> This attribute represents the Maximum number of L2 Column Repairs allowed in the Field. creator: platform (generated based on MRW data) </description> + <id>FIELD_TH_P8EX_L2_COL_REPAIRS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>7</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>FIELD_TH_P8EX_L3_COL_REPAIRS</id> + <attribute> <description> This attribute represents the Maximum number of L3 Column Repairs allowed in the Field. creator: platform (generated based on MRW data) </description> + <id>FIELD_TH_P8EX_L3_COL_REPAIRS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>7</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_P8EX_L2_LINE_DELETES</id> + <attribute> <description> This attribute represents the Maximum number of L2 Line Deletes allowed during Manufacturing. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_P8EX_L2_LINE_DELETES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_P8EX_L3_LINE_DELETES</id> + <attribute> <description> This attribute represents the Maximum number of L3 Line Deletes allowed during Manufacturing. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_P8EX_L3_LINE_DELETES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_P8EX_L2_COL_REPAIRS</id> + <attribute> <description> This attribute represents the Maximum number of L2 Column Repairs allowed during Manufacturing. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_P8EX_L2_COL_REPAIRS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_P8EX_L3_COL_REPAIRS</id> + <attribute> <description> This attribute represents the Maximum number of L3 Column Repairs allowed during Manufacturing. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_P8EX_L3_COL_REPAIRS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO</id> + <attribute> <description> This attribute represents the Base threshold (for 2GB DRAM ) of Memory CEs allowed during runtime. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>2</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO</id> + <attribute> <description> This attribute represents the Base threshold (for 2GB DRAM ) of Memory CEs allowed during IPL. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>2</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_CEN_MBA_RT_RCE_PER_RANK</id> + <attribute> <description> This attribute represents the maximum number of Memory RCEs allowed per Rank during runtime. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_CEN_MBA_RT_RCE_PER_RANK</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>2</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_CEN_L4_CACHE_CES</id> + <attribute> <description> This attribute represents the maximum number of L4 Cache CEs allowed. creator: platform (generated based on MRW data) </description> + <id>MNFG_TH_CEN_L4_CACHE_CES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>2</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_RCD_PARITY_ERRORS</id> + <attribute> <description> With MNFG thresholds enabled, PRD will make a predictive callout when an RCD parity error (recovery enabled) attention count is equal to this value. A value of 0 defaults to the max threshold of 0xff. </description> + <id>MNFG_TH_RCD_PARITY_ERRORS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>1</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_MEMORY_IUES</id> + <attribute> <description> With MNFG thresholds enabled, PRD will make a predictive callout when a memory intermittent UE attention count is equal to this value. A value of 0 defaults to the max threshold of 0xff. </description> + <id>MNFG_TH_MEMORY_IUES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>1</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MNFG_TH_MEMORY_IMPES</id> + <attribute> <description> With MNFG thresholds enabled, PRD will make a predictive callout when a memory intermittent MPE attention count is equal to this value. A value of 0 defaults to the max threshold of 0xff. </description> + <id>MNFG_TH_MEMORY_IMPES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>1</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<!-- === end configurable threshold attributes for PRD === --> - -<!-- === start RCD parity error reconfig loop attributes for PRD/MDIA === --> + </attribute> -<attribute> - <id>RCD_PARITY_RECONFIG_LOOPS_ALLOWED</id> + <attribute> <description> The number of reconfig loops allowed due to RCD parity errors when recovery is disabled. PRD will make a predictive callout and stop issuing @@ -18044,3087 +3796,2096 @@ Measured in GB</description> greater than this value. A value of 0 indicates that no reconfig loops are allowed due to RCD parity errors. </description> + <id>RCD_PARITY_RECONFIG_LOOPS_ALLOWED</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>1</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>RCD_PARITY_RECONFIG_LOOP_COUNT</id> + <attribute> <description> PRD will increment this count and issue a reconfig loop each time an RCD parity error (recovery disabled) is detected during Memory Diagnostics. This value will be cleared at the end of Memory Diagnostics if it is able to complete without the need to issue a reconfig loop. </description> + <id>RCD_PARITY_RECONFIG_LOOP_COUNT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<!-- === end RCD parity error reconfig loop attributes for PRD/MDIA === --> - -<attribute> - <id>PRD_HWP_PLID</id> - <description> - PRD will perform error isolation for certain errors that may cause a HWP - to fail. This attribute will be used by the HWP to store the PLID so that - PRD can subsequently check it for a non-zero value and link the HWP PLID - to the PRD error log. - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>RESOURCE_IS_CRITICAL</id> + <attribute> <description> Used to tell if a resource is critical to perform an IPL. If this attribute is set to 1 and the target is deconfigured, the IPL MUST terminate. </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> + <id>RESOURCE_IS_CRITICAL</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> - - -<attribute> - <id>BRAZOS_RX_FIFO_OVERRIDE</id> - <description> - Defines where to apply Brazos rx_fifo_final_l2u_dly override settings for SW299500. - </description> + <readable></readable> <simpleType> <uint8_t> <default>0</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_BRAZOS_RX_FIFO_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- === Manufacturing threshold Attributes of PRD === --> - -<attribute> - <id>MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id> - <description> - Maximum number of installed DIMMs per VMEM regulator for all - VMEM regulators in the system. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id> - <description>Machine Readable Workbook enablement of the HWP code to adjust - the VMEM regulator power limit based on number of installed DIMMs. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id> - <description>Machine Readable Workbook value for the maximum possible number - of dimms that can be installed under any of the VMEM regulators. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>TRUSTED_SLAVE_SCAN_PATH_ACTIVE</id> - <description> - Set to indicate state of master->slave scan path. - Platform should default to false at beginning of IPL, and set to - true once trusted XSCOM path is active to all slave chips in drawer - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_TRUSTED_SLAVE_SCAN_PATH_ACTIVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FORCE_SKIP_SBE_MASTER_INTR_SERVICE</id> - <description> - Set to force skip of SBE interrupt service for master chip. - Default is to disable the use of the SBE interrupt service. - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_FORCE_SKIP_SBE_MASTER_INTR_SERVICE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FORCE_USE_SBE_SLAVE_SCAN_SERVICE</id> - <description> - Set to force use of SBE scan service for slave chips. - Default is to enable the use of the SBE scan service - only for slave chips with security enabled. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SBE_MASTER_INTR_SERVICE_DELAY_CYCLES</id> - <description> - Cycle delay of SBE master interrupt service loop wait statement. - Paces rate of decrementer progress and prevents SBE from consuming PIB. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_MASTER_INTR_SERVICE_DELAY_CYCLES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SBE_MASTER_INTR_SERVICE_DELAY_US</id> - <description> - Execution delay (in microseconds) of SBE master interrupt service loop. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_MASTER_INTR_SERVICE_DELAY_US</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VREF_CAL_CNTL</id> - <description>Training Control over IPL - - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=DRAM - Enable V-Ref Train DRAM Level; 0x02=RANK Level Training; - 0x03=PORT Level Training; 0x04=MBA Level; 0x05=CENTAUR level; - Default Value = 0x01; - </description> - <simpleType> - <uint8_t> - <default>0x01</default> - </uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VREF_CAL_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_RCD_CNTL_WORD_X</id> - <description>Additional RCD Control Word for DDR4. Used in mss_dram_init and is computed in mss_eff_cnfg. - Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint64_t></uint64_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_RCD_CNTL_WORD_X</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC00</id> - <description>F0RC00: Global Features Control Word.For normal operation, output inversion is always enabled. For DIMM vendor test purpose, output - inversion can be disabled. When disabled, register tPDM is not guaranteed to be met. - NOTE: Default value - 0x00. Values Range from 0-8. - 00 - Normal Operation; 01 - Output Inversion Disabled; 02 - Weak Drive Enabled; 04 - A outputs disabled; 08 - B outputs disabled; So on. - No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC00</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC01</id> - <description>F0RC01 - Clock Driver Enable Control Word.1. Output clocks may be individually turned on or off to conserve power. - The system must read the module SPD to determine which clock outputs are used by the module. The PLL remains locked - on CK_t/CK_c unless the system stops the clock inputs to the DDR4RCD02 to enter the lowest power mode. - Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC01</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC02</id> - <description>F0RC02: Timing and IBT Control Word; - Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC02</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC03</id> - <description>F0RC03 - CA and CS Signals Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC03</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC04</id> - <description>F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC04</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC05</id> - <description>F0RC05 - Clock Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC05</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC06_07</id> - <description>F0RC06: Command Space Control Word definition; - Default value - 0xF0 (NOP). Values Range from 00 to F0. F0RC07 not used. RDIMM - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC06_07</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC08</id> - <description>F0RC08: Command Space Control Word definition; - Default value - 0x03. Values Range from 00 to 08 decimal. Check the stack height and calculate dynamically; - 00 = Stack height_8; 01 = Stack height_4; 02 = Stack height_2; - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC08</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC09</id> - <description>F0RC09: Command Space Control Word definition; - Default value - 0xF0 (NOP). Values Range from 00 to F0. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC09</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--HWSV needs to update names so we can remove this--> -<attribute> - <id>EFF_DIMM_DDR4_RC10</id> - <description>RDIMM Operating Speed; Read from ATTR_MSS_FREQ; - Default value - 00. Values Range from 00 to 09. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC10</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC0A</id> - <description>RDIMM Operating Speed; Read from ATTR_MSS_FREQ; - Default value - 00. Values Range from 00 to 09. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC0A</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<!--HWSV needs to update names so we can remove this--> -<attribute> - <id>EFF_DIMM_DDR4_RC11</id> - <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR_MILLIVOLTS. - Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC11</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC0B</id> - <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR_MILLIVOLTS. - Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC0B</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--HWSV needs to update names so we can remove this--> -<attribute> - <id>EFF_DIMM_DDR4_RC12</id> - <description>F0RC0C - Training Control Word; - Default value - 00. Values Range from 00 to 07 decimal.No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC12</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC0C</id> - <description>F0RC0C - Training Control Word; - Default value - 00. Values Range from 00 to 07 decimal.No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC0C</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--HWSV needs to update names so we can remove this--> -<attribute> - <id>EFF_DIMM_DDR4_RC13</id> - <description>F0RC0D - DIMM Configuration Control Word; - Default value - 0x0B. Values Range from 00 to 15 decimal. - Dynamically calculated using 4 bits[0:3] Bit 0 - Address Mirroring; Bit 1 - Rdimm(1)/Lrdimm (0) ; Bit 2 - N/A ; Bit 3 - CS Mode (Direct / Quad CS mode etc); - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC13</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC0D</id> - <description>F0RC0D - DIMM Configuration Control Word; - Default value - 0x0B. Values Range from 00 to 15 decimal. - Dynamically calculated using 4 bits[0:3] Bit 0 - Address Mirroring; Bit 1 - Rdimm(1)/Lrdimm (0) ; Bit 2 - N/A ; Bit 3 - CS Mode (Direct / Quad CS mode etc); - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC0D</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--HWSV needs to update names so we can remove this--> -<attribute> - <id>EFF_DIMM_DDR4_RC14</id> - <description>F0RC0E - Parity Control Word; Default value - 00. Check from ATTR_EFF_CA_PARITY and assign; Values Range from 00 to 0F. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC14</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC0E</id> - <description>F0RC0E - Parity Control Word; Default value - 00. Check from ATTR_EFF_CA_PARITY and assign; Values Range from 00 to 0F. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC0E</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--HWSV needs to update names so we can remove this--> -<attribute> - <id>EFF_DIMM_DDR4_RC15</id> - <description>F0RC0F - Command Latency Adder Control Word; - Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC15</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC0F</id> - <description>F0RC0F - Command Latency Adder Control Word; - Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC0F</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>EFF_DIMM_DDR4_RC_1x</id> - <description>F0RC1x - Internal VrefCA Control Word; - Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC_1x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC_2x</id> - <description>F0RC2x: I2C Bus Control Word; - Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC_2x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC_3x</id> - <description>F0RC3x - Fine Granularity RDIMM Operating Speed; - Default value = (Operating Freq - 1250)/20. Values Range from 00 to 61 Hex. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC_3x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC_4x</id> - <description>F0RC4x: CW Source Selection Control Word; - Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC_4x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC_5x</id> - <description>F0RC5x: CW Destination Selection and Write/Read Additional QxODT[1:0] Signal High; - Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC_5x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC_6x</id> - <description>F0RC6x: CW Data Control Word; - Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC_6x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC_7x</id> - <description>F0RC7x: IBT Control Word; - Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC_7x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC_8x</id> - <description>F0RC8x: ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word; - Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC_8x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC_9x</id> - <description>F0RC9x1: QxODT[1:0] Write Pattern Control Word; - Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC_9x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC_Ax</id> - <description>F0RCAx1: QxODT[1:0] Read Pattern Control Word; - Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC_Ax</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_RC_Bx</id> - <description>F0RCBx: IBT and MRS Snoop Control Word; Default value - 07. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. - creator: mss_eff_cnfg - consumer: mss_dram_init - firmware notes: none - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_RC_Bx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_LRDIMM_WORD_X</id> - <description>Additional buffer control word for LRDIMM building of the BCW</description> - <simpleType> - <uint64_t></uint64_t> - <array>2,2</array> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_EFF_LRDIMM_WORD_X</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>EFF_LRDIMM_ADDITIONAL_CNTL_WORDS</id> - <description>LRDIMM additional RCD control words as set by DIMM SPD: - F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, - F[7,8]RC11, F[9,10]RC10, F[9,10]RC11, F[1]RC8, F[3]RC9, - F[3]RC8, F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15. - Eff config should set this up. - </description> - <simpleType> - <uint64_t></uint64_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_LRDIMM_ADDITIONAL_CNTL_WORDS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MCBIST_DDR4_PDA_ENABLE</id> - <description>Controls PDA train enable or PBA. 00 - Disable; 01 - PDA; 02 - PBA(Lrdimm)</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MCBIST_DDR4_PDA_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--Deprecated--> -<attribute> - <id>MSS_MRW_MCS_PREFETCH_RETRY_THRESHOLD</id> - <description> - Option to control MCS prefetch retry threshold, for performance - optimization. This attribute controls the number of retries in the - prefetch engine. Retry threshold available ranges from 16 to 30. Note: - Values outside those ranges will default to 30. In MRW. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_MCS_PREFETCH_RETRY_THRESHOLD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<!--Deprecated--> - -<attribute> - <id>EFF_DRAM_TCCD_S</id> - <description>tccd_l. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory channel will have a value. - Creator: mss_eff_cnfg - Consumer:various - Firmware notes: none - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TCCD_S</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + </attribute> -<attribute> - <id>VAS_HYPERVISOR_WINDOW_CONTEXT_ADDR</id> + <attribute> <description>VAS - Hypervisor Window Contexts address MMIO consumed by PHYP </description> + <id>VAS_HYPERVISOR_WINDOW_CONTEXT_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t></uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>VAS_USER_WINDOW_CONTEXT_ADDR</id> + <attribute> <description>VAS - User Window Context address MMIO consumed by PHYP </description> + <id>VAS_USER_WINDOW_CONTEXT_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t></uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>LPC_BUS_ADDR</id> + <attribute> <description>LPC Bus address - MMIO consumed by PHYP</description> + <id>LPC_BUS_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> + <writeable></writeable> <simpleType> - <uint64_t></uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>volatile</persistency> - <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>NVIDIA_NPU_PRIVILEGED_ADDR</id> + <attribute> <description>Nvidia Link - NPU Privileged Regs address MMIO consumed by PHYP </description> + <id>NVIDIA_NPU_PRIVILEGED_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t></uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>NVIDIA_NPU_USER_REG_ADDR</id> + <attribute> <description>Nvidia Link - NPU User Regs address MMIO consumed by PHYP </description> + <id>NVIDIA_NPU_USER_REG_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t></uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>NVIDIA_PHY0_REG_ADDR</id> + <attribute> <description>Nvidia Link - Phy 0 Regs address MMIO consumed by PHYP </description> + <id>NVIDIA_PHY0_REG_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t></uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>NVIDIA_PHY1_REG_ADDR</id> + <attribute> <description>Nvidia Link - Phy 1 Regs address MMIO consumed by PHYP </description> + <id>NVIDIA_PHY1_REG_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t></uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>XIVE_CONTROLLER_BAR_ADDR</id> + <attribute> <description>XIVE - Controller Bar address MMIO consumed by PHYP </description> + <id>XIVE_CONTROLLER_BAR_ADDR</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> + <writeable></writeable> <simpleType> - <uint64_t></uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>XIVE_THREAD_MGMT1_BAR_ADDR</id> + <attribute> <description>XIVE - Thread Management Bar address register 1 MMIO consumed by HB/PHYP </description> + <id>XIVE_THREAD_MGMT1_BAR_ADDR</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> + <writeable></writeable> <simpleType> - <uint64_t></uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - + </attribute> -<attribute> - <id>PSI_HB_ESB_ADDR</id> + <attribute> <description>PSIHB - ESB space address - MMIO consumed by PHYP </description> + <id>PSI_HB_ESB_ADDR</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> + <writeable></writeable> <simpleType> - <uint64_t></uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>NX_RNG_ADDR</id> + <attribute> <description>NX - RNG space - MMIO consumed by PHYP</description> + <id>NX_RNG_ADDR</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint64_t></uint64_t> + <uint64_t></uint64_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<enumerationType> - <id>FUSED_CORE_OPTION</id> - <description>Enum for FUSED_CORE_OPTION</description> - <enumerator> - <name>USING_DEFAULT_CORES</name> - <value>0</value> - </enumerator> - <enumerator> - <name>USING_NORMAL_CORES</name> - <value>1</value> - </enumerator> - <enumerator> - <name>USING_FUSED_CORES</name> - <value>2</value> - </enumerator> -</enumerationType> + </attribute> -<attribute> - <id>FUSED_CORE_OPTION</id> + <attribute> <description> If not loading PHYP or OPAL, then use this to decide whether to use FUSED cores or NOT. </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> + <id>FUSED_CORE_OPTION</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<enumerationType> - <id>FUSED_CORE_MODE</id> - <description>Enum for FUSED_CORE_MODE</description> - <enumerator> - <name>SMT4_DEFAULT</name> - <value>0</value> - </enumerator> - <enumerator> - <name>SMT4_ONLY</name> - <value>1</value> - </enumerator> - <enumerator> - <name>SMT8_ONLY</name> - <value>2</value> - </enumerator> -</enumerationType> - -<attribute> - <id>FUSED_CORE_MODE</id> - <description> - Stores the SMT setting used to determine fused mode. - SMT4_DEFAULT: Nimbus_DD1, boot in SMT4 but can change to SMT8 - SMT4_ONLY: Nimbus_DD2/Cumulus, set based on PVR info - SMT8_ONLY: Nimbus_DD2/Cumulus, set based on PVR info - </description> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>ICACHE_LINE_SIZE</id> + <attribute> <description>Icache Line Size in bytes</description> + <id>ICACHE_LINE_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>ICACHE_BLOCK_SIZE</id> + <attribute> <description>ICache Block Size in bytes</description> + <id>ICACHE_BLOCK_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>ICACHE_SIZE</id> + <attribute> <description>ICache Size in KB</description> + <id>ICACHE_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>ICACHE_ASSOC_SETS</id> + <attribute> <description>ICache Assoc Sets</description> + <id>ICACHE_ASSOC_SETS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>DCACHE_LINE_SIZE</id> + <attribute> <description>DCache Line Size in bytes</description> + <id>DCACHE_LINE_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>DCACHE_ASSOC_SETS</id> + <attribute> <description>DCache Associative Sets</description> + <id>DCACHE_ASSOC_SETS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>L2_CACHE_LINE_SIZE</id> + <attribute> <description>L2 Cache Line Size in bytes</description> + <id>L2_CACHE_LINE_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>L2_CACHE_SIZE</id> + <attribute> <description>L2 Cache Size in KB</description> + <id>L2_CACHE_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>L2_CACHE_ASSOC_SETS</id> + <attribute> <description>L2 Cache Assoc Sets</description> + <id>L2_CACHE_ASSOC_SETS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>L3_CACHE_LINE_SIZE</id> + <attribute> <description>L3 Cache Line Size in bytes</description> + <id>L3_CACHE_LINE_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>L3_CACHE_SIZE</id> + <attribute> <description>L3 Cache Size in KB</description> + <id>L3_CACHE_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> + </attribute> + + <attribute> + <description>Time Base frequency in MHZ</description> + <id>TIME_BASE</id> <persistency>non-volatile</persistency> - <readable/> - </attribute> - - <attribute> - <id>TIME_BASE</id> - <description>Time Base frequency in MHZ</description> - <simpleType> - <uint32_t> - <default>0x800000</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + <simpleType> + <uint32_t> + <default>0x800000</default> + </uint32_t> + </simpleType> + </attribute> -<attribute> - <id>TLB_DATA_ENTRIES</id> + <attribute> <description>TLB Data Entries</description> + <id>TLB_DATA_ENTRIES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>TLB_DATA_ASSOC_SETS</id> + <attribute> <description>TLB Data Associative Sets</description> + <id>TLB_DATA_ASSOC_SETS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>TLB_INSTR_ENTRIES</id> + <attribute> <description>TLB Instruction Entries</description> + <id>TLB_INSTR_ENTRIES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>TLB_INSTR_ASSOC_SETS</id> + <attribute> <description>TLB Instruction Associative Sets</description> + <id>TLB_INSTR_ASSOC_SETS</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>TLB_RESERVE_SIZE</id> + <attribute> <description>Reserve Size in bytes</description> + <id>TLB_RESERVE_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>DATA_CACHE_SIZE</id> + <attribute> <description>L1 Data Cache Size in KB</description> + <id>DATA_CACHE_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>DATA_CACHE_LINE_SIZE</id> + <attribute> <description>L1 Data Cache Line Size in bytes</description> + <id>DATA_CACHE_LINE_SIZE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>THREAD_COUNT</id> + <attribute> <description>Thread Count</description> - <simpleType> - <uint32_t> - <default>0x4</default> - </uint32_t> - </simpleType> + <id>THREAD_COUNT</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PFET_POWERUP_DELAY_NS</id> - <description> - Time (in nanoseconds) between PFET controller steps (7 of them) when turning - the PFES ON - </description> + <readable></readable> <simpleType> - <uint32_t> - <!-- Will be set by HWP --> - <default>0</default> - </uint32_t> + <uint32_t> + <default>0x4</default> + </uint32_t> </simpleType> - <readable/> - <persistency>non-volatile</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PFET_POWERUP_DELAY_NS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - + </attribute> -<attribute> - <id>HDAT_RSV_MEM_NUM_SECTIONS</id> + <attribute> <description> Number of internal data pointers we have in the hostboot reserved memory section. </description> + <id>HDAT_RSV_MEM_NUM_SECTIONS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>HDAT_HBRT_NUM_SECTIONS</id> + <attribute> <description> Number of internal data pointers we have in the hostboot runtime data section. </description> + <id>HDAT_HBRT_NUM_SECTIONS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>HDAT_HBRT_SECTION_SIZE</id> + <attribute> <description> Biggest size for any of the hostboot runtime data sections. </description> - <simpleType> - <uint64_t> - </uint64_t> - <array>9</array> - </simpleType> + <id>HDAT_HBRT_SECTION_SIZE</id> <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<!--<attribute> - <id>FREQ_PROC_REFCLOCK_KHZ</id> - <description> - The frequency of the processor refclock in kHz. - Provided by the Machine Readable Workbook. - This can be overridden to adjust the refclock frequency. - </description> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <array>9</array> + <uint64_t></uint64_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_PROC_REFCLOCK_KHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute>--> + <writeable></writeable> + </attribute> -<!--<attribute> - <id>FREQ_MEM_REFCLOCK</id> + <attribute> <description> - The frequency of the memory refclock in MHz. - Provided by the Machine Readable Workbook. - This is read by the set_ref_clock HWP to find out the desired frequency. - This can be overridden to adjust the refclock frequency. + System control to set the power limit for Workload Optimized + Frequency (WOF) algorithms. This is used to select the + proper VFRT tables. + Producer: TMGT + Consumers: FW that selects VFRT tables </description> + <id>WOF_POWER_LIMIT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_MEM_REFCLOCK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute>--> + <writeable></writeable> + </attribute> -<attribute> - <id>REQUIRED_SYNCH_MODE</id> - <description> - Specify the system policy to enforce synchronous mode between memory and - nest. This drives the value of ATTR_MC_SYNC_MODE. - 0 = UNDETERMINED : Run synchronously if the dimm and nest freq matches - 1 = ALWAYS : Require matching frequencies and deconfigure memory that - does not match the nest - 2 = NEVER : Do not run synchronously, even if the frequencies match - </description> + <attribute> + <description>The address offset which each Chiplet types pervasive + address space used to represent the a chiplet. + 0x00 to 0x0F => For P9 all non-core and non-cache chiplets + 0x10 to 0x1F => All Cache Chiplets + 0x20 to 0x37 => All Core Chiplets + 0x38 to 0x3F => Multicast Operation + </description> + <id>CHIPLET_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t> + <default>0xFF</default> + </uint8_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_REQUIRED_SYNCH_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>MAX_ALLOWED_DIMM_FREQ</id> + <attribute> <description> - Maximum frequency (in MHz) that this system can run the DIMMs at. - There are 5 possible values determined by the dimm configuration. - For configurations which have mixed rank configurations, the lowest - frequency based on ranks of either DIMM is chosen. For example if - there was a 1R and a 2R DIMM installed, and 1R dual drop was a lower - max freq than 2R dual drop, then the 1R max freq would be the max allowed. - [0]=One rank, single drop - [1]=Two rank, single drop - [2]=Four rank, single drop - [3]=One rank, dual drop - [4]=Two rank, dual drop - A value of zero would indicate an unsupported configuration. + Physical entity path of the target's associated pervasive target </description> - <simpleType> - <uint32_t> - <default>2400,2400,2400,2400,2400</default> - </uint32_t> - <array>5</array> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_MAX_ALLOWED_DIMM_FREQ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <id>PARENT_PERVASIVE</id> + <nativeType> + <name>EntityPath</name> + </nativeType> <persistency>non-volatile</persistency> - <readable/> -</attribute> + <readable></readable> + <virtual></virtual> + <no_export/> + </attribute> -<!--<attribute> - <id>PROC_DPLL_DIVIDER</id> + <attribute> <description> - The product of the DPLL internal prescalar divide (CD_DIV124_DC) - and the output divider(CD_DPLLOUT124_DC). This estalishes the step size of - the DPLL in terms of this number divided into the processor reference clock. - - Platform default: 8 + Do we support dynamically updating memory voltages? + 0 = no, 1 = yes </description> + <id>SUPPORTS_DYNAMIC_MEM_VOLT</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_PROC_DPLL_DIVIDER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute>--> + </attribute> -<attribute> - <id>AVSBUS_FREQUENCY</id> + <attribute> <description> - AVSBus Clock Frequency (binary in KHz) - - Consumer: p9_ocb_init.C - - Overridden by the Machine Readable Workbook. - - If default of 0 is read, HWP will set AVSBus frequency to 1MHz. + This field is of the form "vendor,name" where the name indicates + the family of the systems. The textual portion of the string has + a maximum length of 63 characters to accommodate a terminating NULL. + Both vendor and name fields are lower case US ASCII. No special + characters other than ",", "-", and "+" as described below should + be used in the string. </description> + <id>SYSTEM_FAMILY</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <string> + <default>ibm,p9</default> + <sizeInclNull>64</sizeInclNull> + </string> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_AVSBUS_FREQUENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> -</attribute> + </attribute> -<attribute> - <id>VDD_AVSBUS_BUSNUM</id> + <attribute> <description> - Defines the AVSBus (0 or 1) which has the core VDD rail VRM - - Producer: Machine Readable Workbook - Consumers: p9_set_evid; - p9_set_voltage (tool); - p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE + This field is of the form ?vendor,type? where the type indicates + a type of system within the System Family. The textual portion of + the string has a maximum length of 63 characters to accommodate a + terminating NULL. Both vendor and name fields are lower case US + ASCII. No special characters other than ",", "-", and "+" as described + below should be used in the string. If identification of specific + models within a system type is desired, "-model" should be appended + to the end of the name. The "-model" portion is optional and could be + used to identify the packaging, specific model numbers, etc. + NOTE: No Hostboot code should ever key off of this value. </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VDD_AVSBUS_BUSNUM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <id>SYSTEM_TYPE</id> <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>VDN_AVSBUS_BUSNUM</id> - <description> - Defines the AVSBus (0 or 1) which has the chip VDN rail VRM - - Producer: Machine Readable Workbook - Consumers: p9_set_evid; - p9_set_voltage (tool); - p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE - </description> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <string> + <default>ibm,miscopenpower</default> + <sizeInclNull>64</sizeInclNull> + </string> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VDN_AVSBUS_BUSNUM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>VDD_AVSBUS_RAIL</id> - <description> - Defines the AVSBus rail selector number (0 - 15) for the VDD VRM on the bus - defined by ATTR_AVSBUS_VDD_BUSNUM. + </attribute> - Producer: Machine Readable Workbook - Consumers: p9_set_evid; - p9_set_voltage (tool); - p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE + <attribute> + <description>TOD CHIP DATA for each CHIP + The size of the TOD CHIP DATA must be equal to the sizeof(TodChipData) </description> + <id>TOD_CPU_DATA</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <array>44</array> + <uint8_t></uint8_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VDD_AVSBUS_RAIL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>VDN_AVSBUS_RAIL</id> + <attribute> <description> - Defines the AVSBus rail selector number (0 - 15) for the VDN VRM on the bus - defined by ATTR_AVSBUS_VDN_BUSNUM. - - Producer: Machine Readable Workbook - Consumers: - p9_set_avsbus_voltage (tool); - p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE - </description> + STOP levels supported at runtime (sent to Host via HDAT): + Bit 0: STOP0 Supported - Quiesce thread only + Bit 1: STOP1 Supported - P8 Nap + Bit 2: STOP2 Supported - P8 Fast Sleep + Bit 3: STOP3 Supported - P8 Fast Sleep using iVRMs + Bit 4: STOP4 supported - P8 Deep Sleep + Bit 5: STOP5 Supported - WOF-friendly "Instant on" + Bit 6,7: Reserved + Bit 8: STOP8 supported - Half Quad Sleep + Bit 9: STOP9 supported - P8 Fast Winkle + Bit 10: Reserved + Bit 11: STOP11 supported - P8 Deep Winkle + Bit 12-15 : Reserved + Bits 16..31 - Reserved + </description> + <id>SUPPORTED_STOP_STATES</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint32_t> + <default>0x80000000</default> + </uint32_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VDN_AVSBUS_RAIL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>VCS_AVSBUS_RAIL</id> - <description> - Defines the AVSBus rail selector number (0 - 15) for the VCS VRM on the bus - defined by ATTR_AVSBUS_VCS_BUSNUM. + </attribute> - Producer: Machine Readable Workbook - Consumers: - p9_set_avsbus_voltage (tool); - p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE + <attribute> + <description>PCIE Lane Equalization values for each PHB + Creator: MRW + Purpose: Holds settings which are loaded into the HW to optimize the + PCIE lane signal eye between the chips + PCIE Gen3 endpoints + Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ + value for each of its 16 lanes. Each value is a uint16 formatted as + follows: + Bit 0:3 - up_rx_hint (bit 0 reserved) + Bit 4:7 - up_tx_preset + Bit 8:11 - dn_rx_hint (bit 0 reserved) + Bit 12:15 - dn_tx_preset </description> + <id>PROC_PCIE_LANE_EQUALIZATION_GEN3</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <array>16</array> + <uint16_t> + <default> + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777 + </default> + </uint16_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VCS_AVSBUS_RAIL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>VCS_AVSBUS_BUSNUM</id> - <description> - Defines the AVSBus (0 or 1) which has the core VCS rail VRM + </attribute> - Producer: Machine Readable Workbook - Consumers: p9_set_evid; - p9_set_voltage (tool); - p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE + <attribute> + <description>PCIE Lane Equalization values for each PHB + Creator: MRW + Purpose: Holds settings which are loaded into the HW to optimize the + PCIE lane signal eye between the chips + PCIE Gen4 endpoints + Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ + value for each of its 16 lanes. Each value is a uint16 formatted as + follows: + Bit 0:3 - up_rx_hint (bit 0 reserved) + Bit 4:7 - up_tx_preset + Bit 8:11 - dn_rx_hint (bit 0 reserved) + Bit 12:15 - dn_tx_preset </description> + <id>PROC_PCIE_LANE_EQUALIZATION_GEN4</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <array>16</array> + <uint16_t> + <default> + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777, + 0x7777,0x7777,0x7777,0x7777 + </default> + </uint16_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VCS_AVSBUS_BUSNUM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>VCS_I2C_BUSNUM</id> - <description> - Defines the I2C bus number (0 - 15) that has the VCS VRM. + </attribute> - Producer: Machine Readable Workbook - Consumers: p9_set_evid; - sp9_set_voltage (tool) - </description> + <attribute> + <description>Ordinal ID of a target</description> + <id>ORDINAL_ID</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint32_t> + <default>0xFFFFFFFF</default> + </uint32_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VCS_I2C_BUSNUM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + <writeable></writeable> + <no_export/> + </attribute> -<attribute> - <id>VDD_BOOT_VOLTAGE</id> + <attribute> <description> - Voltage (binary in 1mV units) to apply to the VDD VRM for booting. Value - chosen is system dependent and is a combination of the part's Vital Product - Data (VPD) (typically the PowerSave value) and the minimum allowed for - correct operation of the fabric bus. - - Producer: p9_setup_evid (first pass) - - Consumer: p9_setup_evid (second pass) + Raw value of system MTM </description> + <id>RAW_MTM</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <string> + <sizeInclNull>64</sizeInclNull> + </string> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VDD_BOOT_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <writeable></writeable> + </attribute> -<attribute> - <id>VCS_BOOT_VOLTAGE</id> + <attribute> <description> - Voltage (binary in 1mV units) to apply to the VCS VRM for booting. Value - chosen is system dependent and is a combination of the part's Vital Product - Data (VPD) (typically the PowerSave value) and the minimum allowed for - correct operation of the fabric bus. - - Producer: p9_setup_evid (first pass) - - Consumer: p9_setup_evid (second pass) + Used to tell INTRP code whether to use the XIVE HW Reset + or a software based reset. + 0 = Software based reset + 1 = XIVE HW reset </description> + <id>XIVE_HW_RESET</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VCS_BOOT_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + </attribute> -<attribute> - <id>SPIPSS_FREQUENCY</id> + <attribute> <description> - SPIPSS Clock Frequency (binary in KHz) - - Valid range: 500KHz to 2500KHz - - Consumer: p8_pss_init - - Overridden by the Machine Readable Workbook. - - If default of 0 is read, HWP will set SPIPSS frequency to 10MHz. + Used to tell I2C code whether to run + I2C Engine 2 Port 0 in diag mode or not + 0 = Use Diag Mode + 1 = Disable Diag Mode </description> + <id>DISABLE_I2C_ENGINE2_PORT0_DIAG_MODE</id> + <persistency>non-volatile</persistency> + <readable></readable> <simpleType> - <uint32_t> - </uint32_t> + <uint8_t> + <default>1</default> + </uint8_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_SPIPSS_FREQUENCY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> -</attribute> - -<attribute> - <id>PM_APSS_CHIP_SELECT</id> - <description> - Defines which of the PSS chip selects (0 or 1) that the APSS is connected + </attribute> - Provided by the Machine Readable Workbook. - Consumer: p9_pm_pss_init - </description> + <attribute> + <description>Save state of the sfc driver flash workarounds for runtime</description> + <id>PNOR_FLASH_WORKAROUNDS</id> + <persistency>volatile-zeroed</persistency> + <readable></readable> <simpleType> - <uint8_t> - </uint8_t> + <uint32_t> + <default>0</default> + </uint32_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_PM_APSS_CHIP_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + <writeable></writeable> + </attribute> -<enumerationType> - <id>PM_APSS_CHIP_SELECT</id> - <description>Enumeration for the ATTR_PM_APSS_CHIP_SELECT</description> + <enumerationType> + <default>NA</default> + <description>Enumeration indicating the target's class</description> <enumerator> - <name>NONE</name> - <value>0xFF</value> + <name>NA</name> + <value>0</value> </enumerator> <enumerator> - <name>CS0</name> - <value>0x00</value> + <name>CARD</name> + <value>1</value> </enumerator> - <enumerator> - <name>CS1</name> - <value>0x01</value> + <enumerator> + <name>ENC</name> + <value>2</value> </enumerator> -</enumerationType> - -<attribute> - <id>FREQ_EXT_BIAS_ULTRATURBO</id> - <description> - UltraTurbo Frequency Bias - % of bias (signed twos complement in 0.5 percent - steps) used in calculating the frequency associated with a Pstate. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC - CME Quad Pstate Region (CQPR) for CM Quad Manager - - Platform default: 0 - </description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_EXT_BIAS_ULTRATURBO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>FREQ_EXT_BIAS_TURBO</id> - <description> - Turbo Frequency Bias - % of bias (signed twos complement in 0.5 percent - steps) used in calculating the frequency associated with a Pstate. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC - CME Quad Pstate Region (CQPR) for CM Quad Manager - - Platform default: 0 - </description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_EXT_BIAS_TURBO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>FREQ_EXT_BIAS_NOMINAL</id> - <description> - Nominal Frequency Bias - % of bias (signed twos complement in 0.5 percent - steps) used in calculating the frequency associated with a Pstate. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC - CME Quad Pstate Region (CQPR) for CM Quad Manager - - Platform default: 0 - </description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_EXT_BIAS_NOMINAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>FREQ_EXT_BIAS_POWERSAVE</id> - <description> - PowerSave Frequency Bias - % of bias (signed twos complement in 0.5 percent - steps) used in calculating the frequency associated with a Pstate. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC - CME Quad Pstate Region (CQPR) for CM Quad Manager - - Platform default: 0 - </description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_EXT_BIAS_POWERSAVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>VOLTAGE_VDD_BIAS_ULTRATURBO</id> - <description> - UltraTurbo VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent - steps) that is applied to the UltraTurbo VPD point used in calculating the - the Global Pstate values. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC - - Platform default: 0 - </description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_VDD_BIAS_ULTRATURBO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>VOLTAGE_VDD_BIAS_TURBO</id> - <description> - Turbo VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent - steps) that is applied to the UltraTurbo VPD point used in calculating the - the Global Pstate values. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC - - Platform default: 0 - </description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_VDD_BIAS_TURBO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>VOLTAGE_VDD_BIAS_NOMINAL</id> - <description> - Nominal VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent - steps) that is applied to the UltraTurbo VPD point used in calculating the - the Global Pstate values. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC + <enumerator> + <name>CHIP</name> + <value>3</value> + </enumerator> + <enumerator> + <name>UNIT</name> + <value>4</value> + </enumerator> + <enumerator> + <name>DEV</name> + <value>5</value> + </enumerator> + <enumerator> + <name>SYS</name> + <value>6</value> + </enumerator> + <enumerator> + <name>LOGICAL_CARD</name> + <value>7</value> + </enumerator> + <enumerator> + <name>BATTERY</name> + <value>8</value> + </enumerator> + <enumerator> + <name>LED</name> + <value>9</value> + </enumerator> + <enumerator> + <name>SP</name> + <value>10</value> + </enumerator> + <enumerator> + <name>MAX</name> + <value>11</value> + </enumerator> + <id>CLASS</id> + </enumerationType> - Platform default: 0 - </description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_VDD_BIAS_NOMINAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <enumerationType> + <default>NA</default> + <description>Enumeration indicating the target's type</description> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>SYS</name> + <value>1</value> + </enumerator> + <enumerator> + <name>NODE</name> + <value>2</value> + </enumerator> + <enumerator> + <name>DIMM</name> + <value>3</value> + </enumerator> + <enumerator> + <name>MEMBUF</name> + <value>4</value> + </enumerator> + <enumerator> + <name>PROC</name> + <value>5</value> + </enumerator> + <enumerator> + <name>EX</name> + <value>6</value> + </enumerator> + <enumerator> + <name>CORE</name> + <value>7</value> + </enumerator> + <enumerator> + <name>L2</name> + <value>8</value> + </enumerator> + <enumerator> + <name>L3</name> + <value>9</value> + </enumerator> + <enumerator> + <name>L4</name> + <value>10</value> + </enumerator> + <enumerator> + <name>MCS</name> + <value>11</value> + </enumerator> + <enumerator> + <name>MBA</name> + <value>13</value> + </enumerator> + <enumerator> + <name>XBUS</name> + <value>14</value> + </enumerator> + <enumerator> + <name>ABUS</name> + <value>15</value> + </enumerator> + <enumerator> + <name>PCI</name> + <value>16</value> + </enumerator> + <enumerator> + <name>DPSS</name> + <value>17</value> + </enumerator> + <enumerator> + <name>APSS</name> + <value>18</value> + </enumerator> + <enumerator> + <name>OCC</name> + <value>19</value> + </enumerator> + <enumerator> + <name>PSI</name> + <value>20</value> + </enumerator> + <enumerator> + <name>FSP</name> + <value>21</value> + </enumerator> + <enumerator> + <name>PNOR</name> + <value>22</value> + </enumerator> + <enumerator> + <name>OSC</name> + <value>23</value> + </enumerator> + <enumerator> + <name>TODCLK</name> + <value>24</value> + </enumerator> + <enumerator> + <name>CONTROL_NODE</name> + <value>25</value> + </enumerator> + <enumerator> + <name>OSCREFCLK</name> + <value>26</value> + </enumerator> + <enumerator> + <name>OSCPCICLK</name> + <value>27</value> + </enumerator> + <enumerator> + <name>REFCLKENDPT</name> + <value>28</value> + </enumerator> + <enumerator> + <name>PCICLKENDPT</name> + <value>29</value> + </enumerator> + <enumerator> + <name>NX</name> + <value>30</value> + </enumerator> + <enumerator> + <name>PORE</name> + <value>31</value> + </enumerator> + <enumerator> + <name>PCIESWITCH</name> + <value>32</value> + </enumerator> + <enumerator> + <name>CAPP</name> + <value>33</value> + </enumerator> + <enumerator> + <name>FSI</name> + <value>34</value> + </enumerator> + <enumerator> + <name>EQ</name> + <value>35</value> + </enumerator> + <enumerator> + <name>MCA</name> + <value>36</value> + </enumerator> + <enumerator> + <name>MCBIST</name> + <value>37</value> + </enumerator> + <enumerator> + <name>MI</name> + <value>38</value> + </enumerator> + <enumerator> + <name>DMI</name> + <value>39</value> + </enumerator> + <enumerator> + <name>OBUS</name> + <value>40</value> + </enumerator> + <enumerator> + <name>NV</name> + <value>41</value> + </enumerator> + <enumerator> + <name>SBE</name> + <value>42</value> + </enumerator> + <enumerator> + <name>PPE</name> + <value>43</value> + </enumerator> + <enumerator> + <name>PERV</name> + <value>44</value> + </enumerator> + <enumerator> + <name>PEC</name> + <value>45</value> + </enumerator> + <enumerator> + <name>PHB</name> + <value>46</value> + </enumerator> + <enumerator> + <name>SYSREFCLKENDPT</name> + <value>47</value> + </enumerator> + <enumerator> + <name>MFREFCLKENDPT</name> + <value>48</value> + </enumerator> + <enumerator> + <name>TPM</name> + <value>49</value> + </enumerator> + <enumerator> + <name>SP</name> + <value>50</value> + </enumerator> + <enumerator> + <name>UART</name> + <value>51</value> + </enumerator> + <enumerator> + <name>PS</name> + <value>52</value> + </enumerator> + <enumerator> + <name>FAN</name> + <value>53</value> + </enumerator> + <enumerator> + <name>VRM</name> + <value>54</value> + </enumerator> + <enumerator> + <name>USB</name> + <value>55</value> + </enumerator> + <enumerator> + <name>ETH</name> + <value>56</value> + </enumerator> + <enumerator> + <name>PANEL</name> + <value>57</value> + </enumerator> + <enumerator> + <name>BMC</name> + <value>58</value> + </enumerator> + <enumerator> + <name>FLASH</name> + <value>59</value> + </enumerator> + <enumerator> + <name>SEEPROM</name> + <value>60</value> + </enumerator> + <enumerator> + <name>TMP</name> + <value>61</value> + </enumerator> + <enumerator> + <name>GPIO_EXPANDER</name> + <value>62</value> + </enumerator> + <enumerator> + <name>POWER_SEQUENCER</name> + <value>63</value> + </enumerator> + <enumerator> + <name>RTC</name> + <value>64</value> + </enumerator> + <enumerator> + <name>FANCTLR</name> + <value>65</value> + </enumerator> + <enumerator> + <name>OBUS_BRICK</name> + <value>66</value> + </enumerator> + <enumerator> + <name>NPU</name> + <value>67</value> + </enumerator> + <enumerator> + <name>MC</name> + <value>68</value> + </enumerator> + <enumerator> + <name>TEST_FAIL</name> + <value>69</value> + </enumerator> + <enumerator> + <name>MFREFCLK</name> + <value>70</value> + </enumerator> + <enumerator> + <name>LAST_IN_RANGE</name> + <value>71</value> + </enumerator> + <id>TYPE</id> + </enumerationType> -<attribute> - <id>VOLTAGE_VDD_BIAS_POWERSAVE</id> - <description> - PowerSave VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent - steps) that is applied to the UltraTurbo VPD point used in calculating the - the Global Pstate values. + <enumerationType> + <default>NA</default> + <description>Enumeration indicating the target's model</description> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>RESERVED</name> + <value>16</value> + </enumerator> + <enumerator> + <name>VENICE</name> + </enumerator> + <enumerator> + <name>MURANO</name> + </enumerator> + <enumerator> + <name>NAPLES</name> + </enumerator> + <enumerator> + <name>NIMBUS</name> + </enumerator> + <enumerator> + <name>CUMULUS</name> + </enumerator> + <enumerator> + <name>CENTAUR</name> + <value>48</value> + </enumerator> + <enumerator> + <name>JEDEC</name> + <value>80</value> + </enumerator> + <enumerator> + <name>CDIMM</name> + </enumerator> + <enumerator> + <name>POWER8</name> + <value>112</value> + </enumerator> + <enumerator> + <name>POWER9</name> + <value>144</value> + </enumerator> + <enumerator> + <name>CECTPM</name> + </enumerator> + <enumerator> + <name>BMC</name> + </enumerator> + <enumerator> + <name>AST2500</name> + </enumerator> + <id>MODEL</id> + </enumerationType> - Producer: Attribute Overrides by Lab/Mfg Characterization Team + <enumerationType> + <default>NA</default> + <description>Enumeration indicating the target's engine type</description> + <enumerator> + <name>NA</name> + <value>0</value> + </enumerator> + <enumerator> + <name>ENGINE_IIC</name> + <value>1</value> + </enumerator> + <enumerator> + <name>ENGINE_SCOM</name> + <value>2</value> + </enumerator> + <id>ENGINE_TYPE</id> + </enumerationType> - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC + <enumerationType> + <default>NO_MASTER</default> + <description>Enumeration indicating the master's FSI type</description> + <enumerator> + <name>MFSI</name> + <value>0</value> + </enumerator> + <enumerator> + <name>CMFSI</name> + <value>1</value> + </enumerator> + <enumerator> + <name>NO_MASTER</name> + <value>2</value> + </enumerator> + <id>FSI_MASTER_TYPE</id> + </enumerationType> - Platform default: 0 + <enumerationType> + <description>Enumeration indicating the services that are concerned + with target changes (ie, via HCDB change). + The values can be combined using a bitwise 'OR'. </description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_VDD_BIAS_POWERSAVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>VOLTAGE_VCS_BIAS</id> - <description> - VCS Voltage Bias - % of bias (signed twos complement in 0.5 percent - steps) that is applied to the VCS value stored in the UltraTurbo VPD - point for setting the VCS rail. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team + <enumerator> + <name>GARD</name> + <value>0x00000001</value> + </enumerator> + <enumerator> + <name>MEMDIAG</name> + <value>0x00000002</value> + </enumerator> + <enumerator> + <name>PSIDIAG</name> + <value>0x00000004</value> + </enumerator> + <enumerator> + <name>DIAG_MASK</name> + <value>0x00000006</value> + </enumerator> + <enumerator> + <name>HOSTSVC_HBEL</name> + <value>0x00000008</value> + </enumerator> + <id>HWAS_CHANGED_BIT</id> + </enumerationType> - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC + <enumerationType> + <description>Enumeration indicating the PROC_EPS_TABLE_TYPE</description> + <enumerator> + <name>EPS_TYPE_LE</name> + <value>1</value> + </enumerator> + <enumerator> + <name>EPS_TYPE_HE</name> + <value>2</value> + </enumerator> + <id>PROC_EPS_TABLE_TYPE</id> + </enumerationType> - Platform default: 0 - </description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_VCS_BIAS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <enumerationType> + <description>Enumeration indicating the PROC_FABRIC_PUMP_MODE</description> + <enumerator> + <name>MODE1</name> + <value>1</value> + </enumerator> + <enumerator> + <name>MODE2</name> + <value>2</value> + </enumerator> + <id>PROC_FABRIC_PUMP_MODE</id> + </enumerationType> -<attribute> - <id>VOLTAGE_VDN_BIAS</id> + <enumerationType> + <default>UNKNOWN</default> <description> - VDN Voltage Bias - % of bias (signed twos complement in 0.5 percent - steps) that is applied to the VDN value stored in the VPD for setting the - VDN rail. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC - - Platform default: 0 + Enumeration indicating what kind of payload is to be started </description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_VDN_BIAS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>VOLTAGE_INT_VDD_BIAS</id> - <description> - TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS WELL - AS THE IVRM VOLTAGE CALCULATION PROCESS - Internal VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent - steps) that is applied to the Local Pstate voltage *after* the - ATTR_VOLTAGE_VDD_BIAS bias have been applied. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC - CME Quad Pstate Region (CQPR) for CM Quad Manager + <enumerator> + <name>UNKNOWN</name> + <value>0</value> + </enumerator> + <enumerator> + <name>PHYP</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SAPPHIRE</name> + <value>2</value> + </enumerator> + <enumerator> + <name>NONE</name> + <value>3</value> + </enumerator> + <id>PAYLOAD_KIND</id> + </enumerationType> - Platform default: 0 + <enumerationType> + <id>MNFG_FLAG</id> + <description>Enumeration indicating the mnfg flags + that are set by the user. The values can be + combined using a bitwise 'OR'. The values will + need to be kept in sync with the FAPI + enumerator values. Also the enumeration type + is used by the ATTR_MNFG_FLAGS attribute. Should + note that the MNFG_FLAG values are of type uint32_t </description> - <simpleType> - <int32_t> - </int32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_INT_VDD_BIAS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>STOP4_DISABLE</id> - <description> - Control CME response to execution of PowerPC STOP instruction - - if OFF, treat STOP4 as STOP4 - if ON, treat STOP4 as STOP2 + <enumerator> + <!-- Use default mfg error thresholds and reporting values --> + <name>THRESHOLDS</name> + <value>0x00000001</value> + </enumerator> + <enumerator> + <!-- Enable AVP execution --> + <name>AVP_ENABLE</name> + <value>0x00000002</value> + </enumerator> + <enumerator> + <!-- Enable HDAT AVPs** --> + <name>HDAT_AVP_ENABLE</name> + <value>0x00000004</value> + </enumerator> + <enumerator> + <!-- All SRCs are terminating (CEC hardware/procedural) --> + <name>SRC_TERM</name> + <value>0x00000008</value> + </enumerator> + <enumerator> + <!-- Enable IPL memory diagnostics to report memory CE --> + <name>IPL_MEMORY_CE_CHECKING</name> + <value>0x00000010</value> + </enumerator> + <enumerator> + <!-- Enable Fast Background Scrub --> + <name>FAST_BACKGROUND_SCRUB</name> + <value>0x00000020</value> + </enumerator> + <enumerator> + <!-- Test DRAM Repairs --> + <name>TEST_DRAM_REPAIRS</name> + <value>0x00000040</value> + </enumerator> + <enumerator> + <!-- Disable Dram Repairs --> + <name>DISABLE_DRAM_REPAIRS</name> + <value>0x00000080</value> + </enumerator> + <enumerator> + <!-- Enable exhaustive pattern test --> + <name>ENABLE_EXHAUSTIVE_PATTERN_TEST</name> + <value>0x00000100</value> + </enumerator> + <enumerator> + <!-- Enable standard pattern test --> + <name>ENABLE_STANDARD_PATTERN_TEST</name> + <value>0x00000200</value> + </enumerator> + <enumerator> + <!-- Enable minimum pattern test --> + <name>ENABLE_MINIMUM_PATTERN_TEST</name> + <value>0x00000400</value> + </enumerator> + <enumerator> + <!-- Disable Fabric eRepair --> + <name>DISABLE_FABRIC_eREPAIR</name> + <value>0x00000800</value> + </enumerator> + <enumerator> + <!-- Disable Memory eRepair --> + <name>DISABLE_MEMORY_eREPAIR</name> + <value>0x00001000</value> + </enumerator> + <enumerator> + <!-- Fabric deploy lane spares --> + <name>FABRIC_DEPLOY_LANE_SPARES</name> + <value>0x00002000</value> + </enumerator> + <enumerator> + <!-- DMI deploy lane spares --> + <name>DMI_DEPLOY_LANE_SPARES</name> + <value>0x00004000</value> + </enumerator> + <enumerator> + <!-- Forcibly run PSI diagnostics --> + <name>PSI_DIAGNOSTIC</name> + <value>0x00008000</value> + </enumerator> + <enumerator> + <!-- Brazos Wrap Config --> + <name>BRAZOS_WRAP_CONFIG</name> + <value>0x00010000</value> + </enumerator> + <enumerator> + <!-- FSP is responsible for updating Processor SBE Image --> + <name>FSP_UPDATE_SBE_IMAGE</name> + <value>0x00020000</value> + </enumerator> + <enumerator> + <!-- Update both sides of SBE Image if update is needed --> + <name>UPDATE_BOTH_SIDES_OF_SBE</name> + <value>0x00040000</value> + </enumerator> +</enumerationType> - Producer: ??? + <enumerationType> + <description>Enumeration indicating the BAR size + used with ATTR_PROC_NPU_MMIO_BAR_SIZE</description> + <enumerator> + <name>2_MB</name> + <value>0x0000000000200000</value> + </enumerator> + <enumerator> + <name>1_MB</name> + <value>0x0000000000100000</value> + </enumerator> + <enumerator> + <name>512_KB</name> + <value>0x0000000000080000</value> + </enumerator> + <enumerator> + <name>256_KB</name> + <value>0x0000000000040000</value> + </enumerator> + <enumerator> + <name>128_KB</name> + <value>0x0000000000020000</value> + </enumerator> + <enumerator> + <name>64_KB</name> + <value>0x0000000000010000</value> + </enumerator> + <id>NPU_MMIO_BAR_SIZE</id> + </enumerationType> - Consumer: p8_hcd_image_build.C + <enumerationType> + <description>Enumeration indicating which chip should be used as the PROC_SELECT_BOOT_MASTER</description> + <enumerator> + <name>PRIMARY</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SECONDARY</name> + <value>2</value> + </enumerator> + <id>PROC_SELECT_BOOT_MASTER</id> + </enumerationType> - Platform default: OFF - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_STOP4_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> -</attribute> + <enumerationType> + <description>Enumeration indicating which SEEPROM image should be used for the boot master</description> + <enumerator> + <name>FIRST</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SECOND</name> + <value>2</value> + </enumerator> + <id>PROC_SELECT_SEEPROM_IMAGE</id> + </enumerationType> -<attribute> - <id>STOP5_DISABLE</id> - <description> Control CME response to execution of PowerPC STOP instruction - if OFF, treat STOP5 as STOP5 - if ON, treat STOP5 as STOP4 + <enumerationType> + <description>Enumeration indicating which SEEPROM image should be used to boot a processor</description> + <enumerator> + <name>FIRST</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SECOND</name> + <value>2</value> + </enumerator> + <id>PROC_SELECT_BOOT_SEEPROM_IMAGE</id> + </enumerationType> - Producer: ??? + <enumerationType> + <description>Enumeration indicating which _PBIEX_ASYNC_SEL should be use</description> + <enumerator> + <name>SEL0</name> + <value>0</value> + </enumerator> + <enumerator> + <name>SEL1</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SEL2</name> + <value>2</value> + </enumerator> + <id>PROC_PBIEX_ASYNC_SEL</id> + </enumerationType> - Consumer: p8_hcode_image_build.C + <enumerationType> + <description>Enumeration of CDM_POLICIES flags</description> + <enumerator> + <description> + MFG_Guard policy: + Used in MFG only to prevent and disable the following: + . Storing or creation of new Guard records from Diagno`stic or other + faults through error logs. This is all domains, CEC + processor/memory, VPD, FSP, etc. + . Storing or creation of Manual Guard record from user. + NOTE: this does not stop FCO. + . Using an already stored System or Manual Guard record from + deconfiguring resources. This is all domains, CEC + processor/memory, VPD, FSP, etc. + </description> + <name>MANUFACTURING_DISABLED</name> + <value>0x01</value> + </enumerator> + <enumerator> + <description> + Predictive_Guard policy: + Used in Field or development to prevent and disable the following: + . Storing or creation of new Guard records from diagnostics or other + faults through error logs with the error_type of Predictive. + . Using an already stored System Guard record with error_type of + Predictive from deconfiguring resources. + </description> + <name>PREDICTIVE_DISABLED</name> + <value>0x02</value> + </enumerator> + <id>CDM_POLICIES</id> + </enumerationType> - Platform default: OFF + <enumerationType> + <description>Enumeration indicating the multi scome + buffer size. The values can be combined using a + bitwise 'OR'. The values will need to be kept + in sync with the FAPI enumerator values. Also + the enumeration type is used by the + ATTR_MULTI_SCOM_BUFFER_MAX_SIZE. Should + note that the MULTI_SCOM_BUFFER_MAX_SIZE values + are of type uint32_t </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_STOP5_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_1KB</name> + <value>0x00000400</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_2KB</name> + <value>0x00000800</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_4KB</name> + <value>0x00001000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_8KB</name> + <value>0x00002000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_16KB</name> + <value>0x00004000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_32KB</name> + <value>0x00008000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_64KB</name> + <value>0x00010000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_128KB</name> + <value>0x00020000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_256KB</name> + <value>0x00040000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_512KB</name> + <value>0x00080000</value> + </enumerator> + <enumerator> + <name>MULTI_SCOM_BUFFER_SIZE_1MB</name> + <value>0x00100000</value> + </enumerator> + <id>MULTI_SCOM_BUFFER_MAX_SIZE_BIT</id> + </enumerationType> -<attribute> - <id>STOP8_DISABLE</id> + <enumerationType> + <default>NOT_MASTER</default> <description> - Control CME response to execution of PowerPC STOP instruction - - if OFF, treat STOP8 as STOP8 - if ON, treat STOP8 as STOP4 - - Producer: ??? - - Consumer: p8_hcd_image_build.C - - Platform default: OFF + Enumeration indicating the role of proc as master/alt_master/not_master </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_STOP8_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> -</attribute> - -<attribute> - <id>STOP11_DISABLE</id> - <description> - Control CME response to execution of PowerPC STOP instruction - - if OFF, treat STOP8 as STOP11 - if ON, treat STOP8 as STOP8 - - Producer: ??? - - Consumer: p8_hcd_image_build.C + <enumerator> + <name>ACTING_MASTER</name> + <value>0</value> + </enumerator> + <enumerator> + <name>MASTER_CANDIDATE</name> + <value>1</value> + </enumerator> + <enumerator> + <name>NOT_MASTER</name> + <value>2</value> + </enumerator> + <id>PROC_MASTER_TYPE</id> + </enumerationType> - Platform default: OFF - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_STOP11_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> -</attribute> + <enumerationType> + <description>Enumeration of RECONFIGURE_LOOP flags</description> + <enumerator> + <description> + Indicates HW has been deconfigured + </description> + <name>DECONFIGURE</name> + <value>0x01</value> + </enumerator> + <enumerator> + <description> + Indicates a bad DQ bit was set in the BadDqBitmap + </description> + <name>BAD_DQ_BIT_SET</name> + <value>0x02</value> + </enumerator> + <enumerator> + <description> + An RCD parity error has been detected + </description> + <name>RCD_PARITY_ERROR</name> + <value>0x04</value> + </enumerator> + <id>RECONFIGURE_LOOP</id> + </enumerationType> -<attribute> - <id>SYSTEM_IVRM_DISABLE</id> + <enumerationType> + <default>NON_MASTER</default> <description> - Disables IVRM enablement in the system - - Producer: Override - - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC - CME Quad Pstate Region (CQPR) for CM Quad Manager - - Platform default: OFF + Enumeration indicating what role this chip has in tod topology </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_IVRM_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <enumerator> + <name>NON_MASTER</name> + <value>0</value> + </enumerator> + <enumerator> + <name>PRIMARY</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SECONDARY</name> + <value>2</value> + </enumerator> + <id>TOD_ROLE</id> + </enumerationType> -<attribute> - <id>SYSTEM_WOF_DISABLE</id> + <enumerationType> + <default>OFF</default> <description> - Disables Work Load Optimized Frequency (WOF) algoritms to - modify frequency based on active core count and other inputs. - - OFF: Will enable WOF given all validity checks pass. If - validity checks fail, WOF will be disabled for - the present IPL. - ON: Will disable WOF. - OFF_SKIP_DD: Same as OFF but skips any validity checking of the chip - design level (lab use only). - - Producer: Override - - Consumers: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE/OCC + Enumeration defining the type of power control requested </description> - <simpleType> - <uint8_t> - <default>OFF</default> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_WOF_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<enumerationType> - <id>SYSTEM_WOF_DISABLE</id> - <description> Enumeration for ATTR_SYSTEM_WOF_DISABLE</description> <enumerator> - <name>OFF</name> - <value>0x00</value> + <name>OFF</name> + <value>0</value> </enumerator> <enumerator> - <name>ON</name> - <value>0x01</value> + <name>POWER_DOWN</name> + <value>1</value> </enumerator> <enumerator> - <name>OFF_SKIP_DD</name> - <value>0x02</value> + <name>STR</name> + <value>2</value> </enumerator> -</enumerationType> + <enumerator> + <name>PD_AND_STR</name> + <value>3</value> + </enumerator> + <id>MSS_MRW_POWER_CONTROL_REQUESTED</id> + </enumerationType> -<attribute> - <id>WOF_ENABLE_FRATIO</id> + <enumerationType> + <default>NONE</default> <description> - If wof_enabled, defines the Frequency Ratio calculation performed. - (THIS IS NOT SUPPORTED IN P9 GA1!). - - Producer: MRWB - - Consumers: p9_hcode_image_build.C - + Enumeration defining the type of power control requested </description> - <simpleType> - <uint8_t> - <default>FIXED</default> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_WOF_ENABLE_FRATIO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<enumerationType> - <id>WOF_ENABLE_FRATIO</id> - <description>Enumeration for Work Load Optimized Frequency ratio</description> <enumerator> - <name>FIXED</name> - <value>0x00</value> + <name>OFF</name> + <value>0</value> </enumerator> <enumerator> - <name>STEPPED</name> - <value>0x01</value> + <name>POWER_DOWN</name> + <value>1</value> </enumerator> -</enumerationType> - + <enumerator> + <name>STR</name> + <value>2</value> + </enumerator> + <enumerator> + <name>PD_AND_STR</name> + <value>3</value> + </enumerator> + <id>MSS_MRW_IDLE_POWER_CONTROL_REQUESTED</id> + </enumerationType> -<attribute> - <id>WOF_ENABLE_VRATIO</id> + <enumerationType> + <default>NONE</default> <description> - If wof_enabled, defines the Voltage Ratio calculation performed. - THIS IS NOT SUPPORTED AT PRESENT. GA1 SUPPORT IS TBD). - - Producer: MRWB - - Consumers: p9_hcode_image_build.C - + Enumeration specifying a target's CEC degraded mode domain </description> - <simpleType> - <uint8_t> - <default>FIXED</default> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_WOF_ENABLE_VRATIO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<enumerationType> - <id>WOF_ENABLE_VRATIO</id> - <description>Enumeration for Work Load Optimized Frequency ratio</description> <enumerator> - <name>FIXED</name> - <value>0x00</value> + <name>NONE</name> + <value>0</value> </enumerator> <enumerator> - <name>STEPPED</name> - <value>0x01</value> + <name>CPU</name> + <value>1</value> </enumerator> -</enumerationType> + <enumerator> + <name>DIMM</name> + <value>2</value> + </enumerator> + <enumerator> + <name>FABRIC</name> + <value>3</value> + </enumerator> + <enumerator> + <name>MEM</name> + <value>4</value> + </enumerator> + <enumerator> + <name>IO</name> + <value>5</value> + </enumerator> + <enumerator> + <name>NODE</name> + <value>6</value> + </enumerator> + <enumerator> + <name>CLOCK</name> + <value>7</value> + </enumerator> + <enumerator> + <name>PSI</name> + <value>8</value> + </enumerator> + <enumerator> + <name>FSP</name> + <value>9</value> + </enumerator> + <enumerator> + <name>ALL</name> + <value>10</value> + </enumerator> + <id>CDM_DOMAIN</id> + </enumerationType> -<attribute> - <id>WOF_VRATIO_SELECT</id> + <enumerationType> + <default>NA</default> <description> - If wof_enabled AND ATTR_WOF_ENABLE_VRATIO = CALCULATED, this attribute - selects the Vratio calculation type. - ACTIVE_CORES: Vratio is the number of active cores to the - number of good cores - FULL: Vratio is Vaverage to Vclip(Fclip) where Vclip(Fclip) is - the normal interpolated regulator voltage (including load line uplife @ RDP - current) derated with presently measured Idd current (from the AVSBus) and - the loadline. - - - Producer: MRWB - - Consumers: p9_hcode_image_build.C - + Enumeration indication which Hot Plug Controllers are supported by + the current system. </description> - <simpleType> - <uint8_t> - <default>ACTIVE_CORES</default> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_WOF_VRATIO_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<enumerationType> - <id>WOF_VRATIO_SELECT</id> - <description>Enumeration for Work Load Optimized Frequency ratio</description> <enumerator> - <name>ACTIVE_CORES</name> - <value>0x00</value> + <name>NA</name> + <value>0</value> </enumerator> <enumerator> - <name>FULL</name> - <value>0x01</value> + <name>MAX5961</name> + <value>0x01</value> </enumerator> -</enumerationType> + <enumerator> + <name>PCA9551</name> + <value>0x02</value> + </enumerator> + <id>SUPPORTED_HOT_PLUG</id> + </enumerationType> + <enumerationType> + <description>Enum for FUSED_CORE_OPTION</description> + <enumerator> + <name>USING_DEFAULT_CORES</name> + <value>0</value> + </enumerator> + <enumerator> + <name>USING_NORMAL_CORES</name> + <value>1</value> + </enumerator> + <enumerator> + <name>USING_FUSED_CORES</name> + <value>2</value> + </enumerator> + <id>FUSED_CORE_OPTION</id> + </enumerationType> + <enumerationType> + <description>Enumeration for the ATTR_PM_APSS_CHIP_SELECT</description> + <enumerator> + <name>NONE</name> + <value>0xFF</value> + </enumerator> + <enumerator> + <name>CS0</name> + <value>0x00</value> + </enumerator> + <enumerator> + <name>CS1</name> + <value>0x01</value> + </enumerator> + <id>PM_APSS_CHIP_SELECT</id> + </enumerationType> -<enumerationType> - <id>WOF_POWER_LIMIT</id> + <enumerationType> <description>Enumeration to select WOF Power Limit</description> <enumerator> - <name>NOMINAL</name> - <value>0</value> + <name>NOMINAL</name> + <value>0</value> </enumerator> <enumerator> - <name>TURBO</name> - <value>1</value> + <name>TURBO</name> + <value>1</value> </enumerator> -</enumerationType> - -<attribute> <id>WOF_POWER_LIMIT</id> - <description> - System control to set the power limit for Workload Optimized - Frequency (WOF) algorithms. This is used to select the - proper VFRT tables. - Producer: TMGT - Consumers: FW that selects VFRT tables - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> + </enumerationType> -<attribute> - <id>WOF_TABLE_LID_NUMBER</id> + <enumerationType> <description> - LID id used to load tables for Workload Optimized - Frequency (WOF) algorithms. - Producer: TMGT - Consumers: FW that selects VFRT tables + Enumeration indicating the OFF setting for the core and cache chiplet + DD PFET controllers </description> - <simpleType> - <uint32_t> -<!-- @todo-RTC:172776-Get rid of default value that points to ZZ --> - <default>0x81E00440</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>SYS_VFRT_STATIC_DATA_ENABLE</id> - <description> - Enables pstate parameter block code to use the static system vfrt data - Consumer: p9_pstate_parameter_block.C - 0 = OFF, 1 = ON - Platform default: OFF - <!-- - @todo RTC 169662 at some point in the program, this default may be switched to - the opposite setting. However, coordination needs to occur with all CIs - as this will enable functions that may not be modeled across the board. - --> - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SYS_VFRT_STATIC_DATA_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <enumerator> + <name>NOOFF</name> + <value>0</value> + </enumerator> + <enumerator> + <name>ALLBUT1TO7OFF</name> + <value>1</value> + </enumerator> + <enumerator> + <name>ALLBUT2TO7OFF</name> + <value>2</value> + </enumerator> + <enumerator> + <name>ALLBUT3TO7OFF</name> + <value>3</value> + </enumerator> + <enumerator> + <name>ALLBUT4TO7OFF</name> + <value>4</value> + </enumerator> + <enumerator> + <name>ALLBUT5TO7OFF</name> + <value>5</value> + </enumerator> + <enumerator> + <name>ALLBUT6TO7OFF</name> + <value>6</value> + </enumerator> + <enumerator> + <name>ALLBUT7TO7OFF</name> + <value>7</value> + </enumerator> + <enumerator> + <name>ALLOFF</name> + <value>8</value> + </enumerator> + <id>PFET_VDD_VOFF_SEL</id> + </enumerationType> -<attribute> - <id>SYSTEM_PSTATES_MODE</id> + <enumerationType> <description> - Controls the mode of Pstate Protocol for testing. - ON: Boots the PGPE in "OCC Pstate Mode" but does NOT start the Pstate - protocol - - OFF: Does NOT boot the PGPE - AUTO: Boots the PGPE and automatically starts the Pstate protocol. - PMCR operations to move Pstates are honored - - Producer: Override - - Consumers: - p9_pstate_parameter_block and p9_pm_pstate_gpe_init + Enumeration indicating the OFF setting for the core and cache chiplet + VCS PFET controllers </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_PSTATES_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<enumerationType> - <id>SYSTEM_PSTATES_MODE</id> - <description>Enumeration for Work Load Optimized Frequency</description> <enumerator> - <name>ON</name> - <value>0x00</value> + <name>NOOFF</name> + <value>0</value> </enumerator> <enumerator> - <name>OFF</name> - <value>0x01</value> + <name>ALLBUT1TO7OFF</name> + <value>1</value> </enumerator> <enumerator> - <name>AUTO</name> - <value>0x02</value> + <name>ALLBUT2TO7OFF</name> + <value>2</value> </enumerator> -</enumerationType> - -<attribute> - <id>SYSTEM_RESCLK_STEP_DELAY</id> - <description> - Minimum delay (in nanoseconds) between resonant clock transition steps - - Producer: MRWB - - Consumers: p9_build_pstate_datablock -> - CME Quad Pstate Region (CQPR) for CM Quad Manager + <enumerator> + <name>ALLBUT3TO7OFF</name> + <value>3</value> + </enumerator> + <enumerator> + <name>ALLBUT4TO7OFF</name> + <value>4</value> + </enumerator> + <enumerator> + <name>ALLBUT5TO7OFF</name> + <value>5</value> + </enumerator> + <enumerator> + <name>ALLBUT6TO7OFF</name> + <value>6</value> + </enumerator> + <enumerator> + <name>ALLBUT7TO7OFF</name> + <value>7</value> + </enumerator> + <enumerator> + <name>ALLOFF</name> + <value>8</value> + </enumerator> + <id>PFET_VCS_VOFF_SEL</id> + </enumerationType> - Platform default: 0 - </description> - <simpleType> - <uint16_t> - </uint16_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_RESCLK_STEP_DELAY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + <enumerationType> + <default>NA</default> + <description>Enumeration defining special FAPI_POS values</description> + <enumerator> + <name>NA</name> + <value>0xFFFFFFFF</value> + </enumerator> + <id>FAPI_POS</id> + </enumerationType> -<!--<attribute> - <id>PFET_POWERUP_DELAY_NS</id> + <enumerationType> <description> - Time (in nanoseconds) between PFET controller steps (7 of them) when turning - the PFES ON - - Producer: MRWB - - Consumers: p9_pm_pfet_init - - Platform default: + Enumeration indicating the PROC_FABRIC_A_BUS_WIDTH </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_PFET_POWERUP_DELAY_NS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute>--> + <enumerator> + <name>2_BYTE</name> + <value>1</value> + </enumerator> + <enumerator> + <name>4_BYTE</name> + <value>2</value> + </enumerator> + <id>PROC_FABRIC_A_BUS_WIDTH</id> + </enumerationType> -<attribute> - <id>PFET_POWERDOWN_DELAY_NS</id> + <enumerationType> <description> - Time (in nanoseconds) between PFET controller steps (7 of them) when turning - the PFES OFF - - Producer: MRWB - - Consumers: p9_pm_pfet_init - - Platform default: + Enumeration indicating the PROC_FABRIC_X_BUS_WIDTH </description> - <simpleType> - <uint32_t> - <!-- Will be set by HWP --> - <default>0</default> - </uint32_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_PFET_POWERDOWN_DELAY_NS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + <enumerator> + <name>2_BYTE</name> + <value>1</value> + </enumerator> + <enumerator> + <name>4_BYTE</name> + <value>2</value> + </enumerator> + <id>PROC_FABRIC_X_BUS_WIDTH</id> + </enumerationType> -<attribute> - <id>PFET_VDD_VOFF_SEL</id> + <enumerationType> <description> - Selection of the OFF setting for the core and cache chiplet VDD PFET controllers - - Producer: MRWB - - Consumers: p9_pm_pfet_init - - Platform default: + Enumeration indicating the PROC_FABRIC_SMP_OPTICS_MODE </description> - <simpleType> - <uint8_t> - <!-- Will be set by HWP --> - <default>0</default> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_PFET_VDD_VOFF_SEL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> + <enumerator> + <name>OPTICS_IS_X_BUS</name> + <value>0x0</value> + </enumerator> + <enumerator> + <name>OPTICS_IS_A_BUS</name> + <value>0x1</value> + </enumerator> + <id>PROC_FABRIC_SMP_OPTICS_MODE</id> + </enumerationType> -<enumerationType> - <id>PFET_VDD_VOFF_SEL</id> + <enumerationType> <description> - Enumeration indicating the OFF setting for the core and cache chiplet - DD PFET controllers + Enumeration indicating the PROC_FABRIC_CAPI_MODE </description> <enumerator> - <name>NOOFF</name> - <value>0</value> + <name>OFF</name> + <value>0x0</value> </enumerator> <enumerator> - <name>ALLBUT1TO7OFF</name> - <value>1</value> + <name>ON</name> + <value>0x1</value> </enumerator> + <id>PROC_FABRIC_CAPI_MODE</id> + </enumerationType> + + <enumerationType> + <description>Enumeration for Voltage Drop Monitor enable</description> <enumerator> - <name>ALLBUT2TO7OFF</name> - <value>2</value> + <name>OFF</name> + <value>0x00</value> </enumerator> <enumerator> - <name>ALLBUT3TO7OFF</name> - <value>3</value> + <name>ON</name> + <value>0x01</value> </enumerator> - <enumerator> - <name>ALLBUT4TO7OFF</name> - <value>4</value> + <id>VDM_ENABLE</id> + </enumerationType> + + <enumerationType> + <description>Enumeration for Temperature refresh mode</description> + <enumerator> + <name>DISABLE</name> + <value>0</value> </enumerator> - <enumerator> - <name>ALLBUT5TO7OFF</name> - <value>5</value> + <enumerator> + <name>ENABLE</name> + <value>1</value> </enumerator> - <enumerator> - <name>ALLBUT6TO7OFF</name> - <value>6</value> + <id>MSS_MRW_TEMP_REFRESH_MODE</id> + </enumerationType> + + <enumerationType> + <description>Pulled from the MRW, this describes the device + type to the HDAT. This is for I2C devices only. + </description> + <enumerator> + <name>955X</name> + <value>1</value> </enumerator> - <enumerator> - <name>ALLBUT7TO7OFF</name> - <value>7</value> + <enumerator> + <name>SEEPROM</name> + <value>2</value> </enumerator> - <enumerator> - <name>ALLOFF</name> - <value>8</value> + <enumerator> + <name>NUVOTON_TPM</name> + <value>3</value> </enumerator> -</enumerationType> - -<attribute> - <id>PFET_VCS_VOFF_SEL</id> - <description> - Selection of the OFF setting for the core and cache chiplet VCS PFET controllers - - Producer: MRWB - - Consumers: p9_pm_pfet_init - - Platform default: - </description> - <simpleType> - <uint8_t> - <!-- Will be set by HWP --> - <default>0</default> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_PFET_VCS_VOFF_SEL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<enumerationType> - <id>PFET_VCS_VOFF_SEL</id> - <description> - Enumeration indicating the OFF setting for the core and cache chiplet - VCS PFET controllers - </description> <enumerator> - <name>NOOFF</name> - <value>0</value> + <name>MEX_FPGA</name> + <value>4</value> + </enumerator> + <enumerator> + <name>UCX90XX</name> + <value>5</value> + </enumerator> + <enumerator> + <name>NVLINK</name> + <value>6</value> </enumerator> <enumerator> - <name>ALLBUT1TO7OFF</name> + <name>UNKNOWN</name> + <value>FF</value> + </enumerator> + <id>HDAT_I2C_DEVICE_TYPE</id> + </enumerationType> + + <enumerationType> + <id>HDAT_I2C_DEVICE_PURPOSE</id> + <description>Pulled from the MRW, this describes the device + purpose to the HDAT. This is for I2C devices only. + </description> + <enumerator> + <name>CABLE_CARD_PRES</name> <value>1</value> </enumerator> <enumerator> - <name>ALLBUT2TO7OFF</name> + <name>CABLE_CARD_POWER_SENSE</name> <value>2</value> </enumerator> <enumerator> - <name>ALLBUT3TO7OFF</name> + <name>CABLE_CARD_POWER_CONTROL</name> <value>3</value> </enumerator> - <enumerator> - <name>ALLBUT4TO7OFF</name> + <enumerator> + <name>TPM</name> <value>4</value> </enumerator> - <enumerator> - <name>ALLBUT5TO7OFF</name> + <enumerator> + <name>MODULE_VPD</name> <value>5</value> </enumerator> - <enumerator> - <name>ALLBUT6TO7OFF</name> + <enumerator> + <name>DIMM_SPD</name> <value>6</value> </enumerator> - <enumerator> - <name>ALLBUT7TO7OFF</name> + <enumerator> + <name>PROC_MODULE_VPD</name> <value>7</value> </enumerator> - <enumerator> - <name>ALLOFF</name> + <enumerator> + <name>SBE_SEEPROM</name> <value>8</value> </enumerator> -</enumerationType> - -<attribute> - <id>PBAX_NODEID</id> - <description> - Receive PBAX Nodeid. Value that indicates this PBA's PBAX Node affinity. - This is matched to pbax_nodeid of the PMISC Address phase. - - Provided by the Machine Readable Workbook. - </description> - <simpleType> - <uint8_t> -<!-- TODO RTC:162070 Temporary default --> - <default>0</default> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_PBAX_NODEID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> + <enumerator> + <name>PLANAR_VPD</name> + <value>9</value> + </enumerator> + <enumerator> + <name>PCI_HOTPLUG</name> + <value>A</value> + </enumerator> + <enumerator> + <name>NVLINK</name> + <value>B</value> + </enumerator> + <enumerator> + <name>WINDOW_OPEN</name> + <value>0xD</value> + </enumerator> + <enumerator> + <name>PHYSICAL_PRESENCE</name> + <value>0xE</value> + </enumerator> + <enumerator> + <name>UNKNOWN</name> + <value>FF</value> + </enumerator> + </enumerationType> <attribute> - <id>VCS_I2C_RAIL</id> + <id>FREQ_CORE_MAX</id> <description> - Step delay (binary in microseconds) after a voltage change + SYSTEM Attribute + Maximum frequency (binary in MHz) that any processor in the system will + run. Used to define the top end of the PState range in the frequency space. + From this, the ATTR_PROCPM_PSTATE0_FREQUENCY is computed using + ATTR_SYSTEM_REFCLK_FREQUENCY to determine the step size. - Consumer: p9_build_pstate_datablock -> - Pstate Parameter Block (PSPB) for PGPE + Consumers: proc_build_gpstate_table.C (among others) - Provided by the Machine Readable Workbook after system characterization. + Data is is provided by MVPD #V and is calculated as the minimum + of the turbo frequencies </description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> + <uint32_t></uint32_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VCS_I2C_RAIL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <persistency>non-volatile</persistency> <readable/> + <writeable/> </attribute> <attribute> - <id>VDN_BOOT_VOLTAGE</id> - <description> - Voltage (binary in 1mV units) to apply to the VDN VRM for booting. Value - chosen is system dependent and is a combination of the part's Vital Product - Data (VPD) (typically the PowerSave value) and the minimum allowed for - correct operation of the fabric bus. - - Producer: p9_setup_evid (first pass) - - Consumer: p9_setup_evid (second pass) - </description> +<id>PIB_I2C_NEST_PLL</id> +<description> + i2c pll for the system + default is 0x26 (For PIB @500 MHz (2 GHz nest)) for + I2C speed = ~1Mhz per Andreas Koenig. +</description> <simpleType> <uint32_t> + <default>0x026</default> </uint32_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_VDN_BOOT_VOLTAGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> + <persistency>volatile</persistency> <readable/> <writeable/> </attribute> -<enumerationType> - <id>FAPI_POS</id> - <description>Enumeration defining special FAPI_POS values</description> - <enumerator> - <name>NA</name> - <value>0xFFFFFFFF</value> - </enumerator> - <default>NA</default> -</enumerationType> - <attribute> - <id>FAPI_POS</id> + <id>SYNC_BETWEEN_STEPS</id> <description> - Logical position of target within a system. This is derived from the SMP location - of each processor and each target's relationship to a proc. - - PROC = based on SMP groupid+chipid - - MEMBUF = PROC:FAPI_POS * [max membuf per proc] - - 1st level child unit = [parent chip]:FAPI_POS * [max children of this type per chip] - - 2nd+ level child unit = [immediate parent unit]:FAPI_POS * [max units below parent] - Note: This should not be used algorithmically by HWPs directly. - Note: Value ignores physical drawer boundaries, the value is unique across the entire - system. - This data is derived from the MRW. - Default of NA is 0xFFFFFFFF (to avoid confusion with legitimate 0 - values) + Attribute to enable targetting attribute sync when in istep mode. + 1 = sync will occur following each substep when ipl'ing in single step mode + 0 = sync will not be done after each step </description> <simpleType> - <uint32_t> - <default>0xFFFFFFFF</default> - </uint32_t> + <uint8_t> + </uint8_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_FAPI_POS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> - <no_export/> -</attribute> - -<attribute> - <id>I2C_BUS_DIV_REF</id> - <description> - Ref clock I2C bus divider consumed by code running out of OTPROM - </description> - <simpleType> - <uint16_t> - <default>0x0003</default> - </uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_I2C_BUS_DIV_REF</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NEST_PLL_BUCKET</id> - <description> - Select Nest I2C and pll setting from one of the supported frequencies - </description> - <simpleType> - <uint8_t> - <default>0x05</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_NEST_PLL_BUCKET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> -<!-- ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== - @todo: RTC:167266 set attributes from HWP nest PLL bucket data - ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== --> <attribute> <id>NEST_PLL_FREQ_BUCKETS</id> <description> @@ -21138,10 +5899,6 @@ Measured in GB</description> </simpleType> <persistency>volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_NEST_PLL_FREQ_BUCKETS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> @@ -21158,10 +5915,6 @@ Measured in GB</description> </simpleType> <persistency>volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_NEST_PLL_FREQ_LIST</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> @@ -21179,982 +5932,141 @@ Measured in GB</description> </simpleType> <persistency>volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_NEST_PLL_FREQ_I2CDIV_LIST</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> -<!-- ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== - @todo: RTC:167266 set attributes from HWP nest PLL bucket data - ===== ===== ===== ===== ===== ===== ===== ===== ===== ===== --> <attribute> - <id>BOOT_FREQ</id> - <description>EQ boot frequency</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_BOOT_FREQ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SBE_UPDATE_DISABLE</id> - <description> - Control execution of updateProcessorSbeSeeproms() - - if 0, enable SBE update of processor SEEPROM - if 1, disable SBE update of processor SEEPROM - - Consumer: sbe_update.C - - Default: 0 - </description> + <id>MBA_PORT</id> + <description>MBA port this DIMM is connected to</description> <simpleType> <uint8_t> - <default>0</default> + <default>0</default> </uint8_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_SBE_UPDATE_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <persistency>non-volatile</persistency> <readable/> + <no_export/> </attribute> <attribute> - <id>BOOT_FLAGS</id> - <description>Switch to using a flag to indicate SEEPROM side SBE</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_BOOT_FLAGS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- Deprecated --> -<attribute> - <id>NODE_POS</id> - <description>Indicate the node position in FSP based systems - (unused in Spless systems)</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_NODE_POS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>CHIP_POS</id> - <description>Indicate the chip position</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CHIP_POS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--Deprecated--> -<attribute> - <id>FUNCTIONAL_EQ_EC_VALID</id> - <description> - Indicates the validitiy of FW functional EQ/EQ register - FALSE = 0x0, TRUE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_FUNCTIONAL_EQ_EC_VALID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EQ_GARD</id> - <description>Capturing EQ Gard value</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EQ_GARD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EC_GARD</id> - <description>Capturing EC Gard Value</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EC_GARD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--Deprecated--> -<attribute> - <id>I2C_BUS_DIV_REF_VALID</id> - <description>Indicates the validity of ref clock I2C bus divider consumed by - code running out of OTPROM - FALSE = 0x0,TRUE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_I2C_BUS_DIV_REF_VALID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--Deprecated--> -<attribute> - <id>FW_MODE_FLAGS_VALID</id> - <description>Indicates the validity of FW flags. Ex: ISTEP_MODE, - SBE_RUNTIME_MODE, MPIPL_MODE, SP_MODE, SBE_FFDC_ENABLE - FALSE = 0x0,TRUE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_FW_MODE_FLAGS_VALID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- Deprecated --> -<attribute> - <id>SBE_RUNTIME_MODE</id> - <description>Indicates that SBE should go directly to runtime functionality - FALSE = 0x0, TRUE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_RUNTIME_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- Deprecated --> -<attribute> - <id>IS_SP_MODE</id> - <description>Indicates whether we are connected to FSP or not - FSP_LESS = 0x0,FSP = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_IS_SP_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--Deprecated--> -<attribute> - <id>SBE_FFDC_ENABLE</id> - <description>Indicates whether SBE should collect FFDC - FALSE = 0x0,TRUE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_FFDC_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--Deprecated--> -<attribute> - <id>SBE_INTERNAL_FFDC_ENABLE</id> - <description>Indicates that the SBE should send back internal FFDC on any - chipOp failure response - FALSE = 0x0,TRUE = 0x1</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_INTERNAL_FFDC_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--Deprecated--> -<attribute> - <id>BOOT_FREQUENCY_VALID</id> - <description>Indicates if BOOT_FREQ_MULT and NEST_PLL_BUCKET are valid - FALSE = 0x0,TRUE = 0x1</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_BOOT_FREQUENCY_VALID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>BOOT_FREQ_MULT</id> - <description>EQ boot frequency multiplier</description> - <simpleType> - <uint16_t> - <default>150</default> - </uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_BOOT_FREQ_MULT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--Deprecated--> -<attribute> - <id>HWP_CONTROL_FLAGS_VALID</id> - <description> - Indicates if HWP control flags are valid - FALSE = 0x0,TRUE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_HWP_CONTROL_FLAGS_VALID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SYS_FORCE_ALL_CORES</id> - <description> - Indicates that SBE should init all cores - FALSE = 0x0,TRUE = 0x1 - Override Attribute - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SYS_FORCE_ALL_CORES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DISABLE_HBBL_VECTORS</id> - <description> - BootLoader HWP flag to not place 12K exception vectors. - This flag is only applicable when security is disabled. - FALSE = 0x0,TRUE = 0x1 - Override Attribute - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_DISABLE_HBBL_VECTORS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--Deprecated--> -<attribute> - <id>CHIP_SELECTION_VALID</id> - <description>Indicates that master/slave, node/chip selection attributes - are valid - FALSE = 0x0,TRUE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CHIP_SELECTION_VALID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>CHIP_SELECTION</id> - <description>master/slave bit - MASTER = 0x0,SLAVE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CHIP_SELECTION</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--Deprecated--> -<attribute> - <id>SCRATCH6_VALID</id> - <description>Indicate if scratch reg6 bits are valid - FALSE = 0x0,TRUE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH6_VALID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--Deprecated--> -<attribute> - <id>SCRATCH7_VALID</id> - <description>Indicate if scratch reg7 bits are valid - FALSE = 0x0,TRUE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SCRATCH7_VALID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>BACKUP_SEEPROM_SELECT</id> - <description>Set with Primary SEEPROM</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_BACKUP_SEEPROM_SELECT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>BOOT_FMULT</id> - <description>EQ boot frequency multiplier</description> - <simpleType> - <uint16_t> - </uint16_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_BOOT_FMULT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>BRANCH_PIBMEM_ADDR</id> - <description>Bransh Pibmem address</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_BRANCH_PIBMEM_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DEVICE_ID</id> - <description>Device Identification</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_DEVICE_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <no_export/> -</attribute> - -<!-- Deprecated --> -<attribute> - <id>I2C_BUS_DIV_NEST</id> - <description>I2C Bus speed based on nest freq, ref clock</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_I2C_BUS_DIV_NEST</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- Deprecated --> -<attribute> - <id>LEN_OF_SEEPROM_DATA</id> - <description>Length of Seeprom data</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_LEN_OF_SEEPROM_DATA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>MB_BIT_RATE_DIVISOR_PLL</id> - <description>MN Bitrate divisor pll</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MB_BIT_RATE_DIVISOR_PLL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- Deprecated --> -<attribute> - <id>MB_BIT_RATE_DIVISOR_REFCLK</id> - <description>MB_BIT_RATE_DIVISOR_REFCLK</description> - <simpleType> - <uint8_t> - <default>133</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MB_BIT_RATE_DIVISOR_REFCLK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MC_SYNC_MODE</id> - <description>MC mesh to use Nest mesh or not</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MC_SYNC_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PG</id> - <description> - Chiplet Partial good info attribute. Provided by Ring scans - </description> - <simpleType> - <uint16_t> - </uint16_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>PROC_PB_BNDY_DMIPLL_DATA</id> - <description>Ring image for pb_bndy_dmipll ring creator: - platform firmware notes:</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PB_BNDY_DMIPLL_DATA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA</id> - <description>Ring image for pb_bndy_dmipll ring for DC cal creator: - platform firmware notes:</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>PROC_PERV_BNDY_PLL_DATA</id> - <description>Ring image for perv_bndy_pll ring containing filter plls - and xb_pll,nest_pll creator: platform firmware notes:</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PERV_BNDY_PLL_DATA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>PROC_SBE_MASTER_CHIP</id> - <description> - Indicates if SBE on this chip is serving as hosboot drawer master - FALSE = 0x0,TRUE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_SBE_MASTER_CHIP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>START_PIBMEM_ADDR</id> - <description>Start of PIBMEM address</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_START_PIBMEM_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>START_SEEPROM_ADDR</id> - <description>Start of seeprom address</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_START_SEEPROM_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- Deprecated --> -<attribute> - <id>WAIT_N0</id> - <description>Wait N0</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_WAIT_N0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- Deprecated --> -<attribute> - <id>WAIT_N1</id> - <description>WAIT_N1</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_WAIT_N1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- Deprecated --> -<attribute> - <id>WAIT_N2</id> - <description>WAIT_N2</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_WAIT_N2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- Deprecated --> -<attribute> - <id>WAIT_N3</id> - <description>WAIT_N3</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_WAIT_N3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- name changed in ekb, need to have both to push interim commits through --> -<attribute> - <id>PROC_FABRIC_SYSTEM_ID</id> - <description> - Logical fabric system ID associated with this chip. - Would only need to be a non-zero to support CCSM - (coherent cluster shared memory) system topologies - Provided by the MRW. - </description> - <simpleType> - <uint32_t> - <default>0</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_SYSTEM_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CLOCK_PLL_MUX</id> - <description>setup clock mux settings</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CLOCK_PLL_MUX</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CLOCK_PLL_MUX0</id> - <description>Clock Mux#0 settings</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CLOCK_PLL_MUX0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>MASTER_CORE</id> - <description>Indicates the master boot core chiplet selected by p9_sbe_select_ex. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MASTER_CORE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <id>MBA_DIMM</id> + <description>MBA port DIMM number of this DIMM</description> + <simpleType> + <uint8_t> + <default>0</default> + </uint8_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <no_export/> </attribute> -<!--SBE ONLY--> <attribute> - <id>MASTER_EX</id> - <description>Indicates the EX targert associated with the master boot core selected - by p9_sbe_select_ex. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MASTER_EX</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <id>ASYNC_NEST_FREQ_MHZ</id> + <description> + The asynchronous nest frequency + </description> + <simpleType> + <uint32_t> + <default>2000</default> + </uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> </attribute> <attribute> - <id>STOPGPE_BOOT_COPIER_IVPR_OFFSET</id> - <description>Set by p9_hcode_image build with the offset value from - the HOMER base where the SGPE Boot Copier interrupt vectors reside. This - value must be 512B aligned. The HOMER base address will be pre-establish - in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The SGPE - will be Sreset after this value is established. - </description> + <id>CHIP_ID</id> + <description>attribute indicating the chip's ID</description> <simpleType> <uint32_t> </uint32_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> </attribute> <attribute> - <id>PSTATEGPE_BOOT_COPIER_IVPR_OFFSET</id> - <description>Set by p9_hcode_image build with the offset value from - the HOMER base where the PGPE Boot Copier interrupt vectors reside. This - value must be 512B aligned. The HOMER base address will be pre-establish - in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The PGPE - will be Sreset after this value is established + <id>SBE_IS_STARTED</id> + <description> + If 0, SBE for the processor has not been started. + Otherwise, SBE for the processor has been started. </description> <simpleType> - <uint32_t> - </uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> </attribute> <attribute> - <id>CHIPLET_ID</id> - <description>The address offset which each Chiplet types pervasive - address space used to represent the a chiplet. - 0x00 to 0x0F => For P9 all non-core and non-cache chiplets - 0x10 to 0x1F => All Cache Chiplets - 0x20 to 0x37 => All Core Chiplets - 0x38 to 0x3F => Multicast Operation - </description> - <simpleType> - <uint8_t> - <default>0xFF</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> + <id>MIRROR_BASE_ADDRESS</id> + <description>System Mirrorable base address</description> + <simpleType> + <uint64_t> + <default>0x0000800000000000</default><!-- 128 TB --> + </uint64_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> + <hwpfToHbAttrMap> + <id>ATTR_MIRROR_BASE_ADDRESS</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <id>SYSTEM_IPL_PHASE</id> - <description>Define context for current phase of system IPL. - Provided by the platform. - HB_IPL = 0x1,HB_RUNTIME = 0x2,CACHE_CONTAINED = 0x4</description> - <simpleType> - <uint8_t> - <default>0x01</default> - </uint8_t> - </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_IPL_PHASE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <id>PROC_PCIE_PHB_ACTIVE</id> + <description>PCIE PHB valid mask + creator: platform + consumer: proc_pcie_scominit + firmware notes: + Bit mask defining set of active/valid PHBs + bit0=PHB0, bit1=PHB1, bit2=PHB2, bit3=PHB3 + </description> + <simpleType><uint8_t></uint8_t></simpleType> <persistency>non-volatile</persistency> <readable/> <writeable/> </attribute> <attribute> - <id>ADU_XSCOM_BAR_BASE_ADDR</id> - <description>Defines XSCOM base address on each processor level. - address provided by the MRW </description> + <id>PROC_PCIE_NUM_PEC</id> + <description> + creator: platform + Number of PCIe PEC units present on target + Nimbus: 3 + </description> <simpleType> - <uint64_t></uint64_t> + <uint8_t></uint8_t> </simpleType> - <hwpfToHbAttrMap> - <id>ATTR_ADU_XSCOM_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> </attribute> <attribute> - <id>PARENT_PERVASIVE</id> + <id>HOMER_PHYS_ADDR</id> <description> - Physical entity path of the target's associated pervasive target + Physical address where HOMER image is placed in mainstore. </description> - <nativeType> - <name>EntityPath</name> - </nativeType> - <persistency>non-volatile</persistency> + <simpleType> + <uint64_t></uint64_t> + </simpleType> + <persistency>volatile-zeroed</persistency> <readable/> - <virtual/> - <no_export/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_HOMER_PHYS_ADDR</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + <ignoreEkb/> </attribute> -<!-- ********************************************************************** --> <attribute> <id>FREQ_CORE_CEILING_MHZ</id> - <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> <description> The maximum core frequency in MHz. This is the same for all cores in the system. @@ -22172,891 +6084,170 @@ Measured in GB</description> <id>ATTR_FREQ_CORE_CEILING_MHZ</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> + <ignoreEkb/> </attribute> -<enumerationType> - <id>PROC_FABRIC_A_BUS_WIDTH</id> - <description> - Enumeration indicating the PROC_FABRIC_A_BUS_WIDTH - </description> - <!-- Note: Values must match numbers from nest_attributes.xml --> - <enumerator> - <name>2_BYTE</name> - <value>1</value> - </enumerator> - <enumerator> - <name>4_BYTE</name> - <value>2</value> - </enumerator> -</enumerationType> - -<attribute> - <id>PROC_FABRIC_A_BUS_WIDTH</id> - <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> - <description> - Processor SMP A bus width. - Provided by the MRW. - 2_BYTE = 0x01, 4_BYTE = 0x02 - </description> - <simpleType><uint8_t><default>4_BYTE</default></uint8_t></simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_A_BUS_WIDTH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>PROC_FABRIC_X_BUS_WIDTH</id> - <description> - Enumeration indicating the PROC_FABRIC_X_BUS_WIDTH - </description> - <!-- Note: Values must match numbers from nest_attributes.xml --> - <enumerator> - <name>2_BYTE</name> - <value>1</value> - </enumerator> - <enumerator> - <name>4_BYTE</name> - <value>2</value> - </enumerator> -</enumerationType> - <attribute> - <id>PROC_FABRIC_X_BUS_WIDTH</id> - <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> - <description> - Processor SMP X bus width. - Provided by the MRW. - 2_BYTE = 0x01, 4_BYTE = 0x02 - </description> - <simpleType> - <uint8_t><default>4_BYTE</default></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_X_BUS_WIDTH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_CCSM_MODE</id> - <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> - <description> - Processor SMP topology configuration. - 0 = default = 1 or 2 hop topology (PHYP image spans system) - Provided by the MRW. - OFF = 0x0 (default) - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_CCSM_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>OPTICS_CONFIG_MODE</id> - <description> - Enumeration indicating the OPTICS_CONFIG_MODE - </description> - <enumerator> - <name>SMP</name> - <value>0x0</value> - </enumerator> - <enumerator> - <name>CAPILINK</name> - <value>0x1</value> - </enumerator> - <enumerator> - <name>NVLINK</name> - <value>0x2</value> - </enumerator> -</enumerationType> - -<attribute> - <id>OPTICS_CONFIG_MODE</id> - <description> - Per-link optics configuration - 0 = SMP (default) - 1 = CAPI 2.0 - 2 = NV 2.0 - Provided by the MRW. - </description> - <simpleType> - <uint8_t> - <default>NVLINK</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_OPTICS_CONFIG_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OBUS_BRICK_LANE_MASK</id> - <description> - Lane mask for which 8 lanes belong to this brick - This is a right justified 24-bit value. Only 8 of the - 24 bits will be set representing the lanes belonging to - the associated brick. - Provided by the MRW. - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_OBUS_BRICK_LANE_MASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>OBUS_SLOT_INDEX</id> - <description> - Position of the obus slot that the Obus brick is connected to - (represented in decimal). There is only one slot that a given - brick connects to and there are only 6 slots per proc, - so, we just need a single uint8_t representing the position - of the slot. - Provided by the MRW. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_OBUS_SLOT_INDEX</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <no_export/> -</attribute> - -<enumerationType> - <id>PROC_FABRIC_SMP_OPTICS_MODE</id> - <description> - Enumeration indicating the PROC_FABRIC_SMP_OPTICS_MODE - </description> - <!-- Note: Values must match numbers from nest_attributes.xml --> - <enumerator> - <name>OPTICS_IS_X_BUS</name> - <value>0x0</value> - </enumerator> - <enumerator> - <name>OPTICS_IS_A_BUS</name> - <value>0x1</value> - </enumerator> -</enumerationType> - -<attribute> - <id>PROC_FABRIC_SMP_OPTICS_MODE</id> - <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> - <description> - Processor SMP optics mode. - 0 = Optics_is_X_bus (default) - 1 = Optics_is_A_bus - Provided by the MRW. - OPTICS_IS_X_BUS = 0x0, OPTICS_IS_A_BUS = 0x1 - </description> - <simpleType> - <uint8_t> - <default>OPTICS_IS_X_BUS</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_SMP_OPTICS_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>PROC_FABRIC_CAPI_MODE</id> - <description> - Enumeration indicating the PROC_FABRIC_CAPI_MODE - </description> - <!-- Note: Values must match numbers from nest_attributes.xml --> - <enumerator> - <name>OFF</name> - <value>0x0</value> - </enumerator> - <enumerator> - <name>ON</name> - <value>0x1</value> - </enumerator> -</enumerationType> - -<attribute> - <id>PROC_FABRIC_CAPI_MODE</id> - <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> - <description> - Processor CAPI attachment protocol mode. - 0 = no: SMPA CAPI attachment (default) - 1 = yes: SMPA CAPI attachment - Provided by the MRW. - </description> - <simpleType> - <uint8_t> - <default>OFF</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_CAPI_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_SYSTEM_MASTER_CHIP</id> - <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> - <description> - Indicates if the given chip should serve as the fabric system master. - FALSE = 0x0, TRUE = 0x1 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_SYSTEM_MASTER_CHIP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_GROUP_MASTER_CHIP</id> - <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> - <description> - Indicates if the given chip should serve as the fabric group master. - FALSE = 0x0, TRUE = 0x1 - </description> - <simpleType><uint8_t></uint8_t></simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_GROUP_MASTER_CHIP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_X_ATTACHED_CHIP_CNFG</id> - <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> - <description> - For each fabric X link on this chip, specifies whether or not the chip at - the receiving end of the link is present and configured - FALSE = 0x0, TRUE = 0x1 - </description> - <simpleType> - <uint8_t></uint8_t> - <array>7</array> - </simpleType> - <writeable/> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_A_ATTACHED_CHIP_CNFG</id> - <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> - <description> - For each fabric A link on this chip, specifies whether or not the chip at - the receiving end of the link is present and configured - FALSE = 0x0, TRUE = 0x1 - </description> - <simpleType> - <uint8_t></uint8_t> - <array>4</array> - </simpleType> - <writeable/> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_X_ATTACHED_CHIP_ID</id> - <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> - <description> - For each fabric X link on this chip, specifies the fabric ID of the chip - at the receiving end of the link. Should be considered valid only if - corresponding ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true. - </description> - <simpleType> - <uint8_t></uint8_t> - <array>7</array> - </simpleType> - <writeable/> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_X_ATTACHED_CHIP_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_A_ATTACHED_CHIP_ID</id> - <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> - <description> - For each fabric A link on this chip, specifies the fabric ID of the chip - at the receiving end of the link. Should be considered valid only if - corresponding ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true. - </description> - <simpleType> - <uint8_t></uint8_t> - <array>4</array> - </simpleType> - <writeable/> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_A_ATTACHED_CHIP_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_X_ADDR_DIS</id> - <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> - <description> - Indicates if link should be used to carry data only - (in aggregate configurations). - Should be considered valid only if corresponding - ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true. - OFF = 0x0, ON = 0x1 - </description> - <simpleType> - <uint8_t></uint8_t> - <array>7</array> - </simpleType> - <writeable/> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_X_ADDR_DIS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_A_ADDR_DIS</id> - <!-- <targetType>TARGET_TYPE_PROC_CHIP</targetType> --> - <description> - Indicates if link should be used to carry data only - (in aggregate configurations). - Should be considered valid only if corresponding - ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true. - OFF = 0x0, ON = 0x1 - </description> - <simpleType> - <uint8_t></uint8_t> - <array>4</array> - </simpleType> - <writeable/> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_A_ADDR_DIS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_EPS_READ_CYCLES_T0</id> - <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> - <description> - Calculated read tier0 epsilon protection count. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <writeable/> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_EPS_READ_CYCLES_T0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_EPS_READ_CYCLES_T1</id> - <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> - <description> - Calculated read tier1 epsilon protection count. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <writeable/> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_EPS_READ_CYCLES_T1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_EPS_READ_CYCLES_T2</id> - <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> + <id>PG</id> <description> - Calculated read tier2 epsilon protection count. + Chiplet Partial good info attribute. Provided by Ring scans </description> <simpleType> - <uint32_t></uint32_t> + <uint16_t> + </uint16_t> </simpleType> - <writeable/> - <readable/> <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_EPS_READ_CYCLES_T2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_EPS_WRITE_CYCLES_T1</id> - <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> - <description> - Calculated write tier1 epsilon protection count. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <writeable/> <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_EPS_WRITE_CYCLES_T1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_EPS_WRITE_CYCLES_T2</id> - <!-- <targetType>TARGET_TYPE_SYSTEM</targetType> --> - <description> - Calculated write tier2 epsilon protection count. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> <writeable/> - <readable/> - <persistency>volatile-zeroed</persistency> <hwpfToHbAttrMap> - <id>ATTR_PROC_EPS_WRITE_CYCLES_T2</id> + <id>ATTR_PG</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> + <ignoreEkb/> </attribute> <attribute> - <id>PROC_PCIE_IOVALID_ENABLE</id> - <!-- TARGET_TYPE_PEC --> + <id>SECUREBOOT_PROTECT_DECONFIGURED_TPM</id> <description> - PCIE iovalid enable valid mask - creator: platform - consumer: p9_pcie_scominit + To deconfigure a TPM in a secure system - 01 to set TDP bit </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + </uint8_t> </simpleType> <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOVALID_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> <readable/> <writeable/> -</attribute> -<attribute> - <id>PROC_PCIE_BAR_ENABLE</id> - <!-- TARGET_TYPE_PHB --> - <description> - PCIE MMIO BAR enable - creator: platform - consumer: p9_pcie_config - firmware notes: - Array index: BAR number (0:2) - index 0~1 for MMIO BAR0/1 - index 2 for PHB register space - DISABLE = 0x0, ENABLE = 0x1 - </description> - <simpleType> - <uint8_t></uint8_t> - <array>3</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<attribute> - <id>PROC_PCIE_BAR_BASE_ADDR</id> - <!-- TARGET_TYPE_PHB --> - <description> - PCIE MMIO BAR base address value - creator: platform - consumer: p9_setup_bars - firmware notes: - 64-bit address representing BAR RA - Array index: BAR number (0:2) - NOTE: BAR0/1 registers cover RA 8:47 - NOTE: BAR2 registers covers RA 8:49 - index 0~1 for BAR0/1 - index 2 for PHB - index 3 for interrupt - </description> - <simpleType> - <uint64_t></uint64_t> - <array>4</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<attribute> - <id>PROC_PCIE_BAR_SIZE</id> - <!-- TARGET_TYPE_PHB --> - <description> - PCIE MMIO BAR size values - creator: platform - consumer: p9_pcie_config - firmware notes: - Array index: BAR number (0:2) - NOTE: supported MMIO BAR0/1 sizes are from 64KB-32PB - NOTE: only supported PHB register size is 16KB - 32_PB = 0x8000000000000000, - 16_PB = 0xC000000000000000, - 8_PB = 0xE000000000000000, - 4_PB = 0xF000000000000000, - 2_PB = 0xF800000000000000, - 1_PB = 0xFC00000000000000, - 512_TB = 0xFE00000000000000, - 256_TB = 0xFF00000000000000, - 128_TB = 0xFF80000000000000, - 64_TB = 0xFFC0000000000000, - 32_TB = 0xFFE0000000000000, - 16_TB = 0xFFF0000000000000, - 8_TB = 0xFFF8000000000000, - 4_TB = 0xFFFC000000000000, - 2_TB = 0xFFFE000000000000, - 1_TB = 0xFFFF000000000000, - 512_GB = 0xFFFF800000000000, - 256_GB = 0xFFFFC00000000000, - 128_GB = 0xFFFFE00000000000, - 64_GB = 0xFFFFF00000000000, - 32_GB = 0xFFFFF80000000000, - 16_GB = 0xFFFFFC0000000000, - 8_GB = 0xFFFFFE0000000000, - 4_GB = 0xFFFFFF0000000000, - 2_GB = 0xFFFFFF8000000000, - 1_GB = 0xFFFFFFC000000000, - 512_MB = 0xFFFFFFE000000000, - 256_MB = 0xFFFFFFF000000000, - 128_MB = 0xFFFFFFF800000000, - 64_MB = 0xFFFFFFFC00000000, - 32_MB = 0xFFFFFFFE00000000, - 16_MB = 0xFFFFFFFF00000000, - 8_MB = 0xFFFFFFFF80000000, - 4_MB = 0xFFFFFFFFC0000000, - 2_MB = 0xFFFFFFFFE0000000, - 1_MB = 0xFFFFFFFFF0000000, - 512_KB = 0xFFFFFFFFF8000000, - 256_KB = 0xFFFFFFFFFC000000, - 128_KB = 0xFFFFFFFFFE000000, - 64_KB = 0xFFFFFFFFFF000000, - 16_KB = 0xFFFFFFFFFFFFFFFF - </description> - <simpleType> - <uint64_t></uint64_t> - <array>3</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_BAR_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<attribute> - <id>PROC_PCIE_HOTPLUG_I2C_DEVICE_ADDRESS</id> - <!-- TARGET_TYPE_PROC_CHIP --> - <description> - I2C device address for PCIE hotplug controller - creator: platform - consumer: p9_pcie_hotplug - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_HOTPLUG_I2C_DEVICE_ADDRESS</id> + <id>ATTR_SECUREBOOT_PROTECT_DECONFIGURED_TPM</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> + <ignoreEkb/> </attribute> <attribute> - <id>PROC_PCIE_HOTPLUG_ENABLE_ACTIONS</id> - <!-- TARGET_TYPE_PROC_CHIP --> + <id>PROC_PCIE_PCS_SYSTEM_CNTL</id> <description> - Sequence of PCIE hotplug controller register writes required to enable - slot power + Value of PCS system control creator: platform - consumer: p9_pcie_hotplug - firmware notes: - Primary array index: Sequence number - Secondary array index: Address (0) / Data (1) + consumer: p9_pcie_scominit </description> <simpleType> - <uint8_t></uint8_t> - <array>8,2</array> + <uint16_t></uint16_t> </simpleType> - <persistency>non-volatile</persistency> + <persistency>non-volatile</persistency><!-- @fixme --> <readable/> + <writeable/> <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_HOTPLUG_ENABLE_ACTIONS</id> + <id>ATTR_PROC_PCIE_PCS_SYSTEM_CNTL</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> + <ignoreEkb/> </attribute> <attribute> - <id>PROC_PCIE_HOTPLUG_NUM_ENABLE_ACTIONS</id> - <!-- TARGET_TYPE_PROC_CHIP --> + <id>SBE_UPDATE_DISABLE</id> <description> - Number of valid entries in primary index of - ATTR_PROC_PCIE_HOTPLUG_ENABLE_ACTIONS - creator: platform - consumer: p9_pcie_hotplug - ZERO = 0x0, - ONE = 0x1, - TWO = 0x2, - THREE = 0x3, - FOUR = 0x4, - FIVE = 0x5, - SIX = 0x6, - SEVEN = 0x7, - EIGHT = 0x8 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_HOTPLUG_NUM_ENABLE_ACTIONS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Control execution of updateProcessorSbeSeeproms() -<attribute> - <id>PROC_PCIE_HOTPLUG_DISABLE_ACTIONS</id> - <!-- TARGET_TYPE_PROC_CHIP --> - <description> - Sequence of PCIE hotplug controller register writes required to disable - slot power - creator: platform - consumer: p9_pcie_hotplug - firmware notes: - Primary array index: Sequence number - Secondary array index: Address (0) / Data (1) - </description> - <simpleType> - <uint8_t></uint8_t> - <array>8,2</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_HOTPLUG_DISABLE_ACTIONS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + if 0, enable SBE update of processor SEEPROM + if 1, disable SBE update of processor SEEPROM -<attribute> - <id>PROC_PCIE_HOTPLUG_NUM_DISABLE_ACTIONS</id> - <!-- TARGET_TYPE_PROC_CHIP --> - <description> - Number of valid entries in primary index of - ATTR_PROC_PCIE_HOTPLUG_DISABLE_ACTIONS - creator: platform - consumer: p9_pcie_hotplug - - ZERO = 0x0, - ONE = 0x1, - TWO = 0x2, - THREE = 0x3, - FOUR = 0x4, - FIVE = 0x5, - SIX = 0x6, - SEVEN = 0x7, - EIGHT = 0x8 + Consumer: sbe_update.C + + Default: 0 </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_HOTPLUG_NUM_DISABLE_ACTIONS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_PCIE_PCS_RX_CDR_GAIN</id> - <!-- TARGET_TYPE_PEC --> - <description> - PCS rx cdr gains - creator: platform - consumer: p9_pcie_scominit - firmware notes: - The value of rx cdr gains for PCS. - Array index: Configuration number - index 0~3 for CONFIG0~3 + <id>PROC_PCIE_REFCLOCK_ENABLE</id> + <description>PCIE refclock enable valid mask + PCIE refclock enable valid mask + creator: platform + consumer: p9_pcie_scominit </description> <simpleType> - <uint8_t></uint8_t> - <array>4</array> + <uint8_t> + </uint8_t> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> + <writeable/> <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_CDR_GAIN</id> + <id>ATTR_PROC_PCIE_REFCLOCK_ENABLE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> + <ignoreEkb/> </attribute> <attribute> - <id>PROC_PCIE_PCS_RX_PK_INIT</id> - <!-- TARGET_TYPE_PEC --> - <description> - PCS rx vga peak init value + <id>PROC_PCIE_IOP_CONFIG</id> + <description>PCIE IOP lane configuration creator: platform - consumer: p9_pcie_scominit + consumer: proc_pcie_scominit firmware notes: - The value of rx vga peak init for PCS. - Array index: Configuration number - index 0~3 for CONFIG0~3 - lane 0~15 for each PCIE Lane - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>4,16</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_PK_INIT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + Encoded PCIE IOP lane configuration + </description> + <simpleType><uint8_t></uint8_t></simpleType> + <persistency>non-volatile</persistency> + <readable/> + <writeable/> + <hwpfToHbAttrMap> + <id>ATTR_PROC_PCIE_IOP_CONFIG</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> + <ignoreEkb/> </attribute> <attribute> - <id>PROC_PCIE_PCS_RX_INIT_GAIN</id> + <id>PROC_PCIE_IOVALID_ENABLE</id> <!-- TARGET_TYPE_PEC --> <description> - PCS rx vga gain init value - creator: platform - consumer: p9_pcie_scominit - firmware notes: - The value of rx vga gain init for PCS. - Array index: Configuration number - index 0~3 for CONFIG0~3 - lane 0~15 for each PCIE Lane + PCIE iovalid enable valid mask + creator: platform + consumer: p9_pcie_scominit </description> <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - <array>4,16</array> + <uint8_t></uint8_t> </simpleType> - <persistency>non-volatile</persistency> - <readable/> + <persistency>volatile-zeroed</persistency> <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_INIT_GAIN</id> + <id>ATTR_PROC_PCIE_IOVALID_ENABLE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> + <readable/> + <writeable/> + <ignoreEkb/> </attribute> <attribute> - <id>PROC_PCIE_PCS_RX_SIGDET_LVL</id> - <!-- TARGET_TYPE_PEC --> - <description> - PCS rx sigdet lvl value - creator: platform - consumer: p9_pcie_scominit - firmware notes: - The value of rx sigdet lvl for PCS. - Array index: Configuration number - index 0~3 for CONFIG0~3 - </description> + <id>ISTEP_MODE</id> + <description>If True, puts HostBoot into SPLess SingleStep mode.</description> <simpleType> <uint8_t> - <default>0x0B</default> + <default>0</default> </uint8_t> - <array>4</array> </simpleType> <persistency>non-volatile</persistency> <readable/> + <writeable/> <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_SIGDET_LVL</id> + <id>ATTR_ISTEP_MODE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> + <ignoreEkb/> </attribute> <attribute> - <id>PROC_PCIE_PCS_RX_ROT_EXTEL</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS RX ROT extel latch - creator: platform - consumer: p9_pcie_scominit - firmware notes: - 0 for internal (default) - 1 for external (freezes phase rotators) - </description> + <id>EC</id> + <description>attribute indicating the chip target's EC level</description> <simpleType> <uint8_t> </uint8_t> @@ -23065,43 +6256,27 @@ Measured in GB</description> <readable/> <writeable/> <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_ROT_EXTEL</id> - <macro>DIRECT</macro> + <id>ATTR_EC</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> + <ignoreEkb/> </attribute> <attribute> - <id>PROC_PCIE_PCS_RX_ROT_RST_FW</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS RX ROT rstfw latch - creator: platform - consumer: p9_pcie_scominit - firmware notes: - 0 normal, flywheel is enabled (default) - 1 assert reset to the phase rotator flywheel (disable the flywheel) - </description> + <id>EFF_DRAM_COLS</id><!-- @fixme --> + <description>Number of DRAM columns. Initialized and used by HWPs.</description> <simpleType> <uint8_t> - <default>0</default> </uint8_t> </simpleType> - <persistency>non-volatile</persistency> + <persistency>volatile-zeroed</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_ROT_RST_FW</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> <attribute> - <id>PROC_PCIE_PCS_RX_DFE_FDDC</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS rx dfe func fddc control latch - creator: platform - consumer: p9_pcie_scominit - </description> + <id>EFF_DRAM_ROWS</id><!-- @fixme --> + <description>Number of DRAM rows. Initialized and used by HWPs.</description> <simpleType> <uint8_t> </uint8_t> @@ -23109,233 +6284,156 @@ Measured in GB</description> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_DFE_FDDC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_PCIE_PCS_RX_LOFF_CONTROL</id> - <!-- TARGET_TYPE_PEC --> + <id>REDUNDANT_CLOCKS</id> <description> - PCS rx loff control - creator: platform - consumer: p9_pcie_scominit - firmware notes: - The value of rx loff control for PCS. - Array index: Configuration number - index 0~3 for CONFIG0~3 + 1 = System has redundant clock oscillators + 0 = System does not have redundant clock oscillators + From the Machine Readable Workbook </description> <simpleType> - <uint16_t></uint16_t> - <array>4</array> + <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_LOFF_CONTROL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3</id> - <!-- TARGET_TYPE_PEC --> + <id>REL_POS</id> <description> - PCS rx vga control register3 - creator: platform - consumer: p9_pcie_scominit - firmware notes: - The value of rx vga control register3. - Array index: Configuration number - index 0~3 for CONFIG0~3 + Logical position of this unit/dimm relative to its immediate parent </description> <simpleType> - <uint16_t></uint16_t> - <array>4</array> + <uint8_t> + <default>0xFF</default> + </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3</id> + <id>ATTR_REL_POS</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> + <ignoreEkb/> + <no_export/> </attribute> -<attribute> - <id>PROC_PCIE_PCS_RX_ROT_CDR_LOOKAHEAD</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS RX ROT CNTL CDR lookahead - creator: platform - consumer: p9_pcie_scominit - firmware notes: - 0 for disable, 1 for enable - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_ROT_CDR_LOOKAHEAD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> +<enumerationType> + <id>FUSED_CORE_MODE_HB</id> + <description>Enum for FUSED_CORE_MODE_HB</description> + <enumerator> + <name>SMT4_DEFAULT</name> + <value>0</value> + </enumerator> + <enumerator> + <name>SMT4_ONLY</name> + <value>1</value> + </enumerator> + <enumerator> + <name>SMT8_ONLY</name> + <value>2</value> + </enumerator> +</enumerationType> <attribute> - <id>PROC_PCIE_PCS_RX_ROT_CDR_SSC</id> - <!-- TARGET_TYPE_PEC --> + <id>FUSED_CORE_MODE_HB</id> <description> - Value of PCS RX ROT CNTL CDR ssc - creator: platform - consumer: p9_pcie_scominit - firmware notes: - 0 for disable, 1 for enable + Stores the SMT setting used to determine fused mode. + SMT4_DEFAULT: Nimbus_DD1, boot in SMT4 but can change to SMT8 + SMT4_ONLY: Nimbus_DD2/Cumulus, set based on PVR info + SMT8_ONLY: Nimbus_DD2/Cumulus, set based on PVR info </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_ROT_CDR_SSC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> <attribute> - <id>PROC_PCIE_PCS_PCLCK_CNTL_PLLA</id> - <!-- TARGET_TYPE_PEC --> + <id>SOCKET_POWER_NOMINAL</id> <description> - Value of PCS pclck control plla - creator: platform - consumer: p9_pcie_scominit + The socket power in nominal mode. + Controls how much power can be used. + This is the same for all cores in the system. + Data is provided by MVPD #V. </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> + <simpleType><uint32_t></uint32_t></simpleType> + <persistency>volatile-zeroed</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_PCLCK_CNTL_PLLA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> <attribute> - <id>PROC_PCIE_PCS_PCLCK_CNTL_PLLB</id> - <!-- TARGET_TYPE_PEC --> + <id>SOCKET_POWER_TURBO</id> <description> - Value of PCS pclck control pllb - creator: platform - consumer: p9_pcie_scominit + The socket power in turbo mode. + Controls how much power can be used. + This is the same for all cores in the system. + Data is provided by MVPD #V. </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> + <simpleType><uint32_t></uint32_t></simpleType> + <persistency>volatile-zeroed</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_PCLCK_CNTL_PLLB</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> <attribute> - <id>PROC_PCIE_PCS_TX_DCLCK_ROT</id> - <!-- TARGET_TYPE_PEC --> + <id>WOF_TABLE_LID_NUMBER</id> <description> - Value of PCS tx dclck rotator override - creator: platform - consumer: p9_pcie_scominit + LID id used to load tables for Workload Optimized + Frequency (WOF) algorithms. + Producer: TMGT + Consumers: FW that selects VFRT tables </description> <simpleType> - <uint16_t></uint16_t> + <uint32_t> +<!-- @todo-RTC:172776-Get rid of default value that points to ZZ --> + <default>0x81E00440</default> + </uint32_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_TX_DCLCK_ROT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <writeable/> </attribute> <attribute> - <id>PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET</id> - <!-- TARGET_TYPE_PEC --> + <id>PROC_DCM_INSTALLED</id> <description> - Value of PCS tx fifo config offset - creator: platform - consumer: p9_pcie_scominit + PROC_CHIP Attribute + If true, the chip is installed on a Dual Chip Module + Provided by the Machine Readable Workbook </description> <simpleType> <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> -<attribute> - <id>PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG1</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS tx pcie receiver detect control register 1 - creator: platform - consumer: p9_pcie_scominit - </description> - <simpleType> - <uint16_t></uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> <attribute> - <id>PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG2</id> + <id>PROC_PCIE_PCS_RX_LOFF_CONTROL</id> <!-- TARGET_TYPE_PEC --> <description> - Value of PCS tx pcie receiver detect control register 2 + PCS rx loff control creator: platform consumer: p9_pcie_scominit + firmware notes: + The value of rx loff control for PCS. + Array index: Configuration number + index 0~3 for CONFIG0~3 </description> <simpleType> <uint16_t></uint16_t> + <array>4</array> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS tx power sequence enable - creator: platform - consumer: p9_pcie_scominit - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> @@ -23351,48 +6449,6 @@ Measured in GB</description> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_PHASE_ROTATOR_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_PCS_RX_VGA_CNTL_REG1</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS rx vga control register 1 - creator: platform - consumer: p9_pcie_scominit - </description> - <simpleType> - <uint16_t></uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_VGA_CNTL_REG1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_PCS_RX_VGA_CNTL_REG2</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS rx vga control register 2 - creator: platform - consumer: p9_pcie_scominit - </description> - <simpleType> - <uint16_t></uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_VGA_CNTL_REG2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> @@ -23408,11413 +6464,1217 @@ Measured in GB</description> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_RX_SIGDET_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_PCIE_PCS_SYSTEM_CNTL</id> - <!-- TARGET_TYPE_PEC --> - <description> - Value of PCS system control - creator: platform - consumer: p9_pcie_scominit - </description> - <simpleType> - <uint16_t></uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_SYSTEM_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_PCS_M_CNTL</id> + <id>PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET</id> <!-- TARGET_TYPE_PEC --> <description> - Value of PCS m1-m4 control + Value of PCS tx fifo config offset creator: platform consumer: p9_pcie_scominit - Array index: - 0 -> M1 - 1 -> M2 - 2 -> M3 - 3 -> M4 - </description> - <simpleType> - <uint16_t></uint16_t> - <array>4</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_PCS_M_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<!-- TODO: RTC 145692 - Temporary attributes used for p9_mss_eff_grouping test cases - These attributes need to be removed and test cases need to use - (TBD) attributes that specify the DIMM sizes used to calculate the - result of getDimmSize() function called in p9_mss_eff_grouping --> -<attribute> - <id>UNIT_TEST_MCA_MEMORY_SIZES</id> - <!-- TARGET_TYPE_PROC_CHIP --> - <description> The memory sizes behind the MCAs used for p9_mss_eff_grouping - test case. - Array [Port][DIMM] where num of ports = 8, num of dimms = 2 - </description> - <simpleType> - <uint32_t></uint32_t> - <array>8,2</array> - </simpleType> - <readable/> - <writeable/> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_UNIT_TEST_MCA_MEMORY_SIZES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_SWAP</id> - <description>PCIE IOP swap configuration - creator: platform - consumer: p9_pcie_scominit - firmware notes: - Encoded PCIE IOP swap configuration - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_SWAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <no_export/> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - firmware notes: - PCIe Gen3 PLL Control Register 0. - ATUNE/CPISEL. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - firmware notes: - PCIe Gen2/Gen1 PLL Control Register 0. - ATUNE/CPISEL. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe PLL Global Control Register 0. - REFISRC/REFISINK. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe PLL Global Control Register 1. - ENBGDOCPSRC/ENBGDOCAMP/REFVREG. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_PCS_CONTROL0</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe PCS Control Register 0. - BITLOCKTIME/ADDDREMDELTA_810_B/STARTUPDELTA_810_B/ADDDREMDELTA_810_A/ - STARTUPDELTA_A/RXREJECTHANDLING/EQCOMLETERESPONSE. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_PCS_CONTROL0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_PCS_CONTROL1</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe PCS Control Register 1. - RXSIGDETSETTING/ADDDREMDELTA_128130_B/STARTUPDELTA_128130_B/ - ADDDREMDELTA_128130_A/STARTUPDELTA_128130_A. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_PCS_CONTROL1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_TX_FIFO_OFFSET</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe TX FIFO Offset Register. - G3OFFSET/G2OFFSET/G1OFFSET. - Array index: Lane number (0:15) - </description> - <simpleType> - <uint32_t></uint32_t> - <array>16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_TX_RCVRDETCNTL</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe TX Receiver Detect Control Register. - VREFSEL/RCVRDETCNT/DETDRVC/PH1WAIT. - Array index: Lane number (0:15) - </description> - <simpleType> - <uint32_t></uint32_t> - <array>16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_TX_BWLOSS1</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe TX Bandwidth Loss Coefficient Register. - GEN3BWCOEFF/GEN2BWCOEFF/GEN1BWCOEFF. - Array index: Lane number (0:15) - </description> - <simpleType> - <uint32_t></uint32_t> - <array>16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_TX_BWLOSS1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_RX_VGA_CONTROL2</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe RX VGA Control Register 2. - GAIN2/GAIN1. - Array index: Lane number (0:15) - </description> - <simpleType> - <uint32_t></uint32_t> - <array>16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_RX_PEAK</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe RX Receiver Peaking Value Register. - PEAK1/PEAK2/PEAK3. - Array index: Lane number (0:15) - </description> - <simpleType> - <uint32_t></uint32_t> - <array>16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_RX_PEAK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_RX_SDL</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe RX Signal Detect Level Register. - SDLVL3/SDLVL2/SDLVL1. - Array index: Lane number (0:15) - </description> - <simpleType> - <uint32_t></uint32_t> - <array>16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_RX_SDL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_ZCAL_CONTROL</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe ZCAL Control Register. - CMPEVALDLY. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_ZCAL_CONTROL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_TX_FFE_GEN1</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe TX FFE (Gen1) - Array index: Lane number (0:15) - </description> - <simpleType> - <uint32_t></uint32_t> - <array>16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_TX_FFE_GEN1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_IOP_TX_FFE_GEN2</id><!-- @deprecated --> - <description> - creator: platform (MRW) - consumer: p9_pcie_scominit - notes: - PCIe TX FFE (Gen2) - Array index: Lane number (0:15) - </description> - <simpleType> - <uint32_t></uint32_t> - <array>16</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_IOP_TX_FFE_GEN2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IO_XBUS_DCCAL_FLAGS</id> - <!-- <targetType>TARGET_TYPE_XBUS</targetType> --> - <description> - Flags to indicate if rx / tx dccal has been run. - NONE = 0x0, - TX = 0x1, - RX = 0x2 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_IO_XBUS_DCCAL_FLAGS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IO_X_DEBUG</id> - <!-- <targetType>TARGET_TYPE_XBUS</targetType> --> - <description> - Indicate if debug data should be taken pre / post linktraining. - FALSE = 0x0, - TRUE = 0x1 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IO_X_DEBUG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IO_X_MFG_CHK</id> - <!-- <targetType>TARGET_TYPE_XBUS</targetType> --> - <description> - Indicate if manufacturing tests should be taken pre / post linktraining. - FALSE = 0x0, - TRUE = 0x1 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IO_X_MFG_CHK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IO_X_MFG_MIN_EYE_WIDTH</id> - <!-- <targetType>TARGET_TYPE_XBUS</targetType> --> - <description> - Minimum eye width to allow passing through manufacturing. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IO_X_MFG_MIN_EYE_WIDTH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IO_O_MFG_CHK</id> - <description> - Indicate if manufcaturing tests should be taken pre / post linktraining. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IO_O_MFG_CHK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IO_O_MFG_MIN_EYE_WIDTH</id> - <description> - Minimum eye width to allow passing through manufacturing. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IO_O_MFG_MIN_EYE_WIDTH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IO_XBUS_MASTER_MODE</id> - <description> - Flag to indicate if the target is a master. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_IO_XBUS_MASTER_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IO_XBUS_TX_MARGIN_RATIO</id> - <!-- <targetType>TARGET_TYPE_XBUS</targetType> --> - <description> - Value to select amount of margin to be applied. </description> <simpleType> <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IO_XBUS_TX_MARGIN_RATIO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>IO_XBUS_TX_FFE_PRECURSOR</id> - <!-- <targetType>TARGET_TYPE_XBUS</targetType> --> - <description> - Value to select amount of tx ffe precusor to apply. + <id>HOT_PLUG_POWER_CONTROLLER_INFO</id> + <description>Hot Plug Controller values for a specific processor. + Purpose: Holds information about the hot plug controllers so that a + Hardware procedure is able to turn them on and off. + Data Format: up to 8 Hot Plug Controllers x 7 variables of information + This data is at the processor level. + The needed information and their individual sizes are as follows: + (1) I2C Master processor engine (uint8_t) + (2) I2C Master processor port (uint8_t) + (3) Bus Speed (uint16_t value: 2 uint8_t values: MSB, LSB) + (4) Slave address (uint8_t) + (5) Device type (uint8_t: see SUPPORTED_HOT_PLUG enum) + (6) I2C Master processor node (uint8_t) + (7) I2C Master processor position (uint8_t) + Thus, the information will be 8 bytes. </description> <simpleType> <uint8_t> - <default>6</default> + <default>0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 + </default> </uint8_t> + <array>8,8</array> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IO_XBUS_TX_FFE_PRECURSOR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>POUNDV_BUCKET_NUM_OVERRIDE</id> - <description> - 1 if override of poundv bucket num is available. - 0 if override is unavailable. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> -<!--TODO RTC:144077 This should be volatile-zeroed but cannot test - without a way to do attribute overrides so we have to edit the system xml - to have one of the EQ's have override set--> - <persistency>volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_POUNDV_BUCKET_NUM_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>POUNDV_BUCKET_NUM</id> - <description> - Attribute in place to allow override of which POUNDV - bucket to use to set power management data. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> -<!--TODO RTC:144077 This should be volatile-zeroed but cannot test - without a way to do attribute overrides so we have to edit the system xml - to have one of the EQ's have override set--> - <persistency>volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_POUNDV_BUCKET_NUM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DUMP_STOP_INFO_SUPPRESS_ERROR_TRACE</id> - <description> - if set to 1, FAPI_ERR records are suppressed from being produced - by p9_dump_stop_info. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_DUMP_STOP_INFO_SUPPRESS_ERROR_TRACE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DUMP_STOP_INFO_ENABLE_ERRORLOG</id> - <description> - if set to 1, p9_dump_stop_info output will be written to error logs. - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_DUMP_STOP_INFO_ENABLE_ERRORLOG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SBE_IS_STARTED</id> - <description> - If 0, SBE for the processor has not been started. - Otherwise, SBE for the processor has been started. - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_IS_STARTED</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_CORE_FLOOR_RATIO</id> - <description> - Processor SMP core floor/nest frequency ratio - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_CORE_FLOOR_RATIO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_CORE_CEILING_RATIO</id> - <description> - Processor SMP core celing/nest frequency ratio - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_CORE_CEILING_RATIO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_OPTICS_CONFIG_MODE</id> - <description> - Per-link optics configuration - 0 = default = SMP - 1 = CAPI 2.0 - 2 = NV 2.0 - </description> - <simpleType> - <uint8_t></uint8_t> - <array>4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_X_ATTACHED_LINK_ID</id> - <description> - For each fabric X link on this chip, specifies the link ID of the chip at the - receiving end of the link. Should be considered valid only if corresponding - ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true. - </description> - <simpleType> - <uint8_t></uint8_t> - <array>7</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_X_ATTACHED_LINK_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_A_ATTACHED_LINK_ID</id> - <description> - For each fabric A link on this chip, specifies the link ID of the chip at the - receiving end of the link. Should be considered valid only if corresponding - ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true. - </description> - <simpleType> - <uint8_t></uint8_t> - <array>4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_A_ATTACHED_LINK_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_X_AGGREGATE</id> - <description> - Indicates if X links on this chip should be configured in aggregate mode. - OFF = 0x0, - ON = 0x1 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_X_AGGREGATE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_X_LINK_DELAY</id> - <description> - Average of local/remote end link delay counter values. - Used to designate coherent link in aggregate configurations. - Should be considered valid only if corresponding ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG - index is true. - OFF = 0x0, - ON = 0x1 - </description> - <simpleType> - <uint32_t></uint32_t> - <array>7</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_X_LINK_DELAY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_A_AGGREGATE</id> - <description> - Indicates if A links on this chip should be configured in aggregate mode. - OFF = 0x0, - ON = 0x1 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_A_AGGREGATE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FABRIC_A_LINK_DELAY</id> - <description> - Average of local/remote end link delay counter values. - Used to designate coherent link in aggregate configurations. - Should be considered valid only if corresponding ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG - index is true. - OFF = 0x0, - ON = 0x1 - </description> - <simpleType> - <uint32_t></uint32_t> - <array>4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FABRIC_A_LINK_DELAY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_GEN</id> - <description> - DRAM Device Type. - Decodes SPD byte 2. - Generation of memory: DDR3, DDR4. - creator: mss_eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_GEN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_TYPE</id> - <description> - Base Module Type. - Decodes SPD Byte 3 (bits 3~0). - Type of DIMM: RDIMM, UDIMM, LRDIMM as specified by the JEDIC standard. - creator: mss_eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_HYBRID_MEMORY_TYPE</id> - <description> - Hybrid Media. - Decodes SPD Byte 3 (bits 6~4) - creator: mss_eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_HYBRID_MEMORY_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_HYBRID</id> - <description> - Hybrid. - Decodes SPD Byte 3 (bit 7) - creator: mss_eff_config - consumer: various - firmware notes: none - NOT_HYBRID = 0, IS_HYBRID= 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_HYBRID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_DENSITY</id> - <description> - DRAM Density. - Decodes SPD Byte 4 (bits 3~0). - Total SDRAM capacity per die. - For multi-die stacks (DDP, QDP, or 3DS), this represents - the capacity of each DRAM die in the stack. - creator: mss_eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_DENSITY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_BANK_BITS</id> - <description> - Number of DRAM bank address bits. - Actual number of banks is 2^N, where - N is the number of bank address bits. - Decodes SPD Byte 4 (bits 5~4). - creator: spd_decoder - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_BANK_BITS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_BANK_GROUP_BITS</id> - <description> - Bank Groups Bits. - Decoded SPD Byte 4 (bits 7~6). - Actual number of bank groups is 2^N, - where N is the number of bank address bits. - This value represents the number of bank groups - into which the memory array is divided. - creator: mss_eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_BANK_GROUP_BITS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_COLUMN_BITS</id> - <description> - Column Address Bits. - Decoded SPD Byte 5 (bits 2~0). - Actual number of DRAM columns is 2^N, - where N is the number of column address bits - creator: mss_eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_COLUMN_BITS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_ROW_BITS</id> - <description> - Row Address Bits. - Decodes Byte 5 (bits 5~3). - Number of DRAM column address bits. - Actual number of DRAM rows is 2^N, - where N is the number of row address bits - creator: mss_eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_ROW_BITS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_PRIM_STACK_TYPE</id> - <description> - Primary SDRAM Package Type. - Decodes Byte 6. - This byte defines the primary set of SDRAMs. - Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS - creator: mss_eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_PRIM_STACK_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_PPR</id> - <description> - Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_PPR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_SOFT_PPR</id> - <description> - Soft Post Package Repair. Used in various locations and is evaluated in mss_eff_cnfg. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - NOT_SUPPORTED = 0, SUPPORTED = 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_SOFT_PPR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TRCD</id> - <description> - Minimum RAS to CAS Delay Time - in nck (number of clock cyles). - Decodes SPD byte 25 (7~0) and byte 112 (7~0). - Each memory channel will have a value. - creator: eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRCD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TRP</id> - <description> - SDRAM Row Precharge Delay Time - in nck (number of clock cycles). - Decodes SPD byte 26 (bits 7~0) and byte 121 (bits 7~0). - Each memory channel will have a value. - creator: eff_config - consumer: various - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TRAS</id> - <description> - Minimum Active to Precharge Delay Time - in nck (number of clock cycles). - Decodes SPD byte 27 (bits 3~0) and byte 28 (7~0). - Each memory channel will have a value. - creator: mss_eff_cnfg_timing - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRAS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TRC</id> - <description> - Minimum Active to Active/Refresh Delay - in nck (number of clock cyles). - Decodes SPD byte 27 (bits 7~4), byte 29 (bits 7~0), and byte 120. - Each memory channel will have a value. - creator: eff_confg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TRFC</id> - <description> - DDR4 Spec defined as Refresh Cycle Time (tRFC). - SPD Spec refers it to the Minimum Refresh Recovery Delay Time. - In nck (number of clock cyles). - Decodes SPD byte 31 (bits 15~8) and byte 30 (bits 7~0) for tRFC1. - Decodes SPD byte 33 (bits 15~8) and byte 32 (bits 7~0) for tRFC2. - Decodes SPD byte 35 (bits 15~8) and byte 34 (bits 7~0) for tRFC4. - Selected tRFC value depends on MRW attribute that selects refresh mode. - For 3DS, The tRFC time to the same logical rank is defined as tRFC_slr and is - specificed as the value as for a monolithic DDR4 SDRAM of equivalent density. - creator: eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint16_t> - </uint16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRFC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TFAW</id> - <description> - Minimum Four Activate Window Delay Time - in nck (number of clock cycles). - Decodes SPD byte 36 (bits 3~0) and byte 37 (bits 7~0). - For 3DS, tFAW time to the same logical rank is defined as - tFAW_slr_x4 or tFAW_slr_x8 (for x4 and x8 devices only) and - specificed as the value as for a monolithic DDR4 SDRAM - equivalent density. - Each memory channel will have a value. - creator: eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TFAW</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TRRD_S</id> - <description> - Minimum Activate to Activate Delay Time, different bank group - in nck (number of clock cycles). - Decodes SPD byte 38 (bits 7~0). - For 3DS, The tRRD_S time to a different bank group in the - same logical rank is defined as tRRD_slr and is - specificed as the value as for a monolithic - DDR4 SDRAM of equivalent density. - Each memory channel will have a value. - creator: eff_confg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRRD_S</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TRRD_L</id> - <description> - Minimum Activate to Activate Delay Time, same bank group - in nck (number of clock cycles). - Decodes SPD byte 39 (bits 7~0). - For 3DS, The tRRD_L time to the same bank group in the - same logical rank is defined as tRRD_L_slr and is - specificed as the value as for a monolithic - DDR4 SDRAM of equivalent density. - Each memory channel will have a value. - creator: eff_confg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TRRD_L</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TCCD_L</id> - <description> - Minimum CAS to CAS Delay Time, same bank group - in nck (number of clock cycles). - Decodes SPD byte 40 (bits 7~0) and byte 117 (bits 7~0). - This is for DDR4 MRS6. - Each memory channel will have a value. - Creator: eff_config - Consumer:various - Firmware notes: none - 4NCK = 4, 5NCK = 5, 6NCK = 6, 7NCK = 7, 8NCK = 8 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TCCD_L</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TWR</id> - <description> - Minimum Write Recovery Time. - Decodes SPD byte 41 (bits 3~0) and byte 42 (bits 7~0). - Each memory channel will have a value. - creator: mss_eff_cnfg_timing - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TWR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TWTR_S</id> - <description> - Minimum Write to Read Time, different bank group - in nck (number of clock cycles). - Decodes SPD byte 43 (3~0) and byte 44 (bits 7~0). - Each memory channel will have a value. - creator: eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TWTR_S</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TWTR_L</id> - <description> - Minimum Write to Read Time, same bank group - in nck (number of clock cycles). - Decodes byte 43 (7~4) and byte 45 (bits 7~0). - Each memory channel will have a value. - creator: eff_config - consumer: various - firmware notes: none - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TWTR_L</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_TMAW</id> - <description> - Maximum Activate Window - in nck (number of clock cycles). - Decodes SPD byte 7 (bits 5~4). - Depends on tREFI multiplier. - Each memory channel will have a value. - creator: mss_eff_cnfg - consumer: various - firmware notes: none - </description> - <simpleType> - <uint16_t> - </uint16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_TMAW</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC00</id> - <description> - F0BCW00 Host Interface DQ RTT_NOM Control - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC00</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC01</id> - <description> - F0BCW01 Host Interface DQ RTT_WR Control - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC01</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC02</id> - <description> - F0BCW02 Host Interface DQ RTT_PARK Control - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC02</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC03</id> - <description> - F0BCW03 Host Interface DQ Driver Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC03</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC04</id> - <description> - F0BCW04 DRAM Interface MDQ RTT Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC04</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC05</id> - <description> - F0BCW05 DRAM Interface MDQ Driver Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC05</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC06</id> - <description> - F0BCW06 Command Space Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC06</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC07</id> - <description> - F0BCW07 Rank Presence Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC07</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC08</id> - <description> - F0BCW08 RankSelection Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC08</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC09</id> - <description> - F0BCW09 Power Saving Settings Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC09</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC0A</id> - <description> - F0BCW0A LRDIMM Operating Speed - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC0A</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC0B</id> - <description> - F0BCW0B Operating Voltage Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC0B</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC0C</id> - <description> - F0BCW0C Buffer Training Mode Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC0C</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC0D</id> - <description> - F0BCW0D Reserved for future use - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC0D</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC0E</id> - <description> - F0BCW0E Parity Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC0E</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_BC0F</id> - <description> - F0BCW0F Error Status Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_BC0F</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>EFF_DIMM_DDR4_F0BC1x</id> - <description> - F0BCW1x Buffer Configuration Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F0BC1x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F30BC2x</id> - <description> - F30BCW2x Lower Nibble DRAM Interface Receive Enable Training Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F30BC2x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F30BC3x</id> - <description> - F30BCW3x Lower Nibble DRAM Interface Receive Enable Training Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F30BC3x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F30BC4x</id> - <description> - F30BCW4x Lower Nibble MDQS Read Delay Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F30BC4x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F30BC5x</id> - <description> - F30BCW5x Upper Nibble MDQS Read Delay Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F30BC5x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F0BC6x</id> - <description> - F0BCW6x Fine Granularity Frequency Operating Speed Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F0BC6x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F70BC7x</id> - <description> - F70BCW7x Function Space Selector Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F70BC7x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F30BC8x</id> - <description> - F30BCW8x Lower Nibble MDQ-MDQS Write Delay Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F30BC8x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F30BC9x</id> - <description> - F30BCW9x Upper Nibble MDQ-MDQS Write Delay Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F30BC9x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F30BCAx</id> - <description> - F30BCWAx Lower Nibble DRAM Interface Write Leveling Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F30BCAx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F30BCBx</id> - <description> - F30BCWBx Upper Nibble DRAM Interface Write Leveling Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F30BCBx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F0BCCx</id> - <description> - F0BCWCx Lower/Upper Nibble Additional Cycles of DRAM Interface Receive Enable Control Word for rank 0 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F0BCCx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F0BCDx</id> - <description> - F0BCWDx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 0 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F0BCDx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F0BCEx</id> - <description> - F0BCWEx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 0 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F0BCEx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F0BCFx</id> - <description> - F0BCWFx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 2 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F0BCFx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F1BCCx</id> - <description> - F1BCWCx Lower/Upper Nibble Additional Cycles of DRAM Interface Receive Enable Control Word for rank 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F1BCCx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F1BCDx</id> - <description> - F1BCWDx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F1BCDx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F1BCEx</id> - <description> - F1BCWEx Lower/Upper Nibble Additional Cycles of DRAM Interface Receive Enable Control Word for rank 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F1BCEx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F1BCFx</id> - <description> - F1BCWFx Lower/Upper Nibble Additional Cycles of DRAM Interface Write Leveling Control Word for rank 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F1BCFx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F4BC0x</id> - <description> - F4BCW0x MRS0 snooped settings - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F4BC0x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F4BC1x</id> - <description> - F4BCW1x MRS1 snooped settings - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F4BC1x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F4BC2x</id> - <description> - F4BCW2x MRS2 snooped settings - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F4BC2x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DIMM_DDR4_F4BC3x</id> + <id>PM_UNDERVOLTING_FRQ_MINIMUM</id> <description> - F4BCW3x MRS3 snooped settings - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F4BC3x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Override for Minimum frequency for which undervolting is allowed. -<attribute> - <id>EFF_DIMM_DDR4_F4BC4x</id> - <description> - F4BCW4x MRS4 snooped settings - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F4BC4x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + If value = 0, the value of VPD CPMin data point is passed to OCC FW via + Pstate SuperStructure. -<attribute> - <id>EFF_DIMM_DDR4_F4BC5x</id> - <description> - F4BCW5x MRS5 snooped settings - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F4BC5x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + If value != 0, this value will be passed to OCC FW via Pstate SuperStructure + as the floor frequency for enabled CPMs. -<attribute> - <id>EFF_DIMM_DDR4_F4BC6x</id> - <description> - F4BCW6x MRS6 snooped settings - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F4BC6x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. -<attribute> - <id>EFF_DIMM_DDR4_F5BC0x</id> - <description> - F5BCW0x Upper and Lower MPR bits[7:0] for U0 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F5BC0x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Consumer: OCC FW; OCC Lab Tools -<attribute> - <id>EFF_DIMM_DDR4_F5BC1x</id> - <description> - F5BCW1x Upper and Lower MPR bits[15:8] for U1 + Provided by the Machine Readable Workbook. </description> <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> + <uint8_t></uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F5BC1x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>EFF_DIMM_DDR4_F5BC2x</id> + <id>PM_UNDERVOLTING_FREQ_MAXIMUM</id> <description> - F5BCW2x Upper and Lower MPR bits[23:16] for U2 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F5BC2x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Override for Maximum frequency for which undervolting is allowed. -<attribute> - <id>EFF_DIMM_DDR4_F5BC3x</id> - <description> - F5BCW3x Upper and Lower MPR bits[31:24] for U3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F5BC3x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + If value = 0, the value of VPD Turbo data point is passed to OCC FW via + Pstate SuperStructure. -<attribute> - <id>EFF_DIMM_DDR4_F5BC5x</id> - <description> - F5BCW5x Host Interface Vref Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F5BC5x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + If value != 0, this value will be passed to OCC FW via Pstate SuperStructure + as the ceiling frequency for enabled CPMs. -<attribute> - <id>EFF_DIMM_DDR4_F5BC6x</id> - <description> - F5BCW6x DRAM Interface Vref Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F5BC6x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Will be internally rounded to the nearest ATTR_PROC_REFCLK_FREQUENCY / 8 value. -<attribute> - <id>EFF_DIMM_DDR4_F6BC0x</id> - <description> - F6BCW0x Upper and Lower MPR bits[39:32] for U4 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F6BC0x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Consumer: OCC FW; OCC Lab Tools -<attribute> - <id>EFF_DIMM_DDR4_F6BC1x</id> - <description> - F6BCW1x Upper and Lower MPR bits[47:40] for U5 + Provided by the Machine Readable Workbook. </description> <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> + <uint8_t></uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F6BC1x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>EFF_DIMM_DDR4_F6BC2x</id> - <description> - F6BCW2x Upper and Lower MPR bits[55:48] for U6 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F6BC2x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <id>PM_WINKLE_ENTRY</id> + <description>Setting depends on di/dt charateristics of the system. -<attribute> - <id>EFF_DIMM_DDR4_F6BC3x</id> - <description> - F6BCW3x Upper and Lower MPR bits[63:56] for U7 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F6BC3x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Set Assisted if power off serialization is needed and WINKLE_TYPE=Fast; + Set to Hardware if the system can handle the unrelated powering off between cores. + Hardware setting decreases entry latency -<attribute> - <id>EFF_DIMM_DDR4_F6BC4x</id> - <description> - F6BCW4x Buffer Training Configuration Control Word - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F6BC4x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Producer: MRWB -<attribute> - <id>EFF_DIMM_DDR4_F6BC5x</id> - <description> - F6BCW5x Buffer Training Status Word + Consumer: p8_poreslw_init.C </description> <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> + <uint8_t></uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F6BC5x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>EFF_DIMM_DDR4_F74BC8x</id> - <description> - F74BCW8x MDQ0/4 -Read Delay Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F74BC8x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + <id>PM_WINKLE_EXIT</id> + <description>Setting depends on di/dt charateristics of the system and the setting of ATTR_PM_WINKLE_TYPE. -<attribute> - <id>EFF_DIMM_DDR4_F74BC9x</id> - <description> - F74BCW9x MDQ1/5 -Read Delay Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F74BC9x</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Set to Assisted if power on serialization is needed and WINKLE_TYPE=Fast; Set to Hardware if the system + can handle the unrelated powering off between cores. Hardware setting decreases entry latency. + Must be set to Assisted if ATTR_PM_WINKLE_TYPE=Deep as this necessary for restore. -<attribute> - <id>EFF_DIMM_DDR4_F74BCAx</id> - <description> - >F74BCWAx MDQ2/6 -Read Delay Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F74BCAx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Setting to Hardware is a test mode for Fast only. -<attribute> - <id>EFF_DIMM_DDR4_F74BCBx</id> - <description> - F74BCWBx MDQ3/7 -Read Delay Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F74BCBx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Producer: MRWB -<attribute> - <id>EFF_DIMM_DDR4_F74BCCx</id> - <description> - F74BCWCx MDQ0/4-MDQS Write Delay Control Word for ranks 0 to 3 + Consumer: p8_poreslw_init.C </description> <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> + <uint8_t></uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F74BCCx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>EFF_DIMM_DDR4_F74BCDx</id> + <id>PM_SPIVID_PORT_ENABLE</id> <description> - F74BCWDx MDQ1/5-MDQS Write Delay Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F74BCDx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + PROC_CHIP Attribute + Defines the configuration of the SPIVID ports from the target. + - NONE means that no VRM is attached. + - PORTxNONRED means that the indicated port is used in a non-redundant + configuration. + - REDUNDANT means that all three are connected and considered redundant. -<attribute> - <id>EFF_DIMM_DDR4_F74BCEx</id> - <description> - F74BCWEx MDQ2/6-MDQS Write Delay Control Word for ranks 0 to 3 + Provided by the Machine Readable Workbook. </description> <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> + <uint8_t></uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F74BCEx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>EFF_DIMM_DDR4_F74BCFx</id> + <id>PM_PBAX_NODEID</id> <description> - F74BCWFx MDQ3/7-MDQS Write Delay Control Word for ranks 0 to 3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DIMM_DDR4_F74BCFx</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + DEPRECATED!!! Use PBAX_GROUPID instead + PROC_CHIP Attribute + Receive PBAX Nodeid. Value that indicates this PBA's PBAX Node affinity. + This is matched to pbax_nodeid of the PMISC Address phase. -<attribute> - <id>MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> - <description> - Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_port - Set to below optimum value/ rate. - On a per port (MCA) basis - Consumer: thermal_init + Provided by the Machine Readable Workbook. </description> <simpleType> - <uint16_t> - </uint16_t> + <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id> + <id>PM_SLEEP_ENTRY</id> <description> - Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_slot - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + PROC_CHIP Attribute -<attribute> - <id>MSS_MRW_MEM_M_DRAM_CLOCKS</id> - <description> - Machine Readable Workbook for the number of M DRAM clocks. - One approach to curbing DRAM power usage is by throttling - traffic through a programmable N commands over M window. - </description> - <simpleType> - <uint32_t> - <default>0x00000200</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> +Set Assisted if power off serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency -<attribute> - <id>MSS_MRW_AVDD_OFFSET_DISABLE</id> - <description> - Used for to determine whether to apply an offset to AVDD. Supplied by MRW. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_AVDD_OFFSET_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> +Producer: MRWB -<attribute> - <id>MSS_MRW_VDD_OFFSET_DISABLE</id> - <description> - Used for to determine whether to apply an offset to VDD. Supplied by MRW +Consumer: proc_pm_init and proc_pcbs_init </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_VDD_OFFSET_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>MSS_MRW_VCS_OFFSET_DISABLE</id> + <id>PM_SLEEP_EXIT</id> <description> - Used for to determine whether to apply an offset to VCS. Supplied by MRW. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_VCS_OFFSET_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + PROC_CHIP Attribute -<attribute> - <id>MSS_MRW_VPP_OFFSET_DISABLE</id> - <description> - Used for to determine whether to apply an offset to VPP. Supplied by MRW. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_VPP_OFFSET_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> +Set to Assisted if power on serialization is needed and SLEEP_TYPE=Fast; Set to Hardware if the system can handle the unrelated powering off between cores. Hardware setting decreases entry latency +Must be set to Assisted if ATTR_PM_SLEEP_TYPE=Deep as this necessary for restore. -<attribute> - <id>MSS_MRW_VDDR_OFFSET_DISABLE</id> - <description> - Used for to determine whether to apply an offset to VDDR. Supplied by MRW. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_VDDR_OFFSET_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> +Setting to Hardware is a test mode for Fast only. -<attribute> - <id>MSS_MRW_FINE_REFRESH_MODE</id> - <description> - Fine refresh mode. - Should be defaulted to normal mode. - This is for DDR4 MRS3. +Producer: MRWB + +Consumer: proc_pm_init and proc_pcbs_init. </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_FINE_REFRESH_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>MRW_TEMP_REF_RANGE</id> + <id>PM_SLEEP_TYPE</id> <description> - Temp ref range. - Should be defaulted to extended range. - This is for DDR4 MRS4. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MRW_TEMP_REF_RANGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + PROC_CHIP Attribute +Selects which voltage level to place the Core domain PFETs upon Sleep entry. 0 = Vret (Fast Sleep Mode), 1 = Voff (Deep Sleep Mode) +Producer: MRWB -<attribute> - <id>MSS_MRW_TEMP_REFRESH_RANGE</id> - <description> - Temp ref range. - Should be defaulted to extended range. - This is for DDR4 MRS4. - Should be defaulted to extended range. - NORMAL for running at 85 degrees C or less, EXTENDED for 95 or less degrees C - Used for calculating periodic refresh intervals - JEDEC DDR4 spec 1716.78C from 07-2016 - page 46 4.8.1 +Consumer: proc_pm_init and proc_pcbs_init </description> <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> + <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_TEMP_REFRESH_RANGE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> -<!--Deprecated--> <attribute> - <id>MSS_MRW_RESET_DELAY_BEFORE_CAL</id> - <description> - For resetting the phy delay values at the beginning of - calling mss_draminit_training. YES means the values will be reset. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<!--Deprecated--> - -<attribute> - <id>MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS</id> + <id>PM_WINKLE_TYPE</id> <description> - Describes the settings for periodic calibration for all ports: - Reading left to right + PROC_CHIP Attribute +Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode) </description> <simpleType> - <uint16_t> - </uint16_t> + <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> - <attribute> - <id>MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS</id> + <id>MSS_PHY_SEQ_REFRESH</id> <description> - Describes the settings for periodic ZQ calibration for all ports: - Reading left to right. For each bit: OFF = 0, ON = 1. - Setting to 0 indicates to disable periodic zqcal. - Byte 0: - 0: ZQCAL - All others reserved for future use + Controls ENABLE/DISABLE of workaround that sets + the PHY sequencer to trigger refresh after draminit. </description> <simpleType> - <uint16_t> - </uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_0_VERSION_LAYOUT</id> - <description>MR Keyword Layout Version Number. Increases when attributes are added, removed, or redefined. Does not reset.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_0_VERSION_LAYOUT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_VPD_MR_1_VERSION_DATA</id> - <description>MR Keyword Data Version Number. Increases when data changes with the above layout version. Resets when layout version number increments.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_1_VERSION_DATA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_2_SIGNATURE_HASH</id> - <description>Hash Signature for the MR Keyword. The hash signature is 32bits for 256 bytes of data.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_2_SIGNATURE_HASH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_VPD_MR_DRAM_2N_MODE</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_DRAM_2N_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2</id> - <description>Place holder description</description> - <simpleType> <uint8_t></uint8_t> <array>2</array> </simpleType> <persistency>volatile-zeroed</persistency> - <writeable/> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CLK_D0_P0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CLK_D0_P0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CLK_D0_P1</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> <writeable/> - <readable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CLK_D0_P1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CLK_D1_P0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CLK_D1_P0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CLK_D1_P1</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CLK_D1_P1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>VPD_MR_0_VERSION_LAYOUT</id> - <description>MR Keyword Layout Version Number. Increases when attributes are added, removed, or redefined. Does not reset.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_0_VERSION_LAYOUT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>VPD_MR_1_VERSION_DATA</id> - <description>MR Keyword Data Version Number. Increases when data changes with the above layout version. Resets when layout version number increments.</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_1_VERSION_DATA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_2_SIGNATURE_FREQ_DROP</id> - <description>MR Keyword type, nibble 0 = freq bin (0 = 1600, 1 = 1866, 2 = 2133, 3 = 2400, 4 = 2667, 5 = 2933, 6 = 3200), nibble 1 = num dimms per port (1 = single drop, 2 = dual drop)</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_2_SIGNATURE_FREQ_DROP</id> - <macro>DIRECT</macro> + <id>ATTR_MSS_PHY_SEQ_REFRESH</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> - <id>VPD_MR_2_SIGNATURE_HASH</id> - <description>Hash Signature for the MR Keyword. The hash signature is 32bits for 256 bytes of data.</description> + <id>PRD_HWP_PLID</id> + <description> + PRD will perform error isolation for certain errors that may cause a HWP + to fail. This attribute will be used by the HWP to store the PLID so that + PRD can subsequently check it for a non-zero value and link the HWP PLID + to the PRD error log. + </description> <simpleType> <uint32_t> + <default>0</default> </uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_2_SIGNATURE_HASH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>VPD_MR_DRAM_2N_MODE</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_DRAM_2N_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A00</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A00</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A01</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A01</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A02</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A02</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A03</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A03</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A04</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A04</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A05</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A05</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A06</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A06</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A07</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A07</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A08</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A08</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A09</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A09</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A10</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A10</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A11</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A11</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A12</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A12</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A13</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A13</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_A17</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_A17</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_BA0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_BA0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_BA1</id> - <description>Place holder description</description> + <id>SLOT_NAME</id> + <description>PCIe slot name definition</description> <simpleType> <uint8_t> </uint8_t> - <array>2</array> </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_BA1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <no_export/> </attribute> <attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_BG0</id> - <description>Place holder description</description> + <id>SLOT_INDEX</id> + <description>PCIe slot index definition</description> <simpleType> <uint8_t> </uint8_t> - <array>2</array> </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_BG0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <no_export/> </attribute> <attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_BG1</id> - <description>Place holder description</description> + <id>PCIE_32BIT_MMIO_SIZE</id> + <description>PCIe slot 32bit MMIO size definition</description> <simpleType> <uint8_t> </uint8_t> - <array>2</array> </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_BG1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <no_export/> </attribute> -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_C0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_C0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> <attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_C1</id> - <description>Place holder description</description> + <id>PCIE_64BIT_MMIO_SIZE</id> + <description>PCIe slot 64bit MMIO size definition</description> <simpleType> <uint8_t> </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_C1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_ADDR_C2</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_ADDR_C2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CLK_D0_P0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CLK_D0_P0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CLK_D0_P1</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CLK_D0_P1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CLK_D1_P0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CLK_D1_P0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CLK_D1_P1</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CLK_D1_P1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CMD_ACTN</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CMD_ACTN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CMD_PAR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CMD_PAR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_CKE0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_CKE0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_CKE1</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_CKE1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_CKE2</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_CKE2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_CKE3</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_CKE3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_CSN0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_CSN0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_CSN1</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_CSN1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_CSN2</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_CSN2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_CSN3</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_CSN3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0</id> -<description>Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1</id> - <description>Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0</id> - <description>Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1</id> - <description>Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_ODT0</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_ODT0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_ODT1</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_ODT1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_ODT2</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_ODT2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_CNTL_ODT3</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_CNTL_ODT3</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0</id> - <description>Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1</id> - <description>Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0</id> - <description>Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1</id> - <description>Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_2N_MODE_AUTOSET</id> - <description>Default value for 2N Mode from Signal Integrity.</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_VPD_MR_PERIODIC_MEMCAL_MODE_OPTIONS</id> - <description>Place holder description</description> - <simpleType> - <uint16_t></uint16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_PERIODIC_MEMCAL_MODE_OPTIONS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>VPD_MR_PERIODIC_MEMCAL_MODE_OPTIONS</id> - <description>Place holder description</description> - <simpleType> - <uint16_t></uint16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_PERIODIC_MEMCAL_MODE_OPTIONS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_VPD_MR_TSYS_ADR</id> - <description> - ADR WRClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of clock. - Phase Rotator Static Offset value used to determine the Phase of the WrClk with respect to SysClk. - For zero delay simulations, or simulations where the delay of the SysClk tree and the WrClk tree are equal, - Set this field to 60h - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_TSYS_ADR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_TSYS_DATA</id> - <description> - DP16 WrClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of clock. - Phase Rotator Static Offset value used to determine the Phase of the WrClk with respect to SysClk. - For zero delay simulations, or simulations where the delay of the SysClk tree and the WrClk tree are equal, - Set this field to 60h - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_TSYS_DATA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_D0_CLK0</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_D0_CLK0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_D0_CLK1</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_D0_CLK1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_D1_CLK0</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_D1_CLK0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MR_MC_PHASE_ROT_D1_CLK1</id> - <description>Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of one cycle of clock.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MR_MC_PHASE_ROT_D1_CLK1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_0_VERSION_LAYOUT</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_0_VERSION_LAYOUT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_1_VERSION_DATA</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_1_VERSION_DATA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_2_SIGNATURE_HASH</id> - <description>Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of data.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_2_SIGNATURE_HASH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_CKE_PRI_MAP</id> - <description>Place holder description</description> - <simpleType> - <uint16_t></uint16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_CKE_PRI_MAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_CKE_PWR_MAP</id> - <description>Place holder description</description> - <simpleType> - <uint32_t></uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_CKE_PWR_MAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_DIMM_RCD_IBT_CA</id> - <description>Register Clock Driver, Input Bus Termination for Command/Address in tens of Ohms</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_DIMM_RCD_IBT_CKE</id> - <description>Register Clock Driver, Input Bus Termination for Clock Enable in tens of Ohms.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_DIMM_RCD_IBT_CS</id> - <description>Register Clock Driver, Input Bus Termination for Chip Select in tens of Ohms.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_DIMM_RCD_IBT_ODT</id> - <description>Register Clock Driver, Input Bus Termination for Clock Enable in tens of Ohms.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_DIMM_RCD_OUTPUT_TIMING</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_DIMM_RCD_OUTPUT_TIMING</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_DRAM_RTT_NOM</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_DRAM_RTT_NOM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - - <attribute> - <id>MSS_VPD_MT_DRAM_RTT_PARK</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_DRAM_RTT_PARK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_DRAM_RTT_WR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_DRAM_RTT_WR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_DRV_IMP_CLK</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_DRV_IMP_CNTL</id> - <description>Memory Controller side Drive Impedance for Clock Enable, - ODT, Parity, and Reset Lines in Ohms.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_DRV_IMP_CSCID</id> - <description> - Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_DRV_IMP_DQ_DQS</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,5</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_RCV_IMP_DQ_DQS</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2, 5</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_PREAMBLE</id> - <description>Number of clocks used for preamble. - Calibration only uses 1 nCK preamble (DEFAULT). - Mainline has both 1 nCK and 2 nCK preamble option.</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_PREAMBLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_SLEW_RATE_ADDR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_SLEW_RATE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_SLEW_RATE_CLK</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_SLEW_RATE_CLK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_SLEW_RATE_CNTL</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_SLEW_RATE_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_SLEW_RATE_DQ_DQS</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_SLEW_RATE_DQ_DQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_SLEW_RATE_SPCKE</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_SLEW_RATE_SPCKE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_ODT_RD</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_ODT_RD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_ODT_WR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_ODT_WR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_OFFSET_GPO</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_OFFSET_GPO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_OFFSET_RLO</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_OFFSET_RLO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_OFFSET_WLO</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_OFFSET_WLO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_VREF_DRAM_WR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_VREF_DRAM_WR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_VREF_MC_RD</id> - <description>Place holder description</description> - <simpleType> - <uint32_t></uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_VREF_MC_RD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_WINDAGE_RD_CTR</id> - <description>Place holder description</description> - <simpleType> - <int16_t></int16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_WINDAGE_RD_CTR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_0_VERSION_LAYOUT</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_0_VERSION_LAYOUT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_1_VERSION_DATA</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_1_VERSION_DATA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_2_SIGNATURE_HASH</id> - <description>Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of data.</description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_2_SIGNATURE_HASH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - - -<attribute> - <id>VPD_MT_2_SIGNATURE_DIMM0RANK_DIMM1RANK</id> - <description>Place holder description</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_2_SIGNATURE_DIMM0RANK_DIMM1RANK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_CKE_PRI_MAP</id> - <description>Place holder description</description> - <simpleType> - <uint16_t></uint16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_CKE_PRI_MAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_CKE_PWR_MAP</id> - <description>Place holder description</description> - <simpleType> - <uint32_t></uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_CKE_PWR_MAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_DIMM_RCD_IBT</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_DIMM_RCD_IBT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_DIMM_RCD_OUTPUT_TIMING</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_DIMM_RCD_OUTPUT_TIMING</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_DRAM_DRV_IMP_DQ_DQS</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_DRAM_DRV_IMP_DQ_DQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_DRAM_RTT_NOM</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_DRAM_RTT_NOM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - - <attribute> - <id>VPD_MT_DRAM_RTT_PARK</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_DRAM_RTT_PARK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_DRAM_RTT_WR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_DRAM_RTT_WR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_MC_DRV_IMP_ADDR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_MC_DRV_IMP_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_MC_DRV_IMP_CLK</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_MC_DRV_IMP_CLK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_MC_DRV_IMP_CNTL</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_MC_DRV_IMP_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_MC_DRV_IMP_DQ_DQS</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_MC_DRV_IMP_DQ_DQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_MC_DRV_IMP_SPCKE</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_MC_DRV_IMP_SPCKE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_MC_RCV_IMP_DQ_DQS</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_MC_RCV_IMP_DQ_DQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_MC_SLEW_RATE_ADDR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_MC_SLEW_RATE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_MC_SLEW_RATE_CLK</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_MC_SLEW_RATE_CLK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_MC_SLEW_RATE_CNTL</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_MC_SLEW_RATE_CNTL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_MC_SLEW_RATE_DQ_DQS</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_MC_SLEW_RATE_DQ_DQS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_MC_SLEW_RATE_SPCKE</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_MC_SLEW_RATE_SPCKE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_ODT_RD</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_ODT_RD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_ODT_WR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_ODT_WR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_OFFSET_GPO</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_OFFSET_GPO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_OFFSET_RLO</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_OFFSET_RLO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_OFFSET_WLO</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_OFFSET_WLO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_VREF_DRAM_WR</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_VREF_DRAM_WR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_VREF_MC_RD</id> - <description>Place holder description</description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_VREF_MC_RD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VPD_MT_WINDAGE_RD_CTR</id> - <description>Place holder description</description> - <simpleType> - <uint16_t></uint16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VPD_MT_WINDAGE_RD_CTR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MRW_DRAMINIT_RESET_DISABLE</id> - <description>A disable switch for resetting the phy delay values at the beginning of calling mss_draminit_training.</description> - <simpleType> - <uint8_t></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MRW_DRAMINIT_RESET_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SECURITY_ENABLE</id> - <description>Holds the state of Security Access Bit (SAB)</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SECURITY_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_PREFETCH_ENABLE</id> - <description>0 = OFF 1 = ON Value of on or off. Determines if prefetching enabled or not. See chapter 7 of the Centaur Workbook.</description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_PREFETCH_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_CLEANER_ENABLE</id> - <description> - Value of on or off. - Determines if the cleaner of the L4 cache (write modified entries to memory on idle cycles) - enabled or not. See chapter 7 of the Centaur Workbook. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_CLEANER_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PFET_OFF_CONTROLS</id> - <description> - To disable force pfet off control from fuse status - Override attribute - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PFET_OFF_CONTROLS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>PIBMEM_REPAIR0</id> - <description> - Pibmem repair attribute 0 - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PIBMEM_REPAIR0</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>PIBMEM_REPAIR1</id> - <description> - Pibmem repair attribute 1 - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PIBMEM_REPAIR1</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!--SBE ONLY--> -<attribute> - <id>PIBMEM_REPAIR2</id> - <description> - Pibmem repair attribute 2 - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PIBMEM_REPAIR2</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SENSEADJ_STEP</id> - <description> - IPL for skew adjust and duty cycle adjust - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SENSEADJ_STEP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <no_export/> </attribute> <attribute> - <id>SUPPORTS_DYNAMIC_MEM_VOLT</id> - <description> - Do we support dynamically updating memory voltages? - 0 = no, 1 = yes - </description> + <id>PCIE_32BIT_DMA_SIZE</id> + <description>PCIe slot 32bit DMA size definition</description> <simpleType> <uint8_t> - <default>0</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> + <no_export/> </attribute> <attribute> - <id>PROC_NHTM_BAR_BASE_ADDR</id> - <description> The base address where the NHTM traces start. They are - calculated based on the NHTM trace size requested by user. - This address in memory will be the location where NHTM0/1 - traces are output. - Set by p9_mss_eff_grouping. - Used by p9_setup_bars and p9_htm_setup. - </description> - <simpleType><uint64_t></uint64_t></simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NHTM_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_NHTM_BAR_SIZE</id> - <description> The amount of memory a user can reserve to store NHTM traces. - This amount will be used to store both NHTM0 and NHTM1 traces. - Used by p9_mss_eff_grouping. - </description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NHTM_BAR_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_CHTM_BAR_BASE_ADDR</id> - <description> The base addresses where the CHTM traces start. They are - calculated based on the CHTM trace sizes requested by users. - There are 24 different CHTM regions, thus 24 different sizes. - Each region is to store HTM trace for a core. - Set by p9_mss_eff_grouping. - Used by p9_setup_bars. - </description> - <simpleType> - <uint64_t></uint64_t> - <array>24</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_CHTM_BAR_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_CHTM_BAR_SIZES</id> - <description> The amount of memory a user can reserve to store CHTM traces. - There are 24 cores, thus 24 different sizes. - Used by p9_mss_eff_grouping. - </description> - <simpleType> - <uint64_t> - </uint64_t> - <array>24</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_CHTM_BAR_SIZES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NHTM_TRACE_TYPE</id> - <description> The Nest HTM trace type desired to be collected. This setting - is applied to both NHTM0 and NHTM1. - DISABLE = 0x0, FABRIC = 0x1, EVENT = 0x2, OCC = 0x3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NHTM_TRACE_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CHTM_TRACE_TYPE</id> - <description> The Core HTM trace type desired to be collected. - DISABLE = 0x0, CORE = 0x1, LLAT = 0x2, PPE = 0x3, DMW = 0x4 - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>24</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CHTM_TRACE_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_TTYPEFILT_PAT</id> - <description> Nest HTM: defines the TTYPE pattern to match in Fabric trace - mode. These bits are used with the ttype Filter Mask to - indicate the TTYPE value that should be matched on the rcmd. - HTM Ttype Filter Control Register (1:7). - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_TTYPEFILT_PAT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_TSIZEFILT_PAT</id> - <description> Nest HTM: defines the TSIZE pattern to match in Fabric trace - mode. These bits are used with the tsize filter mask to indicate - the TSIZE value that should be matched on the rcmd - HTM Ttype Filter Control Register (8:15). - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_TSIZEFILT_PAT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_TTYPEFILT_MASK</id> - <description> Nest HTM: TTYPE pattern mask. - If mask bit is clear to 0, then do not need to match w/ the pattern. - If all mask bits are clear, no TTYPE pattern/masking is done. - The inversion of this attribute value will be programmed into - bits 17:23 of HTM Ttype Filter Control Register. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_TTYPEFILT_MASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_TSIZEFILT_MASK</id> - <description> Nest HTM: TSIZE pattern mask. - If mask bit is clear to 0, then do not need to match w/ the pattern. - If all mask bits are clear, no TSIZE pattern/masking is done. - The inversion of this attribute value will be programmed into - bits 24:31 of HTM Ttype Filter Control Register. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_TSIZEFILT_MASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_TTYPEFILT_INVERT</id> - <description> Nest HTM: TTYPE/TSIZE Capture Invert. - HTM Ttype Filter Control Register (32). - This bit controls the inversion of the ttype/tsize filter. - 0 : Capture record based on ttype/tsize pattern matching - 1 : Capture record based on ttype/tsize pattern NOT matching - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_TTYPEFILT_INVERT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_CRESPFILT_INVERT</id> - <description> Nest HTM: CRESP Filter Capture Invert. - HTM Ttype Filter Control Register (33). - This bit controls the inversion of the cresp filter. - 0: Capture record based on cresp filter pattern/mask match - 1: Capture record based on cresp filter pattern/mask NOT matching. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_CRESPFILT_INVERT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_FILT_PAT</id> - <description> Nest HTM: Filter Pattern. - HTM Filter Control Register (0:22). - In Fabric trace mode, defines the TTAG/Scope/Source pattern to - match in the RCMD and CRESP: - 0:3 rcmd_ttag(0:2) Group ID Pattern for rcmd and cresp - filtering. - 4:6 rcmd_ttag(3:5) Chip ID Pattern for rcmd and cresp - filtering. - 7:16 rcmd_ttag(6:13) Unit ID Pattern for rcmd and cresp - (if from this chip) filtering. - 17:19 rcmd_scope(0:2) Scope Pattern for rcmd and cresp - filtering. - 20:21 rcmd_source(0:1) Source Pattern for rcmd filtering. - 22 Powerbus PORT pattern for rcmd and cresp filtering. - In OCC trace mode, defines the occ_trace_data(0:22) pattern - to match: - 0:22 occ_trace_data(0:22) pattern. - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_FILT_PAT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_FILT_CRESP_PAT</id> - <description> Nest HTM: defines the CRESP Filter pattern in FABRIC trace mode. - HTM Filter Control Register (27:31). - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_FILT_CRESP_PAT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_FILT_MASK</id> - <description> Nest HTM FABRIC: Pattern mask. - HTM Filter Control Register (32:54). - Bits clear to 0 in this mask do not need to match with the - Filter Pattern. - If all bits are clear, no pattern/masking is done and all - Cresp/rcmd are captured in Fabric trace mode and all - OCC commands are captured in OCC mode. - The inversion of this attribute value will be programmed into - bits 32:54 of HTM Ttype Filter Control Register. - In Fabric Trace Mode: - 32:35: rcmd_ttag(0:3) Group ID Mask - 36:38: rcmd_ttag(4:6) Chip ID Mask - 39:48: rcmd_ttag(7:16) Unit ID Pattern - 49:51: rcmd_scope(0:2) Mask - 52:53: rcmd_source(0:1) Mask - 54in the : PowerBus PORT MASK (for rcmd and cresp filtering0 - In OCC Trace Mode - 32:54 occ_trace_data(0:22) Mask - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_FILT_MASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_FILT_CRESP_MASK</id> - <description> Nest HTM FABRIC: CRESP Filter Mask. - HTM Filter Control Register (59:63). - If mask bit is clear to 0, then do not need to match w/ the CRESP - Filter pattern. - If all mask bits are clear, no pattern matching is done. - The inversion of this attribute value will be programmed into - bits 59:63 of HTM Ttype Filter Control Register. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_FILT_CRESP_MASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NHTM_HTMSC_MODE_CONTENT_SEL</id> - <description> Nest HTM: defines the NHTM trace mode. - HTM Collection Mode Register (1:2). - Only FABRIC is supported at this time. - FABRIC = 0x0, EVENT = 0x1, OCC = 0x2 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NHTM_HTMSC_MODE_CONTENT_SEL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES</id> - <description> Nest HTM: defines if the generated data writes are captured. - HTM Collection Mode Register (4). - 0 - Ignore HTM generated data writes - 1 - Capture even HTM generated writes if they meet the filtering - criteria. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL</id> - <description> Nest HTM: defines if the filtering will apply to ttype=PMISC - and ttype=Report Hang commands when filtering is enabled. - HTM Collection Mode Register (5). - 0 - filtering ignored on PMISC - 1 - Apply filtering to PMISC also - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE</id> - <description> Nest HTM: defines if Precise cresp mode is disabled. - 0 - Disable precisce cresp mode - 1 - Enable precisce cresp mode - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION</id> - <description> Nest HTM: defines Limit Memory Allocation mode. - 0 - Pre-allocate maximum memory buffers (NHTM=8) - 1 - Pre-allocate only one half maximum memory buffers - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD</id> - <description> Nest HTM: defines PMISC only Command trace mode. - 0 rCmd amd cResp port 0 only goes to NHTM0 - 1 rCmd and Cresp port 0 is stored alternately to NHTM0 and - NHTM1, switching based for each valid - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NHTM_HTMSC_MODE_SYNC_STAMP_FORCE</id> - <description> Control the number of cycles to wait to force a synchronization - stamp or reset the timer. For NHTM only. - HTM Collection Mode Register (19:21). - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NHTM_HTMSC_MODE_SYNC_STAMP_FORCE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NHTM_HTMSC_MODE_WRITETOIO</id> - <description> Use space option. For NHTM only. - HTM Collection Mode Register (22). - 0 = Use HTM_CL_Write op to target system memory. - Do pre-allocation sequence. (default) - 1 = Use ci_pr_st op to target anywhere else. - Dont do pre-allocate sequence. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NHTM_HTMSC_MODE_WRITETOIO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CHTM_HTMSC_MODE_CONTENT_SEL</id> - <description> Core HTM: defines the CHTM trace mode. - HTM Collection Mode Register (1:2). - Only Direct Memory Write mode (IMA) is supported at this time. - CI = 0x0, LLAT = 0x1, PPE = 0x2, DMW = 0x3 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CHTM_HTMSC_MODE_CONTENT_SEL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CHTM_HTMSC_MODE_CAPTURE</id> - <description> Core HTM: defines capture mode according to trace mode. - HTM Collection Mode Register (4:9). - When htm_mode_q(1 TO 2) == 00, i.e. Core Instruction Trace - 00xxxx : tc_pc_trace_active asserted when HTM_STAT[Tracing]=1 to purge the ERAT when entering and exitting trace - 01xxxx : tc_pc_trace_active asserted when HTM_MODE[HTM_Trace_enable]=1 to purge the ERAT only at the beginning - When htm_mode_q(1 TO 2) == 01, i.e. LLAT Trace - 0xxxxx : capture on assertion of l2_htm_llat_disp_req, i.e. any dispatch request - 1xxxxx : capture on assertion of l2_htm_llat_disp_req AND l2_llat_htm_rcdisp_occurred, i.e. only on passed dispatch - x0xxxx : capture on assertion of l2_htm_llat_disp_req, i.e. loads or stores - x1xxxx : capture on assertion of l2_htm_llat_disp_req AND l2_llat_htm_rcdisp_ld_not_st, i.e. only loads - xx0xxx : capture on assertion of l2_llat_htm_pbl3hit_dval - xx1xxx : no capture on assertion of l2_llat_htm_pbl3hit_dval - enable embedded timestamp - When htm_mode_q(1 TO 2) == 11, i.e. Direct Memory Write - 1xxxxx : Enable HPMC-IMA Mode - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CHTM_HTMSC_MODE_CAPTURE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CHTM_HTMSC_MODE_CORE_INSTR_STALL</id> - <description> For CHTM only. - 0: Core execution is stalled whenever the data buffers are almost full to prevent losing records. - 1: Core execution is never stalled and entries may be discarded when buffer is full - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CHTM_HTMSC_MODE_CORE_INSTR_STALL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_MODE_WRAP</id> - <description> Trace Wrap mode, used for both NHTM and CHTM - HTM Collection Mode Register (13). - 0 = Wrap trace to beginning of Trace Memory - 1 = Stop trace when top of Trace Memory is reached - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_MODE_WRAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_MODE_DIS_TSTAMP</id> - <description> TimeStamp Writes option, used for both NHTM and CHTM - HTM Collection Mode Register (14). - 0 = Write of timestamps enabled to indicate elapsed time - between records. - 1 = Timestamps written only to indicate record loss - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_MODE_DIS_TSTAMP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_MODE_SINGLE_TSTAMP</id> - <description> Overflow Timestamps option, used for both NHTM and CHTM. - HTM Collection Mode Register (15). - 0 = Timestamp written to indicate elapsed time overflow. - 1 = Only one timestamp is written between entries, overflow - indication is lost - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_MODE_SINGLE_TSTAMP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_MODE_MARKERS_ONLY</id> - <description> Nest HTM: Stamp/Marker only mode. - HTM Collection Mode Register (17). - 0 = Normal trace - 1 = Ignore incoming trace data and save only markers caused - by HTM_TRIG writes, - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_MODE_MARKERS_ONLY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_MODE_DIS_FORCE_GROUP_SCOPE</id> - <description> Nest HTM: Group scope option. - HTM Collection Mode Register (18). - This is a powerbus debug bit - 0 = htm write ops sent with group scope - 1 = htm write ops sent with Vg scope using programmed - target bits. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_MODE_DIS_FORCE_GROUP_SCOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_MODE_VGTARGET</id> - <description> Nest HTM: VG target mode. - HTM Collection Mode Register (24:39). - Vg Target bits should be configured if HTM_MEM[scope] is Vg - or if Disable Group Scope=1 - </description> - <simpleType> - <uint32_t> - </uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_MODE_VGTARGET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_MEM_SCOPE</id> - <description> Setting of memory scope for HTM collection. - HTM Memory Configuration Register (1:3) - LOCAL = 0x0, NEARNODE = 0x1, GROUP = 0x3, REMOTE = 0x4, VECTORED = 0x5 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_MEM_SCOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_MEM_PRIORITY</id> - <description> Setting of memory priority for HTM collection. - HTM Memory Configuration Register (4) - LOW = 0x0, HIGH = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_MEM_PRIORITY</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NHTM_CTRL_TRIG</id> - <description> Setting of Trigger control for NHTM. - HTM Trigger Control Register (0:1) - 00 local triggers are not forwarded to the PowerBus, it is - inserted into the trace when tracing. Both local and - global triggers control the HTM - 01 local triggers are not forwarded to the PowerBus, it is - inserted into the traCe when tracing. Only local triggers - control the HTM - 1x local triggers are forwarded to the PowerBus, it is not - inserted into the trace when tracing. Only global - triggers control the HTM - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_NHTM_CTRL_TRIG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NHTM_CTRL_MARK</id> - <description> Setting of Mark control for NHTM. - HTM Trigger Control Register (4:5) - 00 local markers are not forwarded to the PowerBus. Both - local and global markers are inserted into the trace - 01 local markers are not forwarded to the PowerBus. Only - local markers are inserted into the trace - 10 local markers are forwarded to the PowerBus. Only global - markers are inserted into the trace - 11 local markers are forwarded to the PowerBus. Markers - are not inserted into the trace (Fabric Trace Mode) - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NHTM_CTRL_MARK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CHTM_CTRL_TRIG</id> - <description> Setting of Trigger control. - HTM Trigger Control Register (0:1) - 00 local triggers are not forwarded to the PowerBus, it is - inserted into the trace when tracing. Both local and - global triggers control the HTM - 01 local triggers are not forwarded to the PowerBus, it is - inserted into the traCe when tracing. Only local triggers - control the HTM - 1x local triggers are forwarded to the PowerBus, it is not - inserted into the trace when tracing. Only global - triggers control the HTM - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CHTM_CTRL_TRIG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CHTM_CTRL_MARK</id> - <description> Setting of Mark control. - HTM Trigger Control Register (4:5) - 00 local markers are not forwarded to the PowerBus. Both - local and global markers are inserted into the trace - 01 local markers are not forwarded to the PowerBus. Only - local markers are inserted into the trace - 10 local markers are forwarded to the PowerBus. Only global - markers are inserted into the trace - 11 local markers are forwarded to the PowerBus. Markers - are not inserted into the trace (Fabric Trace Mode) - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CHTM_CTRL_MARK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_CTRL_DBG0_STOP</id> - <description> Enable Stop on PB Chiplet Debug Trigger 0. - HTM Trigger Control Register (6) - DISABLE = 0x0, ENABLE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_CTRL_DBG0_STOP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_CTRL_DBG1_STOP</id> - <description> Enable Stop on PB Chiplet Debug Trigger 1. - HTM Trigger Control Register (7) - DISABLE = 0x0, ENABLE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_CTRL_DBG1_STOP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_CTRL_RUN_STOP</id> - <description> Enable trace stop on falling edge of PB chiplet trace run. - HTM Trigger Control Register (8) - DISABLE = 0x0, ENABLE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_CTRL_RUN_STOP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_CTRL_OTHER_DBG0_STOP</id> - <description> Enable Stop using OCC Control. - HTM Trigger Control Register (9) - DISABLE = 0x0, ENABLE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_CTRL_OTHER_DBG0_STOP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_CTRL_XSTOP_STOP</id> - <description> Enable Stop on chiplet XSTOP. - HTM Trigger Control Register (13) - ENABLE = 0x0, DISABLE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_CTRL_XSTOP_STOP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_CTRL_CHIP0_STOP</id> - <description> Stop on PC_TC_DBG_Trigger0 - 1 = stop trigger Core Debug Trigger 0 - 0 = ignore Core Debug Trigger 0 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_CTRL_CHIP0_STOP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_CTRL_CHIP1_STOP</id> - <description> Stop on PC_TC_DBG_Trigger1 - 1 = stop trigger Core Debug Trigger 1 - 0 = ignore Core Debug Trigger 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_CTRL_CHIP1_STOP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_IMA_PDBAR_SPLIT_CORE_MODE</id> - <description> This bit controls the indexing of the PDBAR address for the - starting address of the write to the PDBAR space. - For CHTM only. - 0 'Big Core' mode. - 1 'Split Core' mode. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_IMA_PDBAR_SPLIT_CORE_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_IMA_PDBAR_SCOPE</id> - <description> This register defines the starting Scope of the PowerBus - operation. The Scope will be increased if necessary however - it is more efficient to have the request issued according to - where the target memory is located. - 000 LOCAL scope - 001 Reserved - 010 NEAR NODE scope (Nn) - 011 GROUP scope (G). - 100 REMOTE scope (Rn). - 101 VECTORED group scope (Vg). - 110 Reserved - 111 Reserved - Note 1: Since P9 uses a Group Class MCD, the HTM will always - force a 'Nodal' scope to 'Group' scope. If the scope is - initialized to 'Vectored Group Scope', the HTM_MODE[Vg_Target] - bits must also be initialized. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_IMA_PDBAR_SCOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>HTMSC_IMA_PDBAR_ADDR</id> - <description> IMA Write Physical Base Address - </description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTMSC_IMA_PDBAR_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP</id> - <description> - Selects the number of enabled pullup branches during READ mode. - ONLY set range 0-7. Eg. 0x02 = b00000010 (1 branch selected), - 0x06 = b00000110 (2 branches selected) - </description> - <simpleType> - <uint32_t></uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN</id> - <description> - Selects the number of enabled pulldown branches during WRITE mode. - ONLY set range 0-7. Eg. 0x02 = b00000010 (1 branch selected), - 0x06 = b00000110 (2 branches selected) - </description> - <simpleType> - <uint32_t></uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP</id> - <description> - Selects the number of enabled pullup branches during WRITE mode. - ONLY set range 0-7. Eg. 0x02 = b00000010 (1 branch selected), - 0x06 = b00000110 (2 branches selected) - </description> - <simpleType> - <uint32_t></uint32_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_DQ_CTLE_CAP</id> - <description> - Sets the capacitance value in the RC source degeneration for - [PORT#][DP16 BLOCK#]. ONLY set range 0-3. (0x00 = No capacitor selected, - 0x01 = more caps selected, 0x02 = even more caps selected, - 0x03 = maximum capacitors selected) - </description> - <simpleType> - <uint64_t></uint64_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MT_MC_DQ_CTLE_RES</id> - <description> - Sets the resistance value in the RC source degeneration for - [PORT#][DP16 BLOCK#]. Also defines the CTLE's DC Gain. - ONLY set range 0-7. (0x00 = max resistance, 0x01 to 0x06 = decreasing resistance, - 0x07 = min resistance) - </description> - <simpleType> - <uint64_t></uint64_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CP_FILTER_BYPASS</id> - <description> - To skip the locking sequence and check for lock of CP PLL - Override attribute - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CP_FILTER_BYPASS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SS_FILTER_BYPASS</id> - <description> - To skip the locking sequence and check for lock of SS PLL - Override attribute - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SS_FILTER_BYPASS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IO_FILTER_BYPASS</id> - <description> - To skip the locking sequence and check for lock of IO PLL - Override attribute - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_IO_FILTER_BYPASS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DPLL_BYPASS</id> - <description> - Skip locking sequence and check for lock of DPLL - Override attribute - </description> + <id>PCIE_64BIT_DMA_SIZE</id> + <description>PCIe slot 64bit DMA size definition</description> <simpleType> <uint8_t> </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_DPLL_BYPASS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <no_export/> </attribute> <attribute> - <id>NEST_MEM_X_O_PCI_BYPASS</id> - <description> - Skip the locking sequence and check for lock of NEST/MEM/XBUS/OBUS/PCI PLLs - Override attribute - </description> + <id>HDDW_ORDER</id> + <description>PCIe slot HDDW order definition</description> <simpleType> <uint8_t> </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NEST_MEM_X_O_PCI_BYPASS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>LPC_BASE_ADDR</id> - <description> - Defines LPC base address on each processor level. - </description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_LPC_BASE_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FSP_BAR_ENABLE</id> - <description> - FSP BAR enable - DISABLE = 0x0, ENABLE = 0x1 - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FSP_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PSI_BRIDGE_BAR_ENABLE</id> - <description> - PSI Bridge BAR enable - DISABLE = 0x0, ENABLE = 0x1 - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PSI_BRIDGE_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_INT_CQ_PC_BAR_ENABLE</id> - <description> - INT CQ PC BAR enable - DISABLE = 0x0, ENABLE = 0x1 - creator: platform - consumer: p9_setup_bars - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_PC_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET</id> - <description> - INT CQ PC BAR base address offset - Attribute holds offset (relative to chip MMIO origin) - to program into chip address range field of BAR - (excludes system/memsel/group/chip fields) - creator: platform - consumer: p9_setup_bars - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET_MASK</id> - <description> - INT CQ PC BAR base address offset mask - Attribute holds offset mask (relative to chip MMIO origin) - to program into chip address range field of BAR mask - (excludes system/memsel/group/chip fields) - Value defines which bits of VC_BAR are used during address compares - creator: platform - consumer: p9_setup_bars - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> + <persistency>non-volatile</persistency> <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET_MASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <no_export/> </attribute> -<attribute> - <id>PROC_INT_CQ_VC_BAR_ENABLE</id> - <description> - INT CQ VC BAR enable - DISABLE = 0x0, ENABLE = 0x1 - creator: platform - consumer: p9_setup_bars - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_VC_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> <attribute> - <id>PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET</id> - <description> - INT CQ VC BAR base address offset - Attribute holds offset (relative to chip MMIO origin) - to program into chip address range field of BAR - (excludes system/memsel/group/chip fields) - creator: platform - consumer: p9_setup_bars - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET_MASK</id> - <description> - INT CQ VC BAR base address offset mask - Attribute holds offset mask (relative to chip MMIO origin) - to program into chip address range field of BAR mask - (excludes system/memsel/group/chip fields) - Value defines which bits of VC_BAR are used during address compares - creator: platform - consumer: p9_setup_bars - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET_MASK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_INT_CQ_TM1_BAR_ENABLE</id> - <description> - INT CQ TM1 BAR enable - DISABLE = 0x0, ENABLE = 0x1 - creator: platform - consumer: p9_setup_bars - </description> + <id>MGC_LOAD_SOURCE</id> + <description>defines MGC load source</description> <simpleType> <uint8_t></uint8_t> </simpleType> + <persistency>non-volatile</persistency> <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_TM1_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_INT_CQ_TM1_BAR_BASE_ADDR_OFFSET</id> - <description> - INT CQ TM1 BAR base address offset - Attribute holds offset (relative to chip MMIO origin) - to program into chip address range field of BAR - (excludes system/memsel/group/chip fields) - creator: platform - consumer: p9_setup_bars - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_TM1_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <no_export/> </attribute> <attribute> - <id>PROC_INT_CQ_TM1_BAR_PAGE_SIZE</id> - <description> - INT CQ TM1 BAR page size - 4K = 0x0, 64K = 0x1 - creator: platform - consumer: p9_setup_bars - </description> + <id>PCIE_CAPABILITES</id> + <description>Denotes the capabilites of this pcie slot</description> <simpleType> <uint8_t></uint8_t> </simpleType> + <persistency>non-volatile</persistency> <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_TM1_BAR_PAGE_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <no_export/> </attribute> <attribute> - <id>PROC_INT_CQ_IC_BAR_ENABLE</id> - <description> - INT CQ IC BAR enable - DISABLE = 0x0, ENABLE = 0x1 - creator: platform - consumer: p9_setup_bars - </description> + <id>VENDOR_ID</id> + <description>PCIe vendor ID definition</description> <simpleType> <uint8_t></uint8_t> </simpleType> + <persistency>non-volatile</persistency> <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_IC_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_INT_CQ_IC_BAR_BASE_ADDR_OFFSET</id> - <description> - INT CQ IC BAR base address offset - Attribute holds offset (relative to chip MMIO origin) - to program into chip address range field of BAR - (excludes system/memsel/group/chip fields) - creator: platform - consumer: p9_setup_bars - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_IC_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <no_export/> </attribute> <attribute> - <id>PROC_INT_CQ_IC_BAR_PAGE_SIZE</id> - <description> - INT CQ IC (Interrupt Controller) BAR page size - 4K = 0x0, 64K = 0x1 - creator: platform - consumer: p9_setup_bars - </description> + <id>MAX_POWER</id> + <description>Defines the maximum power consumption for a PCIe slot</description> <simpleType> <uint8_t></uint8_t> </simpleType> - <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_PROC_INT_CQ_IC_BAR_PAGE_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SYSTEM_VDM_DISABLE</id> - <description> - Disables the enablement of Voltage Droop Monitors (VDM) in the system. - - Producer: Override - - Consumers: - p9_pstate_parameter_block to clear flag for CME QuadManager Hcode - reaction - </description> - <simpleType> - <uint8_t> - <default>0x01</default> - </uint8_t> - </simpleType> - <readable/> - <writeable/> - <persistency>volatile</persistency> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_VDM_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>SYSTEM_VDM_DISABLE</id> - <description>Enumeration for Voltage Drop Monitor disable</description> - <enumerator> - <name>OFF</name> - <value>0x00</value> - </enumerator> - <enumerator> - <name>ON</name> - <value>0x01</value> - </enumerator> -</enumerationType> - - -<attribute> - <id>DPLL_VDM_RESPONSE</id> - <description> - Indicates the response of the DPLL frequency upon VDM events. This - control will only apply if ATTR_DPLL_VDM_JUMP_ENABLE is ON; - Hardware WOF = DROOP_PROTECT_OVERVOLT (slew to Fmax if margin exists) - - Producer: MRWB. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <readable/> <persistency>non-volatile</persistency> - <hwpfToHbAttrMap> - <id>ATTR_DPLL_VDM_RESPONSE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_DRAM_2N_MODE</id> - <description> - Allows user to manually turn on and off 2N Mode. - AUTO indicates to use Signal Integrity generated setting (from VPD). - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> <readable/> - <persistency>volatile-zeroed</persistency> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_DRAM_2N_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- p9_setup_bars - Begin --> - -<attribute> - <id>PROC_PCIE_MMIO_BAR0_BASE_ADDR_OFFSET</id> - <description> - PCIE MMIO0 BAR base address offset - Attribute holds offset (relative to chip MMIO origin) to program into - chip address range field of BAR -- RA bits 8:47 - (excludes system/memory select/group/chip fields) - Array index: PHB number (0:5) - </description> - <simpleType> - <uint64_t> - </uint64_t> - <array>6</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_MMIO_BAR0_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_MMIO_BAR1_BASE_ADDR_OFFSET</id> - <description> - PCIE MMIO1 BAR base address offset - Attribute holds offset (relative to chip MMIO origin) to program into - chip address range field of BAR -- RA bits 8:47 - (excludes system/memory select/group/chip fields) - Array index: PHB number (0:5) - </description> - <simpleType> - <uint64_t> - </uint64_t> - <array>6</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_MMIO_BAR1_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PCIE_REGISTER_BAR_BASE_ADDR_OFFSET</id> - <description> - PCIE PHB register space BAR base address offset - chip address range field of BAR -- RA bits 8:49 - (excludes system/memory select/group/chip fields) - Array index: PHB number (0:5) - </description> - <simpleType> - <uint64_t> - </uint64_t> - <array>6</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PCIE_REGISTER_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_XSCOM_BAR_BASE_ADDR_OFFSET</id> - <description> - XSCOM BAR base address offset - Defines 16GB range (size implied) mapped for XSCOM usage - Attribute holds offset (relative to chip MMIO origin) to program into - chip address range field of BAR -- RA bits 22:29 - (excludes system/memory select/group/chip fields) - </description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_LPC_BAR_BASE_ADDR_OFFSET</id> - <description> - LPC BAR base address offset - Defines 4GB range (size implied) mapped for LPC usage - Attribute holds offset (relative to chip MMIO origin) to program into - chip address range field of BAR -- RA bits 22:31 - (excludes system/memory select/group/chip fields) - </description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>PROC_FSP_BAR_SIZE</id> - <description> - FSP BAR size value - creator: platform - consumer: p9_setup_bars - firmware notes: none - </description> - <simpleType> - <uint64_t> - <default>0xFFFFFC00FFFFFFFF</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FSP_BAR_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FSP_BAR_BASE_ADDR_OFFSET</id> - <description> - FSP BAR - Defines range mapped for FSP MMIO - Attribute holds offset (relative to chip MMIO origin) to program into - chip address range field of BAR -- RA bits 22:43 - </description> - <simpleType> - <uint64_t> - <default>0x0000030100000000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FSP_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_FSP_MMIO_MASK_SIZE</id> - <description> - FSP MMIO mask size value AND mask applied to RA 32:35 when transmitting - address to FSP - NOTE: RA 8:31 are always replaced with zero - 4_GB = 0x00F0000000000000, - 2_GB = 0x0070000000000000, - 1_GB = 0x0030000000000000, - 512_MB = 0x0010000000000000, - 256_MB = 0x0000000000000000 - </description> - <simpleType> - <uint64_t> - <default>0x0010000000000000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_FSP_MMIO_MASK_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET</id> - <description> - PSI Bridge BAR base address offset - Defines 1MB range (size implied) mapped for PSI host-bridge - Attribute holds offset (relative to chip MMIO origin) to program into - chip address range field of BAR -- RA bits 22:43 - (excludes system/memory select/group/chip fields) - </description> - <simpleType> - <uint64_t> - <default>0x0000030203000000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_NPU_PHY0_BAR_ENABLE</id> - <description> - NPU PHY0 (stack0) BAR enable - DISABLE = 0x0, ENABLE = 0x1 - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NPU_PHY0_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET</id> - <description> - NPU PHY0 (stack0) BAR - Defines 2MB range (size implied) mapped to PHY0 registers - Attribute holds offset (relative to chip MMIO origin) to program into - chip address range field of BAR -- RA bits 22:42 - (excludes system/memory select/group/chip fields) - </description> - <simpleType> - <uint64_t> - <default>0x0000030201200000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_NPU_PHY1_BAR_ENABLE</id> - <description> - NPU PHY1 (stack1) BAR enable - DISABLE = 0x0, ENABLE = 0x1 - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NPU_PHY1_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET</id> - <description> - NPU PHY1 (stack1) BAR - Defines 2MB range (size implied) mapped to PHY1 registers - Attribute holds offset (relative to chip MMIO origin) to program into - chip address range field of BAR -- RA bits 22:42 - (excludes system/memory select/group/chip fields) - </description> - <simpleType> - <uint64_t> - <default>0x0000030201400000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_NPU_MMIO_BAR_ENABLE</id> - <description> - NPU MMIO (stack2) BAR enable - DISABLE = 0x0, ENABLE = 0x1 - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <no_export/> </attribute> <attribute> - <id>PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id> + <id>OBUS_BRICK_LANE_MASK</id> <description> - NPU MMIO (stack2) BAR - Defines 16MB range mapped to all NPU registers - Attribute holds offset (relative to chip MMIO origin) to program into - chip address range field of BAR -- RA bits 22:39 - (excludes system/memory select/group/chip fields) + Lane mask for which 8 lanes belong to this brick + This is a right justified 24-bit value. Only 8 of the + 24 bits will be set representing the lanes belonging to + the associated brick. + Provided by the MRW. </description> <simpleType> - <uint64_t> - <default>0x0000030200000000</default> - </uint64_t> + <uint32_t> + </uint32_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_NX_RNG_BAR_ENABLE</id> + <id>OBUS_SLOT_INDEX</id> <description> - NX RNG BAR enable - DISABLE = 0x0, ENABLE = 0x1 + Position of the obus slot that the Obus brick is connected to + (represented in decimal). There is only one slot that a given + brick connects to and there are only 6 slots per proc, + so, we just need a single uint8_t representing the position + of the slot. + Provided by the MRW. </description> <simpleType> <uint8_t> - <default>0</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NX_RNG_BAR_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_NX_RNG_BAR_BASE_ADDR_OFFSET</id> - <description> - NX RNG BAR - Defines 8KB range (size implied) mapped for NX RNG function - Attribute holds offset (relative to chip MMIO origin) to program into - chip address range field of BAR -- RA bits 22:51 - (excludes system/memory select/group/chip fields) - </description> - <simpleType> - <uint64_t> - <default>0x00000302031D0000</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<!-- p9_setup_bars - End --> - -<!--The following two NX_RING_FAILED attributes are essentially overrides - so we will init them to zero --> -<attribute> - <id>PROC_NX_RNG_FAILED_INT_ENABLE</id> - <description> - Enable optional post of interrupt when both NX RNG noise - sources have failed. - DISABLE = 0x0, ENABLE = 0x1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NX_RNG_FAILED_INT_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PROC_NX_RNG_FAILED_INT_ADDR</id> - <description> - Address used to post interrupt when both NX RNG noise sources have failed - creator: platform - consumer: p9_rng_init_phase2 - firmware notes: - 64-bit address representing RA - NOTE: register covers RA 8:51 - </description> - <simpleType> - <uint64_t> - </uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_NX_RNG_FAILED_INT_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_DPHY_GPO</id> - <description> - Global phy offset in number of clocks - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_DPHY_GPO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_DPHY_RLO</id> - <description> - Read latency offset in number of clocks - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_DPHY_RLO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VPD_MR_DPHY_WLO</id> - <description> - Write latency offset in number of clocks - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_MR_DPHY_WLO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> + <no_export/> </attribute> <attribute> - <id>L2_HASCLOCKS</id> + <id>MFG_TRACE_ENABLE</id> <description> - Indicates the L2 region has clocks running and scommable - + Override this to a non-zero value to have the FAPI manufacturing + traces output to the console or go to a fsp trace buffer when + console not enabled. </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> + <simpleType><uint8_t></uint8_t></simpleType> <persistency>volatile-zeroed</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L2_HASCLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> -<attribute> - <id>L3_HASCLOCKS</id> - <description> - Indicates the L3 region has clocks running and scommable - - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L3_HASCLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> <attribute> - <id>C0_EXEC_HASCLOCKS</id> + <id>MAX_SBE_SEEPROM_SIZE</id> <description> - Indicates the execution units in core 0 have clocks running - and scommable - + Defines the maximum Seeprom storage size for the fully-customized SBE image + permitted by the platform. + For platforms (FSP/HB FW) which require the image to be constrained into a + physical storage device (SEEPROM), this should reflect the maximum size of that + memory (e.g., 256KB). + For platforms (Cronus) which may use a customized image in a virtual + envrionment with no physical storage constraints, this size may be + larger than the physical SEEPROM size. </description> <simpleType> - <uint8_t></uint8_t> + <uint32_t> + <default>0x40000</default> + </uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> <hwpfToHbAttrMap> - <id>ATTR_C0_EXEC_HASCLOCKS</id> + <id>ATTR_MAX_SBE_SEEPROM_SIZE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> - <id>C1_EXEC_HASCLOCKS</id> - <description> - Indicates the execution units in core 1 have clocks running - and scommable + <id>STOP5_DISABLE</id> + <description> Control CME response to execution of PowerPC STOP instruction + if OFF, treat STOP5 as STOP5 + if ON, treat STOP5 as STOP4 - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_C1_EXEC_HASCLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> + Producer: ??? -<attribute> - <id>C0_PC_HASCLOCKS</id> - <description> - Indicates the core pervasive unit in core 0 has clocks - running and scommable + Consumer: p8_hcode_image_build.C + Platform default: OFF </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> <hwpfToHbAttrMap> - <id>ATTR_C0_PC_HASCLOCKS</id> + <id>ATTR_STOP5_DISABLE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>C1_PC_HASCLOCKS</id> - <description> - Indicates the core pervasive unit in core 1 has clocks - running and scommable - - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_C1_PC_HASCLOCKS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> +<!-- Required by FSP --> <attribute> - <id>L2_HASPOWER</id> + <id>FREQ_PROC_REFCLOCK</id> <description> - Indicates L2 has power and has valid latch state that could - be scanned - + System attribute. + The frequency of the processor refclock in MHz. + Provided by the MRW. </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> + <simpleType><uint32_t></uint32_t></simpleType> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L2_HASPOWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>L3_HASPOWER</id> + <id>X_EREPAIR_THRESHOLD_FIELD</id> <description> - Indicates L3 has power and has valid latch state that could - be scanned - + This attribute represents the eRepair threshold value of X-Bus used + in the field. + creator: platform (generated based on MRW data) + See defintion in erepair_thresholds.xml for more information. </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_L3_HASPOWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>C0_HASPOWER</id> + <id>A_EREPAIR_THRESHOLD_FIELD</id> <description> - Indicates core 0 has power and has valid latch state that - could be scanned - + This attribute represents the eRepair threshold value of A-Bus used + in the field. + creator: platform (generated based on MRW data) + See defintion in erepair_thresholds.xml for more information. </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_C0_HASPOWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>C1_HASPOWER</id> + <id>DMI_EREPAIR_THRESHOLD_FIELD</id> <description> - Indicates core 1 has power and has valid latch state that - could be scanned - + This attribute represents the eRepair threshold value of DMI-Bus used + in the field. + creator: platform (generated based on MRW data) + See defintion in erepair_thresholds.xml for more information. </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_C1_HASPOWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>TARGET_HAS_POWER</id> + <id>X_EREPAIR_THRESHOLD_MNFG</id> <description> - Functional Target has power + This attribute represents the eRepair threshold value of X-Bus used + by Manufacturing. + creator: platform (generated based on MRW data) + See defintion in erepair_thresholds.xml for more information. </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_TARGET_HAS_POWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>TARGET_HAS_CLOCK</id> + <id>A_EREPAIR_THRESHOLD_MNFG</id> <description> - Functional Target has clock + This attribute represents the eRepair threshold value of A-Bus used + by Manufacturing. + creator: platform (generated based on MRW data) + See defintion in erepair_thresholds.xml for more information. </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_TARGET_HAS_CLOCK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>TARGET_IS_SCOMMABLE</id> + <id>DMI_EREPAIR_THRESHOLD_MNFG</id> <description> - Functional Target is scommable + This attribute represents the eRepair threshold value of DMI-Bus used + by Manufacturing. + creator: platform (generated based on MRW data) + See defintion in erepair_thresholds.xml for more information. </description> <simpleType> - <uint8_t></uint8_t> + <uint8_t> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_TARGET_IS_SCOMMABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_R_LOADLINE_VDD_UOHM</id> - <description> - - Impedance (binary microOhms) of the load line from a processor VDD VRM to the - Processor Module pins. This value is applied to each processor instance. - - Producer: Machine Readable Workbook (per the power subsystem design) - - Consumers: p9_pstate_parameter_block - - </description> + <id>MSS_MBA_ADDR_INTERLEAVE_BIT</id> + <description>sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. valid values are 23 through 32.</description> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_R_LOADLINE_VDD_UOHM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_R_DISTLOSS_VDD_UOHM</id> - <description> - - Impedance (binary in microOhms) of the VDD distribution loss sense point - to the circuit. This value is applied to each processor instance. - - Producer: Machine Readable Workbook (per the power subsystem design) - - Consumers: p9_pstate_parameter_block - - </description> + <id>MSS_MBA_CACHELINE_INTERLEAVE_MODE</id> + <description>centaur interleave mode. 1 = 256-BIT, 0 = 128-BIT.</description> <simpleType> - <uint32_t></uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_R_DISTLOSS_VDD_UOHM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_VRM_VOFFSET_VDD_UV</id> + <id>PM_SPIVID_FREQUENCY</id> <description> + SYSTEM Attribute + SPI Clock Frequency (binary in MHz) - Offset voltage (binary in microvolts) to apply to the VDD VRM distribution - to the processor module. This value is applied to each processor instance. - - Note: no loadline may be present in the system; thus, a value of 0 is - legal. - - Producer: Machine Readable Workbook (per the power subsystem design) + Consumer: proc_pm_effective - Consumers: p9_pstate_parameter_block + Produces ATTR_PM_SPIVID_CLOCK_DIVIDER + Provided by the Machine Readable Workbook. </description> <simpleType> <uint32_t></uint32_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_VRM_VOFFSET_VDD_UV</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_R_LOADLINE_VDN_UOHM</id> + <id>PM_SAFE_FREQUENCY</id> <description> + Frequency (binary in KHz) indicating the frequency that the cores will be moved + to in the event of the loss of the OCC Heartbeat. This value needs to be the maximum + of the DpoMin frequency for proper PowerBus operation and the PowerSave value for + the present part. - Impedance (binary microOhms) of the load line from a processor VDN VRM to - the Processor Module pins. This value is applied to each processor - instance. + Provided by the Machine Readable Workbook after system characterization. - Note: no loadline may be present in the system; thus, a value of 0 is - legal. + The value is translated to the Pstate space. - Producer: Machine Readable Workbook (per the power subsystem design) + Producer: Machine Readable Workbook - Consumers: p9_pstate_parameter_block + Consumers: p8_build_gpstate_table.C + DYNAMIC_ATTRIBUTE: ATTR_PM_SAFE_PSTATE </description> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_R_LOADLINE_VDN_UOHM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_R_DISTLOSS_VDN_UOHM</id> + <id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> <description> + SYSTEM Attribute + Frequency (binary in MHz) for the point at which clock sector buffers + should be at full strength. This is to support Vmin operation. + Setting cannot overlap the Low or High bands. - Impedance (binary in microOhms) of the VDN distribution loss sense point - to the circuit. This value is applied to each processor instance. - - Producer: Machine Readable Workbook (per the power subsystem design) - - Consumers: p9_pstate_parameter_block - + Provided by the Machine Readable Workbook after system characterization. </description> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> <persistency>non-volatile</persistency> <readable/> <hwpfToHbAttrMap> - <id>ATTR_PROC_R_DISTLOSS_VDN_UOHM</id> + <id>ATTR_PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_VRM_VOFFSET_VDN_UV</id> + <id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id> <description> + SYSTEM Attribute + Frequency (binary in MHz)) for the lower end of the Low Frequency + Resonant band - Offset voltage (binary in microvolts) to apply to the VDN VRM distribution - to the processor module. This value is applied to each processor instance. - - Producer: Machine Readable Workbook (per the power subsystem design) - - Consumers: p9_pstate_parameter_block - + Provided by the Machine Readable Workbook after system characterization. </description> <simpleType> - <uint32_t> - </uint32_t> + <uint32_t></uint32_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_VRM_VOFFSET_VDN_UV</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_R_LOADLINE_VCS_UOHM</id> + <id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id> <description> + SYSTEM Attribute + Frequency (binary in MHz) for the upper end of the Low Frequency + Resonant band - Impedance (binary microOhms) of the load line from a processor VCS VRM to - the Processor Module pins. This value is applied to each processor - instance. - - Note: no loadline may be present in the system; thus, a value of 0 is - legal. - - Producer: Machine Readable Workbook (per the power subsystem design) - - Consumers: p9_pstate_parameter_block - + Provided by the Machine Readable Workbook after system characterization. </description> <simpleType> <uint32_t></uint32_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_R_LOADLINE_VCS_UOHM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_R_DISTLOSS_VCS_UOHM</id> + <id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id> <description> + SYSTEM Attribute + Frequency (binary in MHz) for the lower end of the High Frequency + Resonant band - Impedance (binary in microOhms) of the VCS distribution loss sense point - to the circuit. This value is applied to each processor instance. - - Producer: Machine Readable Workbook (via the power subsystem design per - system) - - Consumer: p9_pstate_parameter_block - + Provided by the Machine Readable Workbook after system characterization. </description> <simpleType> <uint32_t></uint32_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_R_DISTLOSS_VCS_UOHM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PROC_VRM_VOFFSET_VCS_UV</id> + <id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id> <description> + SYSTEM Attribute + Frequency (binary in MHz)) for the upper end of the High Frequency + Resonant band - Offset voltage (binary in microvolts) to apply to the VCS VRM distribution - to the processor module. This value is applied to each processor instance. - - Producer: Machine Readable Workbook (via the power subsystem design per - system) - - Consumer: FSP - + Provided by the Machine Readable Workbook after system characterization. </description> <simpleType> <uint32_t></uint32_t> </simpleType> <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PROC_VRM_VOFFSET_VCS_UV</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> - <attribute> - <id>FREQ_BIAS_ULTRATURBO</id> - <description> - - UltraTurbo Frequency Bias - % of bias (signed twos complement in 0.5 - percent steps) used in calculating the frequency associated with a Pstate - - both Global and Local. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_BIAS_ULTRATURBO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FREQ_BIAS_TURBO</id> - <description> - - Turbo Frequency Bias - % of bias (signed twos complement in 0.5 percent - steps) used in calculating the frequency associated with a Pstate - both - Global and Local. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_BIAS_TURBO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FREQ_BIAS_NOMINAL</id> - <description> - - Nominal Frequency Bias - % of bias (signed twos complement in 0.5 percent - steps) used in calculating the frequency associated with a Pstate - both - Global and Local. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_BIAS_NOMINAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>FREQ_BIAS_POWERSAVE</id> - <description> - - PowerSave Frequency Bias - % of bias (signed twos complement in 0.5 percent - steps) used in calculating the frequency associated with a Pstate - both - Global and Local. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_FREQ_BIAS_POWERSAVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VOLTAGE_EXT_VDD_BIAS_ULTRATURBO</id> - <description> - - UltraTurbo VDD Voltage Bias - % of bias (signed twos complement in 0.5 - percent steps) that is applied to the UltraTurbo VPD point used in - calculating the Global Pstate values. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_EXT_VDD_BIAS_ULTRATURBO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VOLTAGE_EXT_VDD_BIAS_TURBO</id> - <description> - - Turbo VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent - steps) that is applied to the UltraTurbo VPD point used in calculating the - Global Pstate values. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_EXT_VDD_BIAS_TURBO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VOLTAGE_EXT_VDD_BIAS_NOMINAL</id> - <description> - - Nominal VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent - steps) that is applied to the UltraTurbo VPD point used in calculating the - Global Pstate values. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_EXT_VDD_BIAS_NOMINAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VOLTAGE_EXT_VDD_BIAS_POWERSAVE</id> - <description> - - PowerSave VDD Voltage Bias - % of bias (signed twos complement in 0.5 - percent steps) that is applied to the UltraTurbo VPD point used in - calculating the Global Pstate values. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_EXT_VDD_BIAS_POWERSAVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VOLTAGE_EXT_VCS_BIAS</id> - <description> - - VCS Voltage Bias - % of bias (signed twos complement in 0.5 percent - steps) that is applied to the VCS value stored in the UltraTurbo VPD - point for setting the VCS rail. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - Platform default: 0 - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_EXT_VCS_BIAS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VOLTAGE_EXT_VDN_BIAS</id> - <description> - - VDN Voltage Bias - % of bias (signed twos complement in 0.5 percent - steps) that is applied to the VDN value stored in the VPD for setting the - VDN rail. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - Platform default: 0 - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_EXT_VDN_BIAS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VOLTAGE_INT_VDD_BIAS_ULTRATURBO</id> - <description> - - TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS - WELL AS THE IVRM VOLTAGE CALCULATION PROCESS - UltraTurbo Internal VDD Voltage Bias - % of bias (signed twos complement in - 0.5 percent steps) that is applied to the voltage computed (Vout) as part - of the Local Pstate. Note: the Vin Effective that models the Vin to the - PFETs (i.e accounting for system parameter losses) may include biassing - based on ATTR_VOLTAGE_VDD_BIAS_ULTRATURBO. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - Platform default: 0 - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_INT_VDD_BIAS_ULTRATURBO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VOLTAGE_INT_VDD_BIAS_TURBO</id> - <description> - - TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS - WELL AS THE IVRM VOLTAGE CALCULATION PROCESS - TURBO Internal VDD Voltage Bias - % of bias (signed twos complement in 0.5 - percent steps) that is applied to the voltage computed (Vout) as part of - the Local Pstate. Note: the Vin Effective that models the Vin to the PFETs - (i.e accounting for system parameter losses) may include biassing based on - ATTR_VOLTAGE_VDD_BIAS_TURBO. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - Platform default: 0 - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_INT_VDD_BIAS_TURBO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VOLTAGE_INT_VDD_BIAS_NOMINAL</id> - <description> - - TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS - WELL AS THE IVRM VOLTAGE CALCULATION PROCESS - Nominal Internal VDD Voltage Bias - % of bias (signed twos complement in - 0.5 percent steps) that is applied to the voltage computed (Vout) as part - of the Local Pstate. Note: the Vin Effective that models the Vin to the - PFETs (i.e accounting for system parameter losses) may include biassing - based on ATTR_VOLTAGE_VDD_BIAS_NOMINAL. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - Platform default: 0 - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_INT_VDD_BIAS_NOMINAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VOLTAGE_INT_VDD_BIAS_POWERSAVE</id> - <description> - - TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS - WELL AS THE IVRM VOLTAGE CALCULATION PROCESS - PowerSave Internal VDD Voltage Bias - % of bias (signed twos complement in - 0.5 percent steps) that is applied to the voltage computed (Vout) as part of - the Local Pstate. Note: the Vin Effective that models the Vin to the PFETs - (i.e accounting for system parameter losses) may include biassing based on - ATTR_VOLTAGE_VDD_BIAS_POWERSAVE. - - Producer: Attribute Overrides by Lab/Mfg Characterization Team - - Consumer: p9_pstate_parameter_block - - Platform default: 0 - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VOLTAGE_INT_VDD_BIAS_POWERSAVE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VDM_DROOP_SMALL_OVERRIDE</id> - <description> - - Voltage Droop Monitor (VDM) Small Threshold Select Value per VPD point - The enum indicates a negative value below the VDM setting that will - trigger a small droop event. - - Array of 5 entries: - 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable - - If index 4 is non-zero, the other entries are considered valid. - - Producer: MRWB. - - </description> + <id>MRW_MEM_THROTTLE_DENOMINATOR</id> + <description>Machine Readable Workbook throttle value for denominator cfg_nm_m</description> <simpleType> - <uint8_t></uint8_t> - <array>5</array> + <uint32_t></uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_DROOP_SMALL_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>VDM_DROOP_LARGE_OVERRIDE</id> - <description> - - Voltage Droop Monitor (VDM) Large Threshold Select Value per VPD point - The enum indicates a negative value below the VDM setting that will - trigger a large droop event. - - Array of 5 entries: - 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable - - If index 4 is non-zero, the other entries are considered valid. - - Producer: Firmware override - + <id>PM_SYSTEM_IVRM_VPD_MIN_LEVEL</id> + <description>Version level of #M that represents the minimum for IVRM characterized parts. + If this value is non-zero and the #M version level is less than this value, IVRMs are disabled. + If the #M version is greater than or equal to this value, the IVRMs are allowed to be enable from a level of part perspective. + Producer: MRWB + Consumer: p8_build_pstate_datablock.C </description> <simpleType> <uint8_t></uint8_t> - <array>5</array> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_DROOP_LARGE_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>VDM_DROOP_EXTREME_OVERRIDE</id> + <id>MNFG_DMI_MIN_EYE_WIDTH</id> <description> - - Voltage Droop Monitor (VDM) Extreme Threshold Select Value per VPD point. - The enum indicates a negative value below the VDM setting that will - trigger an extreme droop event. - - Array of 5 entries: - 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable - - If index 4 is non-zero, the other entries are considered valid. - - Producer: MRWB. - + System attribute. + 6 bit rx_min_eye_width value for DMI bus interfaces during system + manufacturing; used for both centaur and p8 + creator: platform + firmware notes: Attribute value is in the Machine Readable Workbook </description> <simpleType> - <uint8_t></uint8_t> - <array>5</array> + <uint8_t> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_DROOP_EXTREME_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>VDM_OVERVOLT_OVERRIDE</id> + <id>MNFG_DMI_MIN_EYE_HEIGHT</id> <description> - - Voltage Droop Monitor (VDM) OverVoltage Threshold Select Value per VPD - point. The enum indicates a positive value above the VDM setting that will - indicate an overvolt droop condition. - - Array of 5 entries: - 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable - - If index 4 is non-zero, the other entries are considered valid. - - Producer: MRWB. - + System attribute. + 8 bit rx_min_eye_height value for DMI bus interfaces during system + manufacturing; used for both centaur and p8 + creator: platform + firmware notes: Attribute value is in the Machine Readable Workbook </description> <simpleType> - <uint8_t></uint8_t> - <array>5</array> + <uint8_t> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_OVERVOLT_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>VDM_SMALL_FREQ_DROP_N_S_OVERRIDE</id> + <id>MNFG_ABUS_MIN_EYE_WIDTH</id> <description> - DPLL response override of the respective #W VPD content for a Voltage Droop - Monitor (VDM) Small Frequency Drop (eg Normal to Small). Values are in - 1/32ths with legal values being of N being less than or equal to 8. - Array of 5 entries: - 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable - If index 4 is non-zero, the other entries are considered valid. - Producer: Override + System attribute + 6 bit rx_min_eye_width value for A bus interfaces during system + manufacturing + creator: platform + firmware notes: Attribute value is in the Machine Readable Workbook </description> <simpleType> - <uint8_t></uint8_t> - <array>5</array> + <uint8_t> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_SMALL_FREQ_DROP_N_S_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>VDM_LARGE_FREQ_DROP_N_L_OVERRIDE</id> + <id>MNFG_ABUS_MIN_EYE_HEIGHT</id> <description> - DPLL response override of the respective #W VPD content for a Voltage Droop - Monitor (VDM) Large Frequency Drop (eg Normal to Large). Values are in - 1/32ths with legal values being of N being less than or equal to 8. - Array of 5 entries: - 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable - If index 4 is non-zero, the other entries are considered valid. - Producer: Override + System attribute + 8 bit rx_min_eye_height value for A bus interfaces during system + manufacturing + creator: platform + firmware notes: Attribute value is in the Machine Readable Workbook </description> <simpleType> - <uint8_t></uint8_t> - <array>5</array> + <uint8_t> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_LARGE_FREQ_DROP_N_L_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>VDM_FREQ_RETURN_L_S_OVERRIDE</id> + <id>MNFG_XBUS_MIN_EYE_WIDTH</id> <description> - DPLL response override of the respective #W VPD content for returning - from a Large Frequency Droop value to the Small value. Values are in - 1/32ths with legal values being of N being less than or equal to 8. - Array of 5 entries: - 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable - If index 4 is non-zero, the other entries are considered valid. - Producer: Override + System attribute + 6 bit rx_min_eye_width value for X bus interfaces during system + manufacturing + creator: platform + firmware notes: Attribute value is in the Machine Readable Workbook </description> <simpleType> - <uint8_t></uint8_t> - <array>5</array> + <uint8_t> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_FREQ_RETURN_L_S_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>VDM_FREQ_RETURN_S_N_OVERRIDE</id> + <id>BRAZOS_RX_FIFO_OVERRIDE</id> <description> - DPLL response override of the respective #W VPD content for returning - from a Small Frequency Droop value to the Normal value. Values are in - 1/32ths with legal values being of N being less than or equal to 8. - Array of 5 entries: - 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable - If index 4 is non-zero, the other entries are considered valid. - Producer: Override + Defines where to apply Brazos rx_fifo_final_l2u_dly override settings for SW299500. </description> <simpleType> - <uint8_t></uint8_t> - <array>5</array> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_FREQ_RETURN_S_N_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>VDM_EXTREME_THOTTLE_ENABLE</id> - <description> - Controls the enablement of Voltage Droop Monitors (VDM) to throttle - the core upon an extreme droop event. - OFF = 0x00, ON = 0x01 - Producer: Machine Readable Workbook - Consumers: - p9_hcode_image_build to set flag for CME QuadManager Hcode reaction - </description> + <id>MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id> + <description>At a system level, this attribute controls if interleaving is required, requested or never. The MRW.</description> <simpleType> <uint8_t></uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_EXTREME_THOTTLE_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VDM_FMAX_OVERRIDE_KHZ</id> - <description> - Producer: MRWB. - </description> - <simpleType> - <uint16_t></uint16_t> - <array>5</array> - </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_FMAX_OVERRIDE_KHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>VDM_FMIN_OVERRIDE_KHZ</id> + <id>PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3</id> + <!-- TARGET_TYPE_PEC --> <description> - Producer: MRWB. + PCS rx vga control register3 + creator: platform + consumer: p9_pcie_scominit + firmware notes: + The value of rx vga control register3. + Array index: Configuration number + index 0~3 for CONFIG0~3 </description> <simpleType> <uint16_t></uint16_t> - <array>5</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_FMIN_OVERRIDE_KHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VDM_VID_COMPARE_OVERRIDE_MV</id> - <description> - - Voltage Droop Monitor (VDM) Voltage Compare Voltage to expect when no - droop is present (binary in mV) - - Array of 5 entries: - 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable - - If index 4 is non-zero, the other entries are considered valid. - - Producer: MRWB. - - </description> - <simpleType> - <uint8_t></uint8_t> - <array>5</array> + <array>4</array> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_VID_COMPARE_OVERRIDE_MV</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>IVRM_DEADZONE_MV</id> + <id>PROC_REFCLOCK_RCVR_TERM</id> <description> - - Indicates the size of the deadzone where the iVRM cannot regulate - (binary in millivolts) - - Producer: MRWB. - + Defines system specific value of processor refclock receiver termination (FSI GP4 bits 8:9) </description> <simpleType> <uint8_t> + <default>0</default> </uint8_t> </simpleType> <persistency>non-volatile</persistency> + <hasStringConversion/> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IVRM_DEADZONE_MV</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>TDP_RDP_CURRENT_FACTOR</id> + <id>PCI_REFCLOCK_RCVR_TERM</id> <description> - TODO RTC 157943 -- Placeholder description - Consumers: p9_pstate_parameter_block - + Defines system specific value of PCI refclock receiver termination (FSI GP4 bits 10:11) </description> <simpleType> - <uint32_t> - </uint32_t> + <uint8_t> + <default>0</default> + </uint8_t> </simpleType> <persistency>non-volatile</persistency> + <hasStringConversion/> <readable/> - <hwpfToHbAttrMap> - <id>ATTR_TDP_RDP_CURRENT_FACTOR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> -<attribute> - <id>SYSTEM_RESCLK_FREQ_REGIONS</id> - <description> - - Frequency discontinuity region points that defines the lower edge of a - Resonant Region and where F[i] LT F[i+1] and 0 LE i LE 7. - This yields: - ATTR_RESCLK_FREQ_REGIONS[0] LE Region 0 LT ATTR_RESCLK_FREQ_REGIONS[1] - ATTR_RESCLK_FREQ_REGIONS[1] LE Region 1 LT ATTR_RESCLK_FREQ_REGIONS[2] - ATTR_RESCLK_FREQ_REGIONS[2] LE Region 2 LT ATTR_RESCLK_FREQ_REGIONS[3] - etc. - - Consumers: p9_pstate_parameter_block - - </description> - <simpleType> - <uint16_t></uint16_t> - <array>8</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_RESCLK_FREQ_REGIONS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> +<!-- End Required by FSP --> <attribute> - <id>SYSTEM_RESCLK_FREQ_REGION_INDEX</id> + <id>MAX_DMI_PER_PROC</id> <description> - - Defines the index into ATTR_RESCLK_VALUE[] to use for the frequency region. - - The frequency associated with the region is defined by - ATTR_RESCLK_FREQ_REGIONS[i] and ATTR_RESCLK_FREQ_REGIONS[i+1] for - 0 LE i LE 7. - - Consumers: p9_pstate_parameter_block - + System attribute. + The max DMI units per proc available in the system. </description> <simpleType> - <uint8_t></uint8_t> - <array>8</array> + <uint8_t> + <default>8</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_RESCLK_FREQ_REGION_INDEX</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>SYSTEM_RESCLK_VALUE</id> + <id>PREVIOUS_SBE_ERROR</id> <description> - - Array of Clock strength values that will we written in QACCR by CME Hcode - - Consumers: p9_pstate_parameter_block - + Keeps track of the previous SBE error. We need to know + what last occurred to know what action we need to take. </description> <simpleType> - <uint16_t></uint16_t> - <array>64</array> + <uint8_t><default>0</default></uint8_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_RESCLK_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>SYSTEM_RESCLK_L3_VALUE</id> + <id>MC_PLL_BUCKET</id> <description> - - Array of L3 Clock strength values to be used going between "High and Normal - Voltage" and "Low Voltage" mode. Low Voltage mode is define by - ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV. - - Entry 0 = "High and Normal Voltage" setting - Entry 3 = "High and Normal Voltage" setting - - Entry 1 = transitional setting defined by the clock team - Entry 2 = transitional setting defined by the clock team - - Contents of each entry will be written directly into L3 control bits in the - QACCR(16:23) a RMW operations. If the circuits demand a grey code whereby - only 1 bit of this field can change at a time, the entries must be deal with - such encoding. The Hcode that these values does not perform that function; - it merely steps from 0->3 when going below the voltage defined by - ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV and then steps 3->0 when going at or - above the voltage defined by ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV. - - Consumers: p9_pstate_parameter_block - + MC pll bucket selection in async mode for Cumulus </description> <simpleType> <uint8_t></uint8_t> - <array>4</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_RESCLK_L3_VALUE</id> + <id>ATTR_MC_PLL_BUCKET</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> - <id>SYSTEM_RESCLK_L3_VOLTAGE_THRESHOLD_MV</id> + <id>PM_SPWUP_FSP</id> <description> - - Voltage value (in millivolts) whereby voltage below this value will have - the L3 clock strength moved to "Low" mode while values at or above this - value will have the L3 clock strength moved to "High" mode. The L3 clock - strength values put in the hardware for this mode transtion are defined by - ATTR_RESCLK_L3_VALUE. - - Consumers: p9_pstate_parameter_block - + EX_CHIPLET Attribute </description> <simpleType> - <uint16_t></uint16_t> + <uint32_t></uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_RESCLK_L3_VOLTAGE_THRESHOLD_MV</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>PM_SAFE_FREQUENCY_MHZ</id> - <description> - - Frequency (in MHz) to move to if the Power Management function fails. - This is the same for all cores in the system. - Provided by the MRW. - - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SAFE_FREQUENCY_MHZ</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_OCC_THROTTLED_N_CMDS</id> + <id>PM_SPWUP_OCC</id> <description> - - cfg_nm_n_per_port throttle N value that was calculated from MSS_DATABUS_UTIL - + EX_CHIPLET Attribute </description> <simpleType> <uint32_t></uint32_t> - <array>2</array> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_OCC_THROTTLED_N_CMDS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>MSS_MRW_OFFSET_WLO</id> - <description> - - Write Latency Offset in number of Clocks - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_OFFSET_WLO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_OFFSET_GPO</id> - <description> - - Global Offset in number of Clocks. Delta from the value calculated or taken from VPD. - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_OFFSET_GPO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_OFFSET_RLO</id> - <description> - - Read Latency Offset in number of Clocks. Delta from the value calculated or taken from VPD. - - </description> - <simpleType> - <int8_t></int8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_OFFSET_RLO</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_TSYS_ADR</id> - <description> - - Phase rotator value for the memory sub-system clock in ticks. - Ticks are 1/128 of one cycle of clock. - - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_TSYS_ADR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_TSYS_DATA</id> - <description> - - Phase rotator value for the memory sub-system data in ticks. - Ticks are 1/128 of one cycle of clock. - - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_TSYS_DATA</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_TOTAL_PWR_SLOPE</id> + <id>PM_SPWUP_PHYP</id> <description> - - VDDR+VPP Power slope value for dimm - creator: mss_eff_config - consumer: mss_bulk_pwr_throttles - + EX_CHIPLET Attribute </description> <simpleType> - <uint16_t></uint16_t> - <array>2,2</array> + <uint32_t></uint32_t> </simpleType> <persistency>volatile-zeroed</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_TOTAL_PWR_SLOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>MSS_TOTAL_PWR_INTERCEPT</id> - <description> - - VDDR+VPP Power intercept value for dimm - creator: mss_eff_config - consumer: mss_bulk_pwr_throttles - - </description> +<id>PIB_I2C_REFCLOCK</id> +<description> + i2c reference clock for the system. + default is 0x4 => I2C speed = ~1Mhz per Andreas Koenig +</description> <simpleType> - <uint16_t></uint16_t> - <array>2,2</array> + <uint32_t> + <default>0x4</default> + </uint32_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>volatile</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_TOTAL_PWR_INTERCEPT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>MSS_PORT_MAXPOWER</id> + <id>ALL_MCS_IN_INTERLEAVING_GROUP</id> <description> - Channel Pair Max Power output from thermal procedures + System attribute. + If all MCS chiplets are in an interleaving group (1=true, 0=false). + - If true the SMP fabric is setup in normal mode and multiple MCSs + are grouped (disallowing systems with memory only under 1 MCS + (i.e. systems with a single C-DIMM)) + - If false the SMP fabric is setup in checkerboard mode. + Provided by the Machine Readable Workbook. + This attribute is based on Machine-Type-Model (MTM) and is setup by + the service processor. </description> <simpleType> - <uint32_t></uint32_t> - <array>2</array> + <uint8_t> + <default>0x00</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_PORT_MAXPOWER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>MSS_VPD_CKE_MAP</id> + <id>PROC_SELECT_SEEPROM_IMAGE</id> <description> - The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable signal to its respective rank. - There are 8 bits, but only 4 are currently used - [DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A] - E.g. 0x80 -> 0b10000000, which means DIMM0 CKE0 is mapped to that rank. + Specifies which SEEPROM image should be used for the boot master. + FIRST - the first image was selected + SECOND - the second image was selected + Platforms are expected to set this to FIRST in normal operation </description> <simpleType> - <uint8_t> - </uint8_t> - <array>2,2,4</array> + <uint8_t> + <default>1</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>volatile</persistency> <readable/> <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_CKE_MAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> </attribute> <attribute> - <id>MSS_VPD_DQ_MAP</id> + <id>PROC_SELECT_BOOT_SEEPROM_IMAGE</id> <description> - [PORT][Dimm DQ PIN] The map from the Dual - Inline Memory Module (DIMM) Data (DQ) Pin to - the Module Package Data (DQ) Pinout + Specifies which SEEPROM image should be used to boot a processor + FIRST - the first image was selected + SECOND - the second image was selected </description> <simpleType> - <uint8_t> - </uint8_t> - <array>2,72</array> + <uint8_t> + <default>1</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>volatile</persistency> <readable/> <writeable/> <hwpfToHbAttrMap> - <id>ATTR_MSS_VPD_DQ_MAP</id> + <id>ATTR_PROC_SELECT_BOOT_SEEPROM_IMAGE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> - <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4</id> + <id>OB0_PLL_BUCKET</id> <description> - Machine Readable Workbook VMEM regulator power limit per DIMM assuming a full configuration. Units in cW - Consumed in mss_eff_config_thermal + Select OBUS0 pll setting from one of the supported frequencies </description> <simpleType> - <uint32_t> - <default>0x000006A4</default> - </uint32_t> + <uint8_t><default>1</default></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> + <writeable/><!-- Only because SBE needs it --> <hwpfToHbAttrMap> - <id>ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4</id> - <macro>DIRECT</macro> + <id>ATTR_OB0_PLL_BUCKET</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> - <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR3</id> + <id>OB1_PLL_BUCKET</id> <description> - Machine Readable Workbook VMEM regulator power limit per CDIMM assuming a full configuration. Units in cW - Used for Cumulus - Consumed in mss_eff_config_thermal + Select OBUS1 pll setting from one of the supported frequencies </description> <simpleType> - <uint32_t> - </uint32_t> + <uint8_t><default>1</default></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> + <writeable/><!-- Only because SBE needs it --> <hwpfToHbAttrMap> - <id>ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR3</id> - <macro>DIRECT</macro> + <id>ATTR_OB1_PLL_BUCKET</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> - <id>MSS_IGNORE_PLUG_RULES</id> + <id>OB2_PLL_BUCKET</id> <description> - Set to IGNORE if you want to ignore the plug rules. Sometimes - this is needed in a partial-good configuration + Select OBUS2 pll setting from one of the supported frequencies </description> <simpleType> - <uint8_t> - </uint8_t> + <uint8_t><default>1</default></uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> + <persistency>non-volatile</persistency> <readable/> - <writeable/> + <writeable/><!-- Only because SBE needs it --> <hwpfToHbAttrMap> - <id>ATTR_MSS_IGNORE_PLUG_RULES</id> - <macro>DIRECT</macro> + <id>ATTR_OB2_PLL_BUCKET</id> + <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> <attribute> - <id>SYSTEM_FAMILY</id> - <description> - This field is of the form "vendor,name" where the name indicates - the family of the systems. The textual portion of the string has - a maximum length of 63 characters to accommodate a terminating NULL. - Both vendor and name fields are lower case US ASCII. No special - characters other than ",", "-", and "+" as described below should - be used in the string. - </description> - <simpleType> - <string> - <default>ibm,p9</default> - <sizeInclNull>64</sizeInclNull> - </string> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>SYSTEM_TYPE</id> - <description> - This field is of the form ?vendor,type? where the type indicates - a type of system within the System Family. The textual portion of - the string has a maximum length of 63 characters to accommodate a - terminating NULL. Both vendor and name fields are lower case US - ASCII. No special characters other than ",", "-", and "+" as described - below should be used in the string. If identification of specific - models within a system type is desired, "-model" should be appended - to the end of the name. The "-model" portion is optional and could be - used to identify the packaging, specific model numbers, etc. - NOTE: No Hostboot code should ever key off of this value. - </description> - <simpleType> - <string> - <default>ibm,miscopenpower</default> - <sizeInclNull>64</sizeInclNull> - </string> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>TOD_CPU_DATA</id> - <description>TOD CHIP DATA for each CHIP - The size of the TOD CHIP DATA must be equal to the sizeof(TodChipData) - </description> - <simpleType> - <uint8_t> - </uint8_t> - <!-- the size of the array must be equal to the sizeof(TodChipData) - defined in TodTypes.H --> - <array>44</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>SUPPORTED_STOP_STATES</id> + <id>OB3_PLL_BUCKET</id> <description> - STOP levels supported at runtime (sent to Host via HDAT): - Bit 0: STOP0 Supported - Quiesce thread only - Bit 1: STOP1 Supported - P8 Nap - Bit 2: STOP2 Supported - P8 Fast Sleep - Bit 3: STOP3 Supported - P8 Fast Sleep using iVRMs - Bit 4: STOP4 supported - P8 Deep Sleep - Bit 5: STOP5 Supported - WOF-friendly "Instant on" - Bit 6,7: Reserved - Bit 8: STOP8 supported - Half Quad Sleep - Bit 9: STOP9 supported - P8 Fast Winkle - Bit 10: Reserved - Bit 11: STOP11 supported - P8 Deep Winkle - Bit 12-15 : Reserved - Bits 16..31 - Reserved + Select OBUS3 pll setting from one of the supported frequencies </description> <simpleType> - <uint32_t> - <default>0xEC900000</default> - </uint32_t> + <uint8_t><default>1</default></uint8_t> </simpleType> <persistency>non-volatile</persistency> <readable/> + <writeable/><!-- Only because SBE needs it --> + <hwpfToHbAttrMap> + <id>ATTR_OB3_PLL_BUCKET</id> + <macro>DIRECT</macro> + </hwpfToHbAttrMap> </attribute> <attribute> - <id>SBE_IMAGE_MINIMUM_VALID_ECS</id> - <description> - The minimum number of valid ECs that is required to be used when - customizing an SBE image. The customization will fail if it cannot - create an image with at least this many ECs. - </description> - <simpleType> - <uint8_t> - <default>2</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_IMAGE_MINIMUM_VALID_ECS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>REL_POS</id> - <description> - Logical position of this unit/dimm relative to its immediate parent - </description> - <simpleType> - <uint8_t> - <default>0xFF</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_REL_POS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <no_export/> -</attribute> - -<attribute> - <id>PROC_PCIE_LANE_EQUALIZATION_GEN3</id> - <description>PCIE Lane Equalization values for each PHB - Creator: MRW - Purpose: Holds settings which are loaded into the HW to optimize the - PCIE lane signal eye between the chips + PCIE Gen3 endpoints - Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ - value for each of its 16 lanes. Each value is a uint16 formatted as - follows: - Bit 0:3 - up_rx_hint (bit 0 reserved) - Bit 4:7 - up_tx_preset - Bit 8:11 - dn_rx_hint (bit 0 reserved) - Bit 12:15 - dn_tx_preset - </description> - <simpleType> - <uint16_t><default> - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777 - </default></uint16_t> - <array>16</array><!-- Lane --> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>PROC_PCIE_LANE_EQUALIZATION_GEN4</id> - <description>PCIE Lane Equalization values for each PHB - Creator: MRW - Purpose: Holds settings which are loaded into the HW to optimize the - PCIE lane signal eye between the chips + PCIE Gen4 endpoints - Data Format: 16 entries of 16 bytes of EQ data per PHB. Each PHB has an EQ - value for each of its 16 lanes. Each value is a uint16 formatted as - follows: - Bit 0:3 - up_rx_hint (bit 0 reserved) - Bit 4:7 - up_tx_preset - Bit 8:11 - dn_rx_hint (bit 0 reserved) - Bit 12:15 - dn_tx_preset - </description> - <simpleType> - <uint16_t><default> - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777, - 0x7777,0x7777,0x7777,0x7777 - </default></uint16_t> - <array>16</array><!-- Lane --> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MSS_CAL_ABORT_ON_ERROR</id> - <description> - Whether or not to abort on the first DDR PHY calibration error. - Firmware should always have this set to NO. YES can be used in the - lab for troubleshooting, screening, etc. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_CAL_ABORT_ON_ERROR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SBE_SYS_CONFIG</id> - <description> - System Configuration information - 1 indicates a chip present - </description> - <simpleType> - <uint64_t> - <default>0x0</default> - </uint64_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SBE_SYS_CONFIG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SECUREBOOT_PROTECT_DECONFIGURED_TPM</id> - <description> - To deconfigure a TPM in a secure system - 01 to set TDP bit - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SECUREBOOT_PROTECT_DECONFIGURED_TPM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PERF_24x7_INVOCATION_TIME_MS</id> - <description> - Time between invocations of the 24x7 performance collection function on - GPE1. The time (in milliseconds) is derived as 2^PERF_24x7_INVOCATION_TIME_MS - with 0 indicating the function is OFF. - Consumer: p9_hcode_image_build.c -> - SGPE Header field - Provided by the Machine Readable Workbook to tune the collection. - Platform default: 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_PERF_24x7_INVOCATION_TIME_MS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CME_INSTRUCTION_TRACE_ENABLE</id> - <description> - Enables the SGPE Hcode to enable the CME instruction traces into the L3 - Trace array for debug. Note: all configured CMEs will be put into this - mode if this attribute is ON. - - Consumer: p9_hcode_image_build.c -> - SGPE Header field - - Platform default: OFF - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CME_INSTRUCTION_TRACE_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CP_REFCLOCK_RCVR_TERM</id> - <description> - Defines system specific value of processor refclock receiver termination - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CP_REFCLOCK_RCVR_TERM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IO_REFCLOCK_RCVR_TERM</id> - <description> - Defines system specific value of PCI refclock receiver termination - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IO_REFCLOCK_RCVR_TERM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <!-- explicitly chose not to add support for this platInit attribute --> - <id>SECTOR_BUFFER_STRENGTH</id> - <description> - Sector buffer strength - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SECTOR_BUFFER_STRENGTH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <!-- explicitly chose not to add support for this platInit attribute --> - <id>PULSE_MODE_ENABLE</id> - <description> - enable the pulse mode - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PULSE_MODE_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <!-- explicitly chose not to add support for this platInit attribute --> - <id>PULSE_MODE_VALUE</id> - <description> - value for pulse mode - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PULSE_MODE_VALUE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_PWR_INTERCEPT</id> - <description> - Machine Readable Workbook Power Curve Intercept for DIMM - Used to get the VDDR and VDDR+VPP power curve for each DIMM - Decoded and used to set ATTR_MSS_TOTAL_PWR_INTERCEPT - Key Value pair - KEY (0-19): In order - DIMM_SIZE = bits 0-3, - DIMM_GEN = 4-5, - DIMM_TYPE = 6-7, - DIMM_WIDTH = 8-9, - DIMM_DENSITY = 10-12, - DIMM_STACK_TYPE = 13-14, - DRAM_MFGID = 15-16, - DIMMS_PER_PORT = 17-18, - Bits 19-32: Not used - VALUE (bits 32-63) in cW: - VMEM power curve = 32-47 - VMEM+VPP power curve = 48-63 - Consumers: eff_config_thermal - </description> - <simpleType> - <uint64_t> - <default> - 0xffffe00002CC03AE,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0 - </default> - </uint64_t> - <array>100</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_PWR_INTERCEPT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_PWR_SLOPE</id> - <description> - Machine Readable Workbook Power Curve Slope for DIMM - Used to get the VDDR and VDDR+VPP power curve for each DIMM - Decoded and used to set ATTR_MSS_TOTAL_PWR_INTERCEPT - Key Value pair - KEY (0-19): In order - DIMM_SIZE = bits 0-3, - DIMM_GEN = 4-5, - DIMM_TYPE = 6-7, - DIMM_WIDTH = 8-9, - DIMM_DENSITY = 10-12, - DIMM_STACK_TYPE = 13-14, - DRAM_MFGID = 15-16, - DIMMS_PER_PORT = 17-18, - Bits 19-32: Not used - VALUE (bits 32-63) in cW: - VMEM power curve = 32-47 - VMEM+VPP power curve = 48-63 - Consumers: eff_config_thermal - </description> - <simpleType> - <uint64_t> - <default> - 0xffffe00003FD0546,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, - 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0 - </default> - </uint64_t> - <array>100</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_PWR_SLOPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - - -<attribute> - <id>MSS_MRW_REFRESH_RATE_REQUEST</id> - <description> - Machine Readable Workbook Refresh Rate - Desired refresh interval used in refresh register 0, MBAREF0Q_CFG_REFRESH_INTERVAL - 7.8 us (SINGLE) - 3.9 us (DOUBLE) - 7.02 us (SINGLE_10_PERCENT_FASTER) - 3.51 us (DOUBLE_10_PERCENT_FASTER) - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_REFRESH_RATE_REQUEST</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PM_SAFE_VOLTAGE_MV</id> - <description> - Voltage (in mV) to move to if the Power Management function fails. - Provided by the MRW. - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PM_SAFE_VOLTAGE_MV</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IVRM_STRENGTH_LOOKUP</id> - <description> - Producer: MRWB. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>64</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IVRM_STRENGTH_LOOKUP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IVRM_VIN_MULTIPLIER</id> - <description> - Producer: MRWB. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>64</array> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IVRM_VIN_MULTIPLIER</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IVRM_VIN_MAX_MV</id> - <description> - Producer: MRWB. - </description> - <simpleType> - <uint16_t> - </uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IVRM_VIN_MAX_MV</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IVRM_STEP_DELAY_NS</id> - <description> - Producer: MRWB. - </description> - <simpleType> - <uint16_t> - </uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IVRM_STEP_DELAY_NS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>IVRM_STABILIZATION_DELAY_NS</id> - <description> - Producer: MRWB. - </description> - <simpleType> - <uint16_t> - </uint16_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_IVRM_STABILIZATION_DELAY_NS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SYSTEM_RESCLK_DISABLE</id> + <id>SYSTEM_VDM_DISABLE</id> <description> - Disables the enablement of resonant clocking in the system. + Disables the enablement of Voltage Droop Monitors (VDM) in the system. Producer: Override Consumers: - p9_pstate_parameter_block to clear the flag for CME QuadManager Hcode + p9_pstate_parameter_block to clear flag for CME QuadManager Hcode reaction </description> <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_RESCLK_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>BAD_DQ_BITMAP</id> - <description> - Bad DQ bitmap from a controller point of view. - The data is a 10 byte bitmap for each of 4 possible ranks. - The bad DQ data is stored in NVRAM, and it is stored in a special format - translated to a DIMM Connector point of view. - All of these details are hidden from the user of this attribute. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2,4,10</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_BAD_DQ_BITMAP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VREF_CAL_ENABLE</id> - <description> - A bit vector denoting bits in every DP16 on the port to be calibrated. - That is, all of the set bits will be calibrated for all DP16. A value - of zero indicates the calibration should not be run. - </description> - <simpleType> - <uint16_t> - </uint16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VREF_CAL_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_RDVREF_CAL_ENABLE</id> - <description> - A bit vector denoting bits in every DP16 on the port to be calibrated. - That is, all of the set bits will be calibrated for all DP16. A value - of zero indicates the calibration should not be run. - </description> - <simpleType> - <uint16_t> - </uint16_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_RDVREF_CAL_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VREF_DAC_NIBBLE</id> - <description> - Value for VREF DAC nibbles - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VREF_DAC_NIBBLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MVPD_FWMS</id> - <description> - Mark store records from MPVD Lx keyword - </description> - <simpleType> - <uint32_t> - </uint32_t> - <array>2,8</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MVPD_FWMS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_VCCD_OVERRIDE</id> - <description> - Whether or not to override VCCD. Defaults to no. - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_VCCD_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>ORDINAL_ID</id> - <description>Ordinal ID of a target</description> - <simpleType> - <uint32_t> - <default>0xFFFFFFFF</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <writeable/> - <no_export/> -</attribute> - -<attribute> - <id>RAW_MTM</id> - <description> - Raw value of system MTM - </description> - <simpleType> - <string> - <sizeInclNull>64</sizeInclNull> - </string> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>SYSTEM_RING_DBG_MODE</id> - <description> - Debug modes supported for CME/SGPE Scan layout in HOMER - SCAN_RING_NO_DEBUG = 0x00, SCAN_RING_TRACE_DEBUG = 0x01 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_RING_DBG_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>POUND_W_STATIC_DATA_ENABLE</id> - <description> - Enables pstate parameter block code to use the static #W data - Consumer: p9_pstate_parameter_block.C -> - - Platform default: OFF=0 - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_POUND_W_STATIC_DATA_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>AUX_FUNC_INVOCATION_TIME_MS</id> - <description> - Time between invocations of auxiliary function on - GPE1. The time (in milliseconds) is derived as 2^ATTR_AUX_FUNC_INVOCATION_TIME_MS - with 0 indicating the function is OFF. - Consumer: p9_hcode_image_build.c -> - SGPE Header field - Provided by the Machine Readable Workbook to tune the collection. - Platform default: 1 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_AUX_FUNC_INVOCATION_TIME_MS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PGPE_HCODE_FUNCTION_ENABLE</id> - <description> - Enables the PGPE Hcode to physically perform frequency and voltage - operations based on constructed parameters (eg #V VPD, system - parameters, biases, WPF VFRTs. etc). If OFF, the PGPE provides an - immedicate good response to all Pstate/WOF IPC operations from the - OCC for firmware integration testing purposes. - - Consumer: p9_hcode_image_build.c -> - PGPE Header field - - Platform default: OFF - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_PGPE_HCODE_FUNCTION_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - </attribute> - -<attribute> - <id>MSS_MEM_PORT_POS_OF_FAIL_THROTTLE</id> - <description> - This is the fapi position of the port that failed to calculate - memory throttles given the passed in watt target and or utilization - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MEM_PORT_POS_OF_FAIL_THROTTLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_MRW_UNSUPPORTED_RANK_CONFIG</id> - <description> - Each MCA value is a 64-bit vector, where each byte represents an unsupported rank configuration. - Each nibble in the byte represents the total count of ranks (master and slave) - on each DIMM. The left-most nibble represents slot 0 and the right represents 1. - </description> - <simpleType> - <uint64_t> - </uint64_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>XIVE_HW_RESET</id> - <description> - Used to tell INTRP code whether to use the XIVE HW Reset - or a software based reset. - 0 = Software based reset - 1 = XIVE HW reset - </description> - <simpleType> - <uint8_t> - <default>0</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MAX_SBE_SEEPROM_SIZE</id> - <description> - Defines the maximum Seeprom storage size for the fully-customized SBE image - permitted by the platform. - For platforms (FSP/HB FW) which require the image to be constrained into a - physical storage device (SEEPROM), this should reflect the maximum size of that - memory (e.g., 256KB). - For platforms (Cronus) which may use a customized image in a virtual - envrionment with no physical storage constraints, this size may be - larger than the physical SEEPROM size. - </description> - <simpleType> - <uint32_t> - <default>0x40000</default> - </uint32_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MAX_SBE_SEEPROM_SIZE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DO_MSS_WR_VREF</id> - <description> - In sub DD1.02 Nimbus in the WR VREF algorithm, certain work-arounds are needed - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_DO_MSS_WR_VREF</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SKIP_HW_VREF_CAL</id> - <description> - - In sub DD1.02 Nimbus the HW VREF calibrations should not be run - - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SKIP_HW_VREF_CAL</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SKIP_RD_VREF_VREFSENSE_OVERRIDE</id> - <description> - - In sub DD1.03 Nimbus the HW VREF calibrations should not be run - - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SKIP_RD_VREF_VREFSENSE_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DO_MSS_VREF_DAC</id> - <description> - VREF DAC work-around for Nimbus sub DD1.02 - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_DO_MSS_VREF_DAC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DO_MSS_TRAINING_BAD_BITS</id> - <description> - For Nimbus pre DD1.02 we want to pass DDR training if we see 'correctable' - errors. This isn't the case for post-DD1.02 where we want to pass/fail - training based on the results from the PHY itself - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_DO_MSS_TRAINING_BAD_BITS</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_RTT_NOM</id> - <description> - RTT_NOM value read to be programmed into MRS02 - For RDIMMS, this is based off of the VPD - For LRDIMMS, this comes from the SPD - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2,4</array> + <uint8_t> + <default>0x01</default> + </uint8_t> </simpleType> - <persistency>volatile-zeroed</persistency> <readable/> <writeable/> + <persistency>volatile</persistency> <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_RTT_NOM</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_RTT_NOM_OVERRIDE_DISABLE</id> - <description> - Set equal to 1 to disable setting of RTT_NOM to use RTT_WR values - during WR_LEVEL calibration. - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <writeable/> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_RTT_NOM_OVERRIDE_DISABLE</id> + <id>ATTR_SYSTEM_VDM_DISABLE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> </attribute> -<attribute> - <id>EFF_DRAM_RTT_WR</id> - <description> - RTT_WR value read to be programmed into MRS02 - For RDIMMS, this is based off of the VPD - For LRDIMMS, this comes from the SPD - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_RTT_WR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_DRAM_RTT_PARK</id> - <description> - RTT_PARK value read to be programmed into MRS05 - For RDIMMS, this is based off of the VPD - For LRDIMMS, this comes from the SPD - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>2,2,4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_DRAM_RTT_PARK</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_RANK_GROUP_OVERRIDE</id> - <description> - - Override PHY RANK_PAIR settings. First uint16 value is for RANK_PAIR0 - register value, and second is for RANK_PAIR1. Note that DIMM1 ranks in - a dual-drop config will be converted from Centaur canonical number - (4,5) to correct PHY settings (2,3). Set this attribute to zero - to use default settings. - - </description> - <simpleType> - <uint16_t> - <default>0x0</default> - </uint16_t> - <array>2,2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_RANK_GROUP_OVERRIDE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>DISABLE_I2C_ENGINE2_PORT0_DIAG_MODE</id> - <description> - Used to tell I2C code whether to run - I2C Engine 2 Port 0 in diag mode or not - 0 = Use Diag Mode - 1 = Disable Diag Mode - </description> - <simpleType> - <uint8_t> - <default>1</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> -</attribute> - -<attribute> - <id>MSS_MRW_DRAM_WRITE_CRC</id> - <description> - Enables DRAM Write CRC - </description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_DRAM_WRITE_CRC</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>MSS_MRW_TEMP_REFRESH_MODE</id> - <description>Enumeration for Temperature refresh mode</description> - <enumerator> - <name>DISABLE</name> - <value>0</value> - </enumerator> - <enumerator> - <name>ENABLE</name> - <value>1</value> - </enumerator> -</enumerationType> - -<attribute> - <id>MSS_MRW_TEMP_REFRESH_MODE</id> - <description> - Used in MR4 A3 - Temperature refresh mode - Should be defaulted to disable - </description> - <simpleType> - <uint8_t> - <default>DISABLE</default> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_MRW_TEMP_REFRESH_MODE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>NDL_MESHCTRL_SETUP</id> - <description>Control NDL training:meshctrl setup</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_NDL_MESHCTRL_SETUP</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_REORDER_QUEUE_SETTING</id> - <description>Contains the settings for write/read reorder queue</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_REORDER_QUEUE_SETTING</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<enumerationType> - <id>HDAT_I2C_DEVICE_TYPE</id> - <description>Pulled from the MRW, this describes the device - type to the HDAT. This is for I2C devices only. - </description> - <enumerator> - <name>955X</name> - <value>0x1</value> - </enumerator> - <enumerator> - <name>SEEPROM</name> - <value>0x2</value> - </enumerator> - <enumerator> - <name>NUVOTON_TPM</name> - <value>0x3</value> - </enumerator> - <enumerator> - <name>MEX_FPGA</name> - <value>0x4</value> - </enumerator> - <enumerator> - <name>UCX90XX</name> - <value>0x5</value> - </enumerator> - <enumerator> - <name>NVLINK</name> - <value>0x6</value> - </enumerator> - <enumerator> - <name>UNKNOWN</name> - <value>0xFF</value> - </enumerator> -</enumerationType> - -<enumerationType> - <id>HDAT_I2C_DEVICE_PURPOSE</id> - <description>Pulled from the MRW, this describes the device - purpose to the HDAT. This is for I2C devices only. - </description> - <enumerator> - <name>CABLE_CARD_PRES</name> - <value>0x1</value> - </enumerator> - <enumerator> - <name>CABLE_CARD_POWER_SENSE</name> - <value>0x2</value> - </enumerator> - <enumerator> - <name>CABLE_CARD_POWER_CONTROL</name> - <value>0x3</value> - </enumerator> - <enumerator> - <name>TPM</name> - <value>0x4</value> - </enumerator> - <enumerator> - <name>MODULE_VPD</name> - <value>0x5</value> - </enumerator> - <enumerator> - <name>DIMM_SPD</name> - <value>0x6</value> - </enumerator> - <enumerator> - <name>PROC_MODULE_VPD</name> - <value>0x7</value> - </enumerator> - <enumerator> - <name>SBE_SEEPROM</name> - <value>0x8</value> - </enumerator> - <enumerator> - <name>PLANAR_VPD</name> - <value>0x9</value> - </enumerator> - <enumerator> - <name>PCI_HOTPLUG</name> - <value>0xA</value> - </enumerator> - <enumerator> - <name>NVLINK</name> - <value>0xB</value> - </enumerator> - <enumerator> - <name>WINDOW_OPEN</name> - <value>0xD</value> - </enumerator> - <enumerator> - <name>PHYSICAL_PRESENCE</name> - <value>0xE</value> - </enumerator> - <enumerator> - <name>UNKNOWN</name> - <value>0xFF</value> - </enumerator> -</enumerationType> - -<attribute> - <id>PNOR_FLASH_WORKAROUNDS</id> - <description>Save state of the sfc driver flash workarounds for runtime</description> - <simpleType> - <uint32_t><default>0</default></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>HTM_QUEUES</id> - <description> The number of HTM queues to be reserved for each port in order - to improve HTM trace performance. - This number is calculated in memory grouping process when the - HTM trace spaces are determined. - Set by p9_mss_eff_grouping. - Used by p9_htm_setup. - </description> - <simpleType> - <uint8_t> - </uint8_t> - <array>8</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HTM_QUEUES</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CME_CHTM_TRACE_ENABLE</id> - <description> - Enables the SGPE Hcode to enable the CME instruction traces into the CHTM - for debug. Note: all configured CMEs will be put into this - mode if this attribute is ON. - - Consumer: p9_hcode_image_build.c -> - SGPE Header field - - Platform default: OFF - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CME_CHTM_TRACE_ENABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CME_CHTM_TRACE_MEMORY_CONFIG</id> - <description> - CHTM Trace Memory Configuration value goes directly into CHTM_MEM register. - User is responsible to put correct data for each bit field of the register. - - Consumer: p9_hcode_image_build.c -> - SGPE Header field - - Platform default: 0 - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_CME_CHTM_TRACE_MEMORY_CONFIG</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_PHY_SEQ_REFRESH</id> - <description> - Controls ENABLE/DISABLE of workaround that sets - the PHY sequencer to trigger refresh after draminit. - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_PHY_SEQ_REFRESH</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MSS_RUN_DCD_CALIBRATION</id> - <description> - Selects whether or not DCD should be run - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MSS_RUN_DCD_CALIBRATION</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>VDM_VID_COMPARE_BIAS_0P5PCT</id> - <description> - VDM Voltage Compare Bias - % of bias (signed twos - complement in - 0.5 percent steps) that is applied to the #W VDM - VID Compare before placement in the respective Pstate - Paramter Blocks that will be consumed - by Hcode. - Array of 4 entries: 0 = PowerSave, 1 = - Nominal; 2 = Turbo; 3 = UltraTurbo - If index 4 is non-zero, the - other entries are considered - valid.Producer:MRWB. - </description> - <simpleType> - <uint8_t></uint8_t> - <array>4</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <hwpfToHbAttrMap> - <id>ATTR_VDM_VID_COMPARE_BIAS_0P5PCT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>CORE_THROTTLE_ASSERT_COUNT</id> - <description> - The number of PGPE Fixed Timer Interrupts (see Hcode documentation for - durations) to assert a core throttle when - OCC Scratch 2[Core Throttle Continuous Change Enable] is set. - A value of 0 when Continuous Change Enable is set will deassert throttle. - Producer: Override/Lab - Consumers: - p9_hcode_image_build.c -> PGPE Header field - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CORE_THROTTLE_ASSERT_COUNT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>PREVIOUS_SBE_ERROR</id> - <description> - Keeps track of the previous SBE error. We need to know - what last occurred to know what action we need to take. - </description> - <simpleType> - <uint8_t><default>0</default></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> -</attribute> - -<attribute> - <id>CORE_THROTTLE_DEASSERT_COUNT</id> - <description> - The number of PGPE Fixed Timer Interrupts (see Hcode documentation for - machine dependent durations) to deassert core throttle when - OCC Scratch 2[Core Throttle Continuous Change Enable] is set. - A value of 0 when Continuous Change Enable is set and - ATTR_CORE_THROTTLE_ASSERT_COUNT is non-0, throttling is always on. - Producer: Override/Lab - Consumers: - p9_hcode_image_build.c -> PGPE Header field - </description> - <simpleType> - <uint32_t></uint32_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_CORE_THROTTLE_DEASSERT_COUNT</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SLOT_NAME</id> - <description>PCIe slot name definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>SLOT_INDEX</id> - <description>PCIe slot index definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>PCIE_32BIT_MMIO_SIZE</id> - <description>PCIe slot 32bit MMIO size definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>PCIE_64BIT_MMIO_SIZE</id> - <description>PCIe slot 64bit MMIO size definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>PCIE_32BIT_DMA_SIZE</id> - <description>PCIe slot 32bit DMA size definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>PCIE_64BIT_DMA_SIZE</id> - <description>PCIe slot 64bit DMA size definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>HDDW_ORDER</id> - <description>PCIe slot HDDW order definition</description> - <simpleType> - <uint8_t> - </uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>MGC_LOAD_SOURCE</id> - <description>defines MGC load source</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>PCIE_CAPABILITES</id> - <description>Denotes the capabilites of this pcie slot</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>VENDOR_ID</id> - <description>PCIe vendor ID definition</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>MAX_POWER</id> - <description>Defines the maximum power consumption for a PCIe slot</description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>non-volatile</persistency> - <readable/> - <no_export/> -</attribute> - -<attribute> - <id>EFF_REGISTER_TYPE</id> - <description> - Register Type - Decodes SPD Byte 131 - creator: mss_eff_cnfg - consumer: eff_dimm - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2, 2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_REGISTER_TYPE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_RCD_MFG_ID</id> - <description> - Register Manufacturer ID Code - Decodes SPD Byte 133 and 134 - creator: mss_eff_cnfg - </description> - <simpleType> - <uint16_t></uint16_t> - <array>2, 2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_RCD_MFG_ID</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>EFF_REGISTER_REV</id> - <description> - Register Revision Number - Decodes SPD Byte 135 - creator: mss_eff_cnfg - </description> - <simpleType> - <uint8_t></uint8_t> - <array>2, 2</array> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_EFF_REGISTER_REV</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SYSTEM_CORECACHE_SKEWADJ_DISABLE</id> - <description> - To allow for selective enablement for lab testing - To allow skew function to be enabled/disabled. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_CORECACHE_SKEWADJ_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>SYSTEM_CORECACHE_DCADJ_DISABLE</id> - <description> - To allow for selective enablement for lab testing - To allow dcadj function to be enabled/disabled. - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_SYSTEM_CORECACHE_DCADJ_DISABLE</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> - -<attribute> - <id>MC_PLL_BUCKET</id> - <description> - MC pll bucket selection in async mode for Cumulus - </description> - <simpleType> - <uint8_t></uint8_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_MC_PLL_BUCKET</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> -</attribute> </attributes> diff --git a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml index 9c92984b0..563a1ac7f 100644..100755 --- a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml @@ -390,24 +390,6 @@ </attribute> <attribute> - <id>HOMER_PHYS_ADDR</id> - <description> - Physical address where HOMER image is placed in mainstore. - </description> - <simpleType> - <uint64_t></uint64_t> - </simpleType> - <persistency>volatile-zeroed</persistency> - <readable/> - <writeable/> - <hwpfToHbAttrMap> - <id>ATTR_HOMER_PHYS_ADDR</id> - <macro>DIRECT</macro> - </hwpfToHbAttrMap> - <hbOnly/> -</attribute> - -<attribute> <id>HOMER_VIRT_ADDR</id> <description> Virtual address where HOMER memory is mapped into. If value is zero, @@ -1054,7 +1036,7 @@ <persistency>volatile-zeroed</persistency> <writeable/> <readable/> - <hwpfToHbAttrMap> + <hwpfToHbAttrMap> <id>ATTR_SECURITY_MODE</id> <macro>DIRECT</macro> </hwpfToHbAttrMap> diff --git a/src/usr/targeting/common/xmltohb/attribute_types_openpower.xml b/src/usr/targeting/common/xmltohb/attribute_types_openpower.xml index d6f518e5b..387eb03be 100644 --- a/src/usr/targeting/common/xmltohb/attribute_types_openpower.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types_openpower.xml @@ -1083,4 +1083,26 @@ ID for the sensor number returned with the elog. --> <!-- end HTMGT attributes --> +<attribute> + <id>MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id> + <description>Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_chip</description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>non-volatile</persistency> + <readable/> +</attribute> + +<attribute> + <id>MSS_UTIL_N_PER_MBA</id> + <description>cfg_nm_n_per_mba throttle N value that was calculated from MSS_DATABUS_UTIL_PER_MBA</description> + <simpleType> + <uint32_t></uint32_t> + </simpleType> + <persistency>volatile-zeroed</persistency> + <readable/> + <writeable/> +</attribute> + + </attributes> diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk index fca893c80..525ba5a37 100755 --- a/src/usr/targeting/common/xmltohb/common.mk +++ b/src/usr/targeting/common/xmltohb/common.mk @@ -59,6 +59,7 @@ XMLTOHB_TARGETS += ${XMLTOHB_SOURCE_TARGETS} # Temp defaults XML sources used by updatetempsxml.pl script TEMP_DEFAULTS_XML += tempdefaults.xml HB_TEMP_DEFAULTS_XML += hb_temp_defaults.xml +HB_CUSTOMIZED_ATTRS_XML += hb_customized_attrs.xml ATTRIBUTE_SERVICE_H += plat_attribute_service.H HB_PLAT_ATTR_SRVC_H += hb_plat_attr_srvc.H @@ -66,9 +67,15 @@ HB_PLAT_ATTR_SRVC_H += hb_plat_attr_srvc.H TEMP_GENERIC_XML += temp_generic.xml XMLTOHB_GENERIC_XML += generic.xml XMLTOHB_FAPI_XML += fapiattrs.xml + +#scripts for attribute/target xml manipulation XMLTOHB_MERGE_SCRIPT += mergexml.sh -XMLTOHB_TEMPS_MERGE_SCRIPT += updatetempsxml.pl -XMLTOHB_COMPILER_SCRIPT += xmltohb.pl -VMM_CONSTS_FILE += vmmconst.h +XMLTOHB_TEMPS_MERGE_SCRIPT += updatetempsxml.pl +XMLTOHB_COMPILER_SCRIPT += xmltohb.pl +XMLTOHB_EKB_TARGATTR_SCRIPT += create_ekb_targattr.pl +XMLTOHB_DUPLICATE_SCRIPT += handle_duplicate.pl +XMLTOHB_SWAP_MAPPED_ATTR_SCRIPT += handle_fapi_attr_mapping.pl +XMLTOHB_REMOVE_HB_MAPPED_ATTR_SCRIPT += remove_hb_fapi_maps.pl +VMM_CONSTS_FILE += vmmconst.h GENERATED_CODE = ${XMLTOHB_TARGETS} diff --git a/src/usr/targeting/common/xmltohb/create_ekb_targattr.pl b/src/usr/targeting/common/xmltohb/create_ekb_targattr.pl new file mode 100755 index 000000000..6eb1f1153 --- /dev/null +++ b/src/usr/targeting/common/xmltohb/create_ekb_targattr.pl @@ -0,0 +1,241 @@ +#!/usr/bin/perl +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/targeting/common/xmltohb/create_ekb_targattr.pl $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2017 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# +# +# Usage: +# +# create_attr_ekb --fapi=fapiattrs.xml --attr=attribute_types_ekb.xml +# --targ=target_types.xmltohb --default=hb_temp_default.xml +# +# Purpose: +# +# This perl script processes the FAPI attributes in fapiattrs.xml, and the +# temporary defaults in hb_temp_defaults.xml and creates attribute_types_ekb.xml, +# and target_types_ekb.xml with equivalent Hostboot attribute definitions. +# + +use strict; +use XML::Simple; +use Data::Dumper; + +#add the fapi_utils path to include paths +#this is useful for debugging +push (@INC, "../../xmltohb"); + +require "fapi_utils.pl"; + +$XML::Simple::PREFERRED_PARSER = 'XML::Parser'; +use Digest::MD5 qw(md5_hex); + +#init variables +my $generic = ""; +my $fapi_filename = ""; +my $targ_filename = ""; +my $attr_filename = ""; +my $tempDefault_filename = ""; + +my $usage = 0; +use Getopt::Long; +GetOptions( "fapi:s" => \$fapi_filename, + "attr:s" => \$attr_filename, + "targ:s" => \$targ_filename, + "default:s" => \$tempDefault_filename, + "help" => \$usage, ); + +if( ($fapi_filename eq "") + || ($attr_filename eq "") + || ($targ_filename eq "") ) +{ + display_help(); + exit 1; +} +elsif ($usage) +{ + display_help(); + exit 0; +} + +#use the XML::Simple tool to convert the xml files into hashmaps +my $xml = new XML::Simple (KeyAttr=>[]); + +#data from the ekb fapi attributes +my $fapiXml = $xml->XMLin("$fapi_filename" , + forcearray => ['attribute'], + NoAttr => 1); + +#data from the temporary default xml +my $tempDefaultXml = $xml->XMLin("$tempDefault_filename" , + forcearray => ['attribute'], + NoAttr => 1); + +#################### +##### Generate attribute_types ##### + +print "\nGenerating attribute_types\n"; +my $numattrs = 0; + +open (my $ATTR_FH, ">$attr_filename") || + die "ERROR: unable to open $attr_filename\n"; + +print $ATTR_FH "<attributes>\n\n"; + +# Walk attribute definitions in fapiattrs.xml +foreach my $FapiAttr ( @{$fapiXml->{attribute}} ) +{ + #we dont need to worry about EC FEATURE attributes + if( $FapiAttr->{id} =~ /_EC_FEATURE/ ) + { + next; + } + #print "====" . $FapiAttr->{id} . "\n"; + + #Check if there are any defaults values we need to add to fapi attrs before generating HB + foreach my $tempDefault(@{$tempDefaultXml->{attribute}}) + { + #if we find a match, then add update the attribute w/ customized values + if ($tempDefault->{id} eq $FapiAttr->{id}) + { + if(exists $tempDefault->{default}) + { + #print "Found match for ".$tempDefault->{id}." default val is ".$tempDefault->{default}."\n"; + $FapiAttr->{default} = $tempDefault->{default}; + } + last; + } + } + + #use utility functions to generate enum xml, if possible + my $enum = createEnumFromAttr($FapiAttr); + #use utility functions to generate attribute xml + my $attr = createAttrFromFapi($FapiAttr); + + #Check if there are additional tags besides default we need to add to fapi attrs + foreach my $tempDefault(@{$tempDefaultXml->{attribute}}) + { + #if we find a match, then add update the attribute w/ customized values + if ($tempDefault->{id} eq $attr->{hwpfToHbAttrMap}->{id}) + { + foreach my $tag (keys %$tempDefault) + { + if($tag ne "default" && $tag ne "id" ) + { + #print "Found match for ".$tempDefault->{id}." $tag val is ".$tempDefault->{$tag}."\n"; + $attr->{$tag} = $tempDefault->{$tag}; + } + } + + last; + } + } + + #not all attribute have enumaterated values, so enums are optional + if($enum ne "0" && $enum ne "") + { + printTargEnum($ATTR_FH, $enum); + } + + #write to the attribute xml file + printTargAttr($ATTR_FH,$attr); + print $ATTR_FH "\n"; + $numattrs++; +} + +print "...$numattrs attributes generated from EKB\n"; +print $ATTR_FH "</attributes>"; +close $ATTR_FH; + + +#################### +##### Generate target_types ##### + +print "\nGenerating target_types\n"; + +open (my $TARG_FH, ">$targ_filename") || + die "ERROR: unable to open $targ_filename\n"; + +my $allTargetExt = {}; + +# Walk attribute definitions in fapiattrs.xml +foreach my $FapiAttr ( @{$fapiXml->{attribute}} ) +{ + #print "====" . $FapiAttr->{id} . "\n"; + #like when generating attributes, skip the _EC_FEATURES + if( $FapiAttr->{id} =~ /_EC_FEATURE/ ) + { + next; + } + #use the utility function to generate a target extension xml + createTargetExtensionFromFapi($FapiAttr,$allTargetExt); +} + +#begin writing the file +print $TARG_FH "<attributes>\n\n"; + +# Print out all the generated stuff +foreach my $targ (@{$allTargetExt->{targetTypeExtension}}) +{ + #print $targ->{id} ."\n"; + printTargExt($TARG_FH,$targ); + print $TARG_FH "\n"; +} + +print $TARG_FH "</attributes>"; +close $TARG_FH; + + +########################################################### +########################################################### + + +sub display_help +{ + use File::Basename; + my $scriptname = basename($0); + print STDERR " +Description: + + This perl script processes the FAPI attributes in fapiattrs.xml, and the + temporary defaults in hb_temp_defaults.xml and creates attribute_types_ekb.xml, + and target_types_ekb.xml with equivalent Hostboot attribute definitions. + +Usage: + + $scriptname --help + + $scriptname --fapi=fapifname + fapifname is complete pathname of the fapiattrs.xml file + + $scriptname --attr=attrofname + attrofname is complete pathname of the attribute_types_ekb.xml + + $scriptname --targ=targofname + targofname is complete pathname of the target_types_ekb.xml + + $scriptname --default=defaultifname + defaultifname is the complete pathname of the hb_temp_defaults.xml +\n"; +} diff --git a/src/usr/targeting/common/xmltohb/handle_duplicate.pl b/src/usr/targeting/common/xmltohb/handle_duplicate.pl new file mode 100755 index 000000000..1a03df31a --- /dev/null +++ b/src/usr/targeting/common/xmltohb/handle_duplicate.pl @@ -0,0 +1,314 @@ +#!/usr/bin/perl +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/targeting/common/xmltohb/handle_duplicate.pl $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2017 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# +# +# Usage: +# +# handle_duplicate --ekbXmlFile=attribute_types_ekb.xml --hbXmlFile=attribute_types_src.xml +# --fapi2Header=attribute_service.H --outFile=attribute_types_full.xml +# +# Purpose: +# +# This perl script merges together attribute_types_ekb and attribute_types_src into one output +# file that can be consumed by either the FIPS build or the op-build process. The trick is that +# we don't want the EKB attributes to override fapi-mapped attributes we have already defined in +# hostboot's xml. +# + +use strict; + +use Getopt::Long; +use XML::Simple; +use Text::Wrap; +use Data::Dumper; +use POSIX; +use Env; +use XML::LibXML; +use File::Temp qw(tempfile); + +require "fapi_utils.pl"; + +$XML::Simple::PREFERRED_PARSER = 'XML::Parser'; + + +my $ekbXmlFullPath = ""; +my $hbXmlFullPath = ""; +my $fapi2HeaderFullPath = ""; +my $outFullPath = ""; +my $usage = 0; + + +GetOptions("ekbXmlFile:s" => \$ekbXmlFullPath, + "hbXmlFile:s" => \$hbXmlFullPath, + "fapi2Header:s" => \$fapi2HeaderFullPath, + "outFile:s" => \$outFullPath, + "help" => \$usage); + + +if( ($ekbXmlFullPath eq "") + || ($hbXmlFullPath eq "") + || ($fapi2HeaderFullPath eq "") + || ($outFullPath eq "") ) +{ + display_help(); + exit 1; +} +elsif ($usage) +{ + display_help(); + exit 0; +} + + +my %completeAttr; + +#attributes defined in attribute_types.xml w/ fapi2 mapping +my %hwpfAttributes; + + +#use the XML::Simple tool to convert the xml files into hashmaps +my $xml = new XML::Simple (KeyAttr=>[]); +use Digest::MD5 qw(md5_hex); + + +#Read in EKB attribute xml (fapiattrs.xml) +my $allEKBAttributes = $xml->XMLin($ekbXmlFullPath , + forcearray => ['attribute','hwpfToHbAttrMap','enumerationType','enumerator']); + +#Read in HB attribute xml (attribute_types.xml) +my $allHBAttributes = $xml->XMLin($hbXmlFullPath , + forcearray => ['attribute','hwpfToHbAttrMap','enumerationType','enumerator']); + + +#Get a list of all the function backed fapi2 attributes +my @funcBackedAttr = getFuncionBackedAttrs($fapi2HeaderFullPath); + +#Create a list of all the HB attributes with a HWPF mapping +foreach my $attribute (@{$allHBAttributes->{attribute}}) +{ + if (exists $attribute->{hwpfToHbAttrMap} ) + { + push (@{%hwpfAttributes->{attribute}}, $attribute); + } +} + + +#Looping variable +my $matchFound = 0; + +#Loop over all of the EKB attributes and look for a duplcate in HB list +foreach my $ekbAttr (@{$allEKBAttributes->{attribute}}) +{ + my $isFuncBacked = 0; + $matchFound = 0; + my $theHbAttr; + my $ekbAttrId = $ekbAttr->{hwpfToHbAttrMap}[0]->{id}; + + #check if this matches any in our list of func backed attrs + foreach my $id (@funcBackedAttr) + { + if ($id eq $ekbAttrId) + { + $isFuncBacked = 1; + last; + } + } + + #If it is a function backed attribute , no need to add it + #we want the function to overrule anything else. + if($isFuncBacked) + { + print "SKIPPING EKB $ekbAttrId - function backed\n"; + next; + } + + #Loop over HB attrs until we find a match + foreach my $hbAttr (@{%hwpfAttributes->{attribute}}) + { + my $hbFapiId = $hbAttr->{hwpfToHbAttrMap}[0]->{id}; + + if($ekbAttrId eq $hbFapiId) + { + $matchFound = 1; + $theHbAttr = $hbAttr; + last; + } + } + + #if no match was found we will assume this is a new attribute and add it + if(!$matchFound) + { + push (@{$completeAttr{attribute}}, $ekbAttr); + } + #otherwise we need to check what was updated and handle it accordingly + else + { + #Special case big hammer will ignore the generated version and + # always choose what HB coded up + my $ignoreEkb = 0; + if( exists $theHbAttr->{ignoreEkb} ) + { + $ignoreEkb; + } + + #if the EKB's description was updated we will assume their description + # to be more correct so just update the HB attr's description + my $ekbDesc = $ekbAttr->{description}; + my $hbDesc = $theHbAttr->{description}; + if($ekbDesc ne $hbDesc) + { + $theHbAttr->{description} = $ekbDesc; + } + + #if persistancy has changed we want to notify the developer so cause a fail + my $ekbPersist = $ekbAttr->{persistancy}; + my $hbPersist = $theHbAttr->{persistancy}; + if($ekbPersist ne $hbPersist) + { + die "ERROR Hostboot says persistancy of ".$ekbAttrId." is ".$hbPersist." and Fapi says it is ".$ekbPersist."\n"; + } + + #if array dimmensions have changed we want to notify the developer so cause a fail + my $hbArrayDimmensions = getArrayDimmensions(%$theHbAttr); + my $ekbArrayDimmensions = getArrayDimmensions(%$ekbAttr); + if($hbArrayDimmensions ne $ekbArrayDimmensions) + { + die "ERROR Hostboot says array dimmensions of ".$ekbAttrId." is ".$hbArrayDimmensions." and Fapi says it is ".$ekbArrayDimmensions."\n"; + } + + #if attribute type has changed we want to notify the developer so cause a fail + my $hbAttrType = getAttrType(%$theHbAttr); + my $ekbAttrType = getAttrType(%$ekbAttr); + if($hbAttrType ne $ekbAttrType) + { + die "ERROR Hostboot says type of ".$ekbAttrId." is ".$hbAttrType." and Fapi says it is ".$ekbAttrType."\n"; + } + } +} + +#also need to add all of the EKB enumerations +foreach my $ekbEnum (@{$allEKBAttributes->{enumerationType}}) +{ + $matchFound = 0; + my $ekbEnumId = $ekbEnum->{id}; + my $theHbEnum; + #we dont want to add duplicates so check if the enumeration exists already in HB + foreach my $hbEnum (@{%$allHBAttributes->{enumerationType}}) + { + my $hbEnumId = $hbEnum->{id}; + + if($ekbEnumId eq $hbEnumId) + { + $matchFound = 1; + $theHbEnum = $hbEnum; + last; + } + } + + #if not found already, then add the enum + if(!$matchFound) + { + push (@{$completeAttr{enumerationType}}, $ekbEnum); + } + #if a copy already exists in HB then we just want to update the values and description + else + { + $theHbEnum->{description} = $ekbEnum->{description}; + $theHbEnum->{enumerator} = $ekbEnum->{enumerator}; + } +} + +#add all HB attributes to completeAttr (the hash holding output xml) +foreach my $hbAttr (@{$allHBAttributes->{attribute}}) +{ + push (@{$completeAttr{attribute}}, $hbAttr); +} + +#also add the HB enums to completeAttr hash +foreach my $hbEnum (@{$allHBAttributes->{enumerationType}}) +{ + push (@{$completeAttr{enumerationType}}, $hbEnum); +} + + +#To make things look nicer we add a newline after each attribute or enumerationType +my $completeXml = $xml->XMLout(\%completeAttr, RootName => 'attributes', NoAttr => 1 ); +my $complete_fh_temp = new File::Temp( UNLINK => 1 ); + +print $complete_fh_temp $completeXml; + +seek $complete_fh_temp, 0, 0 or die "Seek $complete_fh_temp failed: $!\n"; + +open(my $complete_fh, '>', $outFullPath) || die; + +foreach my $row (<$complete_fh_temp>) +{ + chomp $row; + print $complete_fh $row."\n"; + if(index($row, "</enumerationType>") != -1 || + index($row, "</attribute>") != -1) + { + print $complete_fh "\n"; + } +} + +close $complete_fh; + + + +sub display_help +{ + use File::Basename; + my $scriptname = basename($0); + print STDERR " +Description: + + This perl script merges together attribute_types_ekb and attribute_types_src into one output + file that can be consumed by either the FIPS build or the op-build process. The trick is that + we don't want the EKB attributes to override fapi-mapped attributes we have already defined in + hostboot's xml. + +Usage: + + $scriptname --help + + $scriptname --ekbXmlFile=generatedEkbAttrXml + generatedEkbAttrXml is complete pathname of the attribute_types_ekb.xml file + that is generated by create_ekb_targattr.pl + + $scriptname --hbXmlFile=srcAttrXml + srcAttrXml is complete pathname of the attribute_types_src.xml, or file that + consists of all the relevent srcs cat'ed together + + $scriptname --fapi2Header=attrServiceHeader + attrServiceHeader is complete pathname of the attribute_service.H file from hostboot + + $scriptname --outFile=completeAttrXml + completeAttrXml is the complete pathname of the attribute_types_full.xml , or file + that will be consumed by downstream repo (FIPS or op-build) +\n"; +} diff --git a/src/usr/targeting/common/xmltohb/handle_fapi_attr_mapping.pl b/src/usr/targeting/common/xmltohb/handle_fapi_attr_mapping.pl new file mode 100755 index 000000000..05b2cb7fd --- /dev/null +++ b/src/usr/targeting/common/xmltohb/handle_fapi_attr_mapping.pl @@ -0,0 +1,287 @@ +#!/usr/bin/perl +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/targeting/common/xmltohb/handle_fapi_attr_mapping.pl $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2017 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# +# +# Usage: +# +# handle_fapi_attr_mapping --fullAttrXml=attribute_types_full.xml +# --fullTargetXml=target_types_full.xml +# --srcTargetXml=target_types_src.xml +# --ekbTargetXml=target_types_ekb.xml +# --fapi2Header=attribute_service.H +# +# Purpose: +# +# This perl script merges together targetExtensions from target_types_ekb and targetType tags from +# target_types_src. The trick is to avoid adding attributes on targets where the attribute already +# exists. Also we don't want to add function backed attributes onto targets. The last step ensures +# that we use the Hostboot name for the attribute, as hostboot can change the name in attribute_types.xml +# and if a mapping exists there we want to use the hostboot name. +# + +use strict; + +use Getopt::Long; +use XML::Simple; +use Text::Wrap; +use Data::Dumper; +use POSIX; +use Env; +use XML::LibXML; +use File::Temp qw(tempfile); + +require "fapi_utils.pl"; + +$XML::Simple::PREFERRED_PARSER = 'XML::Parser'; + + +my $fullTargetXmlFullPath = ""; +my $fullAttrXmlFullPath = ""; +my $srcTargetXmlFullPath = ""; +my $ekbTargetXmlFullPath = ""; +my $fapi2HeaderFullPath = ""; +my $usage = 0; + + + +GetOptions("fullAttrXml:s" => \$fullAttrXmlFullPath, + "fullTargetXml:s" => \$fullTargetXmlFullPath, + "srcTargetXml:s"=> \$srcTargetXmlFullPath, + "ekbTargetXml:s"=> \$ekbTargetXmlFullPath, + "fapi2Header:s" => \$fapi2HeaderFullPath, + "help" => \$usage); + + +if( ($fullTargetXmlFullPath eq "") + || ($fullAttrXmlFullPath eq "") + || ($fapi2HeaderFullPath eq "") + || ($fullAttrXmlFullPath eq "") + || ($fullTargetXmlFullPath eq "") ) +{ + display_help(); + exit 1; +} +elsif ($usage) +{ + display_help(); + exit 0; +} + + +my %hwpfAttributes; + +my $xml = new XML::Simple (KeyAttr=>[]); +use Digest::MD5 qw(md5_hex); + +my $ekbTargetTypes = $xml->XMLin("$ekbTargetXmlFullPath", ForceArray=>['targetTypeExtension', 'attribute']); + +my $srcTargetTypes = $xml->XMLin("$srcTargetXmlFullPath", ForceArray=>['targetType', 'attribute']); + +#Read in HB attribute xml (attribute_types.xml) +my $allAttributes = $xml->XMLin($fullAttrXmlFullPath , + forcearray => ['attribute','hwpfToHbAttrMap','enumerationType','enumerator']); + +my $allTargetTypes = $xml->XMLin($fullTargetXmlFullPath , + forcearray => ['attribute']); + +#Create a list of all the HB attributes with a HWPF mapping +foreach my $attribute (@{$allAttributes->{attribute}}) +{ + if (exists $attribute->{hwpfToHbAttrMap} ) + { + push (@{%hwpfAttributes->{attribute}}, $attribute); + } +} + +#Get a list of all the function backed fapi2 attributes +my %funcBackedAttr = map { $_ => 1 } (getFuncionBackedAttrs($fapi2HeaderFullPath)); + +#new attributes that will be added +my @NewAttr; + +#Walk through target type extensions in target_types_ekb.xml +foreach my $Extension ( @{$ekbTargetTypes->{targetTypeExtension}} ) +{ + #this id is the name of the target type + my $id = $Extension->{id}; + #walk each attribute on the target + foreach my $attr ( @{$Extension->{attribute}} ) + { + #keep track of attribute's id + my $attribute_id = $attr->{id}; + #clear default each loop + my $default = ""; + #clear out success indicator each loop + my $attr_exists_already = 0; + + #Check if this attribute is function backed, if so, skip it + if(exists($funcBackedAttr{("ATTR_".$attribute_id)})) + { + next; + } + + #Make sure to apply defaults if we need + if(exists $attr->{default}) + { + $default = $attr->{default}; + } + + #Make sure we dont add attributes that already exist on the target + foreach my $targetType (@{$srcTargetTypes->{targetType}}) + { + if($targetType->{id} eq $id) + { + foreach my $targetAttr ( @{$targetType->{attribute}}) + { + if ($attribute_id eq $targetAttr->{id} ) + { + $attr_exists_already = 1; + #break when we find an attribute match + last; + } + } + #break once we find a target match + last; + } + } + + #if the attribute does not yet exist on the target, add it to list of attrs to add + if(!$attr_exists_already) + { + push @NewAttr, [ $id, $attribute_id, $default ]; + } + } +} + + +#add the new attributes to the correct targets +foreach my $targetType ( @{$srcTargetTypes->{targetType}}) +{ + my $id = $targetType->{id}; + for my $i (0 ..$#NewAttr) + { + my %attrHash; + $attrHash{'id'} = $NewAttr[$i][1]; + if($NewAttr[$i][2] ne "") + { + $attrHash{'default'} = $NewAttr[$i][2]; + } + if($id eq $NewAttr[$i][0]) + { + push (@{%$targetType->{attribute}}, \%attrHash); + } + } +} + +#Make sure we use the hostboot version of the name and not the Fapi2 version +#loop on each target type in target_types_src +foreach my $targetType (@{$srcTargetTypes->{targetType}}) +{ + #loop on each attribute for every target + foreach my $attribute (@{$targetType->{attribute}}) + { + #check if there is a hostboot mapping w/ a different name + foreach my $hbMappedAttr (@{%hwpfAttributes->{attribute}}) + { + my $fapiAttrId = $hbMappedAttr->{hwpfToHbAttrMap}[0]->{id}; + $fapiAttrId = substr $fapiAttrId , 5; + #if there is, make sure to update the id to match hostboot's xml + if($fapiAttrId eq $attribute->{id}) + { + $attribute->{id} = $hbMappedAttr->{id}; + } + } + } +} + +#Write hash out to a file +my $completeTargXml = $xml->XMLout(\%$srcTargetTypes, RootName => undef, NoAttr => 1 ); + +#use temporary file to be clean +my $tmp_fh = new File::Temp( UNLINK => 1 ); +print $tmp_fh $completeTargXml; + +#open target types full in append mode +open(my $targetXmlFullFH, '+>', $fullTargetXmlFullPath) || die; +#go back to the begining of the temp file handle +seek $tmp_fh, 0, 0 or die "Seek $tmp_fh failed: $!\n"; + +#add \n char between each targetType +foreach my $row (<$tmp_fh>) +{ + chomp $row; + print $targetXmlFullFH $row."\n"; + if(index($row, "</targetType>") != -1) + { + print $targetXmlFullFH "\n"; + } +} + +close $tmp_fh; +close $targetXmlFullFH; + + +sub display_help +{ + use File::Basename; + my $scriptname = basename($0); + print STDERR " +Description: + + This perl script merges together targetExtensions from target_types_ekb and targetType tags from + target_types_src. The trick is to avoid adding attributes on targets where the attribute already + exists. Also we don't want to add function backed attributes onto targets. The last step ensures + that we use the Hostboot name for the attribute, as hostboot can change the name in attribute_types.xml + and if a mapping exists there we want to use the hostboot name. + +Usage: + + $scriptname --help + + $scriptname --fullAttrXml + fullAttrXml is complete pathname of the attribute_types_full.xml file, + this file is used to make sure we use hostboot's version of the attribute + id when we add it to the target + + $scriptname --fullTargetXml + srcAttrXml is complete pathname of the attribute_types_full.xml file that + will be written to in this script + + $scriptname --srcTargetXml + srcTargetXml is complete pathname of the target_types_src.xml file + which should contain all targetType tags merged from various srcs + + + $scriptname --ekbTargetXml + ekbTargetXml is complete pathname of the target_types_ekb.xml file + which contains targetType extensions from EKB attribute generation + + $scriptname --fapi2Header=attrServiceHeader + attrServiceHeader is complete pathname of the attribute_service.H file from hostboot + +\n"; +}
\ No newline at end of file diff --git a/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml b/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml new file mode 100644 index 000000000..ae388e78a --- /dev/null +++ b/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml @@ -0,0 +1,599 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/targeting/common/xmltohb/hb_customized_attrs.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2017 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> + +<!-- ===================================================================== + Contains the definition of temporary FW defaults for FAPI attributes + needing a default. Each FAPI attribute should already be defined + elsewhere in an attribute XML file. + <attribute> + <id>...</id> + <default>...</default> + </attribute> + + These definitions should be removed and replaced with permanent + definitions elsewhere prior to shipping code that uses them. + + Examples: + <attribute> + <id>ATTR_NEW_FW_ATTR_DEF</id> + <default>5</default> + </attribute> + + <attribute> + <id>ATTR_NEW_FW_ATTR_WO_DEFAULT_DEF</id> + </attribute> + + <attribute> + <id>ATTR_NEW_FW_ATTR_ARRAY_DEF</id> + <default>9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20</default> + </attribute> + ================================================================= --> + + <!-- ===================================================================== + Start of customizations + ================================================================= --> + <attribute> + <id>ATTR_DUMMY_SCRATCH_PLAT_INIT_UINT8</id> + <default>5</default> + </attribute> + + <attribute> + <id>ATTR_IS_SIMULATION</id> + <default>0</default> + <writeable/> + </attribute> + + <attribute> + <id>ATTR_ISTEP_MODE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_CHIP_UNIT_POS</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FABRIC_GROUP_ID</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FABRIC_CHIP_ID</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_FREQ_CORE_FLOOR_MHZ</id> + <default>4800</default> + </attribute> + + <attribute> + <id>ATTR_FREQ_A_MHZ</id> + <default>0x1900</default> + </attribute> + + <attribute> + <id>ATTR_FREQ_O_MHZ</id> + <default>1611</default> + </attribute> + + <attribute> + <id>ATTR_OB0_PLL_BUCKET</id> + <default>1</default> + </attribute> + + <attribute> + <id>ATTR_OB1_PLL_BUCKET</id> + <default>1</default> + </attribute> + + <attribute> + <id>ATTR_OB2_PLL_BUCKET</id> + <default>1</default> + </attribute> + + <attribute> + <id>ATTR_OB3_PLL_BUCKET</id> + <default>1</default> + </attribute> + + <attribute> + <id>ATTR_FREQ_X_MHZ</id> + <default>2000</default> + <writeable/> + </attribute> + + <attribute> + <id>ATTR_MNFG_FLAGS</id> + <default>0x0000000000000000</default> + <writeable/> + </attribute> + + <attribute> + <id>ATTR_BOOT_FREQ_MHZ</id> + <default>2400</default> + </attribute> + + <attribute> + <id>ATTR_MSS_INTERLEAVE_ENABLE</id> + <default>0xAF</default> + <writeable/> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_SUPPORTED_FREQ</id> + <default>1866,2133,2400,2667</default> + </attribute> + + <attribute> + <id>ATTR_MEMVPD_POS</id> + <default>0xFF</default> + </attribute> + + <attribute> + <id>ATTR_DMI_REFCLOCK_SWIZZLE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT</id> + <default>0xffffe000000006a4,0,0,0,0,0,0,0,0,0</default> + </attribute> + + <attribute> + <id>ATTR_MEM_MIRROR_PLACEMENT_POLICY</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL</id> + <default>0x00002328</default> + </attribute> + + <attribute> + <id>ATTR_MSS_VDDR_OVERIDE_SPD</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_POWER_CONTROL_REQUESTED</id> + <default>OFF</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED</id> + <default>OFF</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_1x</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_2x</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_3x</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_4x</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_5x</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_6x</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_7x</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_8x</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_9x</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_Ax</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_Bx</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_MAX_ALLOWED_DIMM_FREQ</id> + <default>2400,2400,2400,2400,2400</default> + </attribute> + + <attribute> + <id>ATTR_VCS_I2C_BUSNUM</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_STOP5_DISABLE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_VCS_I2C_RAIL</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_FAPI_POS</id> + <default>0xFFFFFFFF</default> + </attribute> + + <attribute> + <id>ATTR_I2C_BUS_DIV_REF</id> + <default>0x0003</default> + </attribute> + + <attribute> + <id>ATTR_NEST_PLL_BUCKET</id> + <default>0x05</default> + </attribute> + + <attribute> + <id>ATTR_BOOT_FREQ_MULT</id> + <default>150</default> + </attribute> + + <attribute> + <id>ATTR_MB_BIT_RATE_DIVISOR_REFCLK</id> + <default>133</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FABRIC_SYSTEM_ID</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_SYSTEM_IPL_PHASE</id> + <default>0x01</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FABRIC_A_BUS_WIDTH</id> + <default>4_BYTE</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FABRIC_X_BUS_WIDTH</id> + <default>4_BYTE</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FABRIC_CCSM_MODE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_OPTICS_CONFIG_MODE</id> + <default>NV</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FABRIC_SMP_OPTICS_MODE</id> + <default>OPTICS_IS_X_BUS</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FABRIC_CAPI_MODE</id> + <default>OFF</default> + </attribute> + + <attribute> + <id>ATTR_PROC_PCIE_PCS_RX_PK_INIT</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_PROC_PCIE_PCS_RX_INIT_GAIN</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_PROC_PCIE_PCS_RX_SIGDET_LVL</id> + <default>0x0B</default> + </attribute> + + <attribute> + <id>ATTR_PROC_PCIE_PCS_RX_ROT_RST_FW</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_IO_XBUS_TX_FFE_PRECURSOR</id> + <default>6</default> + </attribute> + + <attribute> + <id>ATTR_POUNDV_BUCKET_NUM_OVERRIDE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_POUNDV_BUCKET_NUM</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_DUMP_STOP_INFO_SUPPRESS_ERROR_TRACE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_DUMP_STOP_INFO_ENABLE_ERRORLOG</id> + <default>1</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS</id> + <default>0x00000200</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_TEMP_REFRESH_RANGE</id> + <default>1</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_PREFETCH_ENABLE</id> + <default>1</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FSP_BAR_ENABLE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_PROC_PSI_BRIDGE_BAR_ENABLE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FSP_BAR_SIZE</id> + <default>0xFFFFFC00FFFFFFFF</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FSP_BAR_BASE_ADDR_OFFSET</id> + <default>0x0000030100000000</default> + </attribute> + + <attribute> + <id>ATTR_PROC_FSP_MMIO_MASK_SIZE</id> + <default>0x0010000000000000</default> + </attribute> + + <attribute> + <id>ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET</id> + <default>0x0000030203000000</default> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU_PHY0_BAR_ENABLE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET</id> + <default>0x0000030201200000</default> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU_PHY1_BAR_ENABLE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET</id> + <default>0x0000030201400000</default> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id> + <default>0x0000030200000000</default> + </attribute> + + <attribute> + <id>ATTR_PROC_NX_RNG_BAR_ENABLE</id> + <default>0</default> + </attribute> + + <attribute> + <id>ATTR_PROC_NX_RNG_BAR_BASE_ADDR_OFFSET</id> + <default>0x00000302031D0000</default> + </attribute> + + <attribute> + <id>ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4</id> + <default>0x000006A4</default> + </attribute> + + <attribute> + <id>ATTR_SBE_IMAGE_MINIMUM_VALID_ECS</id> + <default>2</default> + </attribute> + + <attribute> + <id>ATTR_SBE_SYS_CONFIG</id> + <default>0x0</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_PWR_INTERCEPT</id> + <default>0xffffe00002CC03AE,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0</default> + </attribute> + + <attribute> + <id>ATTR_MSS_MRW_PWR_SLOPE</id> + <default>0xffffe00003FD0546,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0</default> + </attribute> + + <attribute> + <id>ATTR_MAX_SBE_SEEPROM_SIZE</id> + <default>0x40000</default> + </attribute> + + <attribute> + <id>ATTR_SYSTEM_RESCLK_DISABLE</id> + <default>0x00</default> + <writeable/> + </attribute> + + <attribute> + <id>ATTR_BACKUP_SEEPROM_SELECT</id> + <writeable/> + </attribute> + + <attribute> + <id>I2C_BUS_DIV_REF</id> + <default>0x0003</default> + <writeable/> + </attribute> + + <attribute> + <id>ATTR_ISDIMM_MBVPD_INDEX</id> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_EFF_FABRIC_GROUP_ID</id> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_EFF_FABRIC_CHIP_ID</id> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_MEMVPD_POS</id> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_EI_BUS_TX_LANE_INVERT</id> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_DMI_REFCLOCK_SWIZZLE</id> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP</id> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_FAPI_POS</id> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_DEVICE_ID</id> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_PCIE_IOP_SWAP</id> + <no_export/> + </attribute> +<!-- ===================================================================== + End of customizations definitions + ================================================================= --> +</attributes>
\ No newline at end of file diff --git a/src/usr/targeting/common/xmltohb/remove_hb_fapi_maps.pl b/src/usr/targeting/common/xmltohb/remove_hb_fapi_maps.pl new file mode 100755 index 000000000..5f93270d8 --- /dev/null +++ b/src/usr/targeting/common/xmltohb/remove_hb_fapi_maps.pl @@ -0,0 +1,222 @@ +#!/usr/bin/perl +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/targeting/common/xmltohb/remove_hb_fapi_maps.pl $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2017 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# +# +# Usage: +# +# handle_fapi_attr_mapping --spAttrXml=attribute_types_sp.xml +# --spTargXml=target_types_sp.xml +# --hbAttrXml=attribute_types_hb.xml + +# +# Purpose: +# +# The FSP side of targeting image building doesn't consume the attribute_types_hb.xml until +# much later in the build process. Our previous scripts aren't smart enough to not add in +# EKB attributes which are already mapped in the attribute_types_hb.xml so when we get to +# the step on the FSP side where we pull in these attributes we hit a fail. This script +# walks through the target_types_sp and attribute_types_sp xmls and removes any attributes +# that have maps defined in attribute_types_hb.xml +# + +use strict; + +use Getopt::Long; +use XML::Simple; +use Text::Wrap; +use Data::Dumper; +use POSIX; +use Env; +use XML::LibXML; +use File::Temp qw(tempfile); + + +$XML::Simple::PREFERRED_PARSER = 'XML::Parser'; + +my $spAttrXml = ""; +my $spTargXml = ""; +my $hbAttrXml = ""; +my $usage = 0; + +GetOptions("spAttrXml:s" => \$spAttrXml, + "spTargXml:s" => \$spTargXml, + "hbAttrXml:s" => \$hbAttrXml, + "help" => \$usage); + + +if( ($spAttrXml eq "") + || ($spTargXml eq "") + || ($hbAttrXml eq "") ) +{ + display_help(); + exit 1; +} +elsif ($usage) +{ + display_help(); + exit 0; +} + +my @hbMappedAttrs; +my @fixedSpAttrs; +my @fixedSpTargetAttr; + +#use the XML::Simple tool to convert the xml files into hashmaps +my $xml = new XML::Simple (KeyAttr=>[]); +use Digest::MD5 qw(md5_hex); + +#read in attribute_types_sp.xml and store in hashmap +my $spAttributes = $xml->XMLin($spAttrXml , + forcearray => ['attribute','hwpfToHbAttrMap','enumerationType','enumerator']); + +#Read in HB attribute xml (attribute_types.xml) +my $hbAttributes = $xml->XMLin($hbAttrXml , + forcearray => ['attribute','hwpfToHbAttrMap','enumerationType','enumerator']); + +#read in target_types_sp.xml and store in hashmap +my $spTargets = $xml->XMLin($spTargXml , + forcearray => ['attribute']); + +#Create a list of all the HB-only attributes(attribute_types_hb) with a HWPF mapping +foreach my $attribute (@{$hbAttributes->{attribute}}) +{ + if (exists $attribute->{hwpfToHbAttrMap} ) + { + push (@hbMappedAttrs, $attribute->{hwpfToHbAttrMap}[0]->{id}); + } +} + +#keep two list of attributes, one list to keep, one to remove +my @spAttributeToKeep; +my @spAttributeToRemove; + +#The attribute_types_sp xml does not include HB srcs ,but we dont want to add EKB +#attribute that are mapped in attribute_types_hb xml. We need to loop through +#all of the attributes and make sure we are not overwriting an HB-only attr +foreach my $spAttribute (@{$spAttributes->{attribute}}) +{ + my $foundMatch = 0; + #First check if it is an EKB attribute + if(exists $spAttribute->{hwpfToHbAttrMap} ) + { + #if it is an EKB attr, check if it has a mapping in Hb-only xml + foreach my $id (@hbMappedAttrs) + { + if($id eq $spAttribute->{hwpfToHbAttrMap}[0]->{id}) + { + #if it already has a mapping, add to list to remove + $foundMatch = 1; + push (@spAttributeToRemove, $spAttribute->{id}) + } + } + } + #if no hb-only mapping is found , add to list to keep. + if (!$foundMatch) + { + push (@spAttributeToKeep, $spAttribute); + } +} + +#Remove the attributes from the spAttribute hashmap and +#replace w/ list of attrs to keep +undef @{$spAttributes->{attribute}}; +@{$spAttributes->{attribute}} = @spAttributeToKeep; + + +#loop on all of the target types defined in target_types_sp +foreach my $spTarget (@{$spTargets->{targetType}}) +{ + #clear local attribute list each loop + undef @fixedSpTargetAttr; + #loop on each attribute of the target + foreach my $targAttr (@{$spTarget->{attribute}}) + { + my $foundMatch = 0; + #check if any attributes are on the list to be removed + foreach my $attrToRemoveId (@spAttributeToRemove) + { + if($attrToRemoveId eq $targAttr->{id}) + { + $foundMatch = 1; + print STDOUT "removing ".$attrToRemoveId."\n"; + } + } + if (!$foundMatch) + { + push (@fixedSpTargetAttr, $targAttr); + } + } + + #update w/ new attribute list + undef @{$spTarget->{attribute}}; + @{$spTarget->{attribute}} = @fixedSpTargetAttr; +} + +#need to write contents of both targ and attr xml hashes becuase both were modified +my $finalTargXmlOutput = $xml->XMLout(\%$spTargets, RootName => 'attributes', NoAttr => 1 ); +my $finalAttrXmlOutput = $xml->XMLout(\%$spAttributes, RootName => 'attributes', NoAttr => 1 ); + +open(my $final_attr_output_fh_temp_w, '>', $spAttrXml ) || die; +print $final_attr_output_fh_temp_w $finalAttrXmlOutput; +close $final_attr_output_fh_temp_w; + +open(my $final_targ_output_fh_temp_w, '>', $spTargXml ) || die; +print $final_targ_output_fh_temp_w $finalTargXmlOutput; +close $final_targ_output_fh_temp_w; + + sub display_help +{ + use File::Basename; + my $scriptname = basename($0); + print STDERR " +Description: + + The FSP side of targeting image building doesn't consume the attribute_types_hb.xml until + much later in the build process. Our previous scripts aren't smart enough to not add in + EKB attributes which are already mapped in the attribute_types_hb.xml so when we get to + the step on the FSP side where we pull in these attributes we hit a fail. This script + walks through the target_types_sp and attribute_types_sp xmls and removes any attributes + that have maps defined in attribute_types_hb.xml + +Usage: + + $scriptname --help + + $scriptname --spAttrXml + spAttrXml is complete pathname of the attribute_types_sp.xml file, + + $scriptname --spTargXml + spTargXml is complete pathname of the target_types_sp.xml file that + + $scriptname --hbAttrXml + hbAttrXml is complete pathname of the attr_types_hb.xml file + + +\n"; +} + + diff --git a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml index 69fd956a5..45270bc65 100644 --- a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml @@ -180,6 +180,14 @@ <id>MAX_PROC_CHIPS_PER_NODE</id> <default>2</default> </attribute> + <attribute> + <id>MAX_ALLOWED_DIMM_FREQ</id> + <default>2400,2400,2400,2400,2400</default> + </attribute> + <attribute> + <id>MSS_INTERLEAVE_ENABLE</id> + <default>0xAF</default> + </attribute> </targetInstance> <!-- System node 0 --> @@ -3272,7 +3280,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -3309,7 +3317,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -3346,7 +3354,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -3383,7 +3391,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -3420,7 +3428,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -3457,7 +3465,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -8677,7 +8685,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -8714,7 +8722,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -8751,7 +8759,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -8788,7 +8796,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -8825,7 +8833,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> @@ -8862,7 +8870,7 @@ </attribute> <attribute> <id>OPTICS_CONFIG_MODE</id> - <default>NVLINK</default> + <default>NV</default> </attribute> <attribute> <id>CHIP_UNIT</id> diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index bb8feb3da..5aca00eef 100755 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -23,1363 +23,2349 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> - <attributes> -<!-- ===================================================================== - HOST BOOT TARGETS - Contains the definition of the different types of targets - ================================================================= --> - <targetType> - <id>base</id> - <attribute><id>CLASS</id></attribute> - <attribute><id>TYPE</id></attribute> - <attribute><id>MODEL</id></attribute> - <attribute><id>HUID</id></attribute> - <attribute><id>PHYS_PATH</id></attribute> - <attribute><id>AFFINITY_PATH</id></attribute> - <attribute><id>PRIMARY_CAPABILITIES</id></attribute> - <attribute><id>HWAS_STATE</id></attribute> - <attribute><id>HWAS_STATE_CHANGED_FLAG</id></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id></attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>0</default></attribute> - <attribute><id>RESOURCE_IS_CRITICAL</id><default>0</default></attribute> - <attribute><id>ORDINAL_ID</id></attribute> - <attribute><id>FAPI_POS</id></attribute> - <attribute><id>FAPI_NAME</id></attribute> - <attribute><id>PNOR_FLASH_WORKAROUNDS</id></attribute> + <id>base</id> + <attribute> + <id>CLASS</id> + </attribute> + <attribute> + <id>TYPE</id> + </attribute> + <attribute> + <id>MODEL</id> + </attribute> + <attribute> + <id>HUID</id> + </attribute> + <attribute> + <id>PHYS_PATH</id> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + </attribute> + <attribute> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute> + <id>HWAS_STATE</id> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_FLAG</id> + </attribute> + <attribute> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default>0</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0</default> + <id>RESOURCE_IS_CRITICAL</id> + </attribute> + <attribute> + <id>ORDINAL_ID</id> + </attribute> + <attribute> + <id>FAPI_POS</id> + </attribute> + <attribute> + <id>FAPI_NAME</id> + </attribute> + <attribute> + <id>PNOR_FLASH_WORKAROUNDS</id> + </attribute> </targetType> <targetType> - <id>chip</id> - <parent>base</parent> - <attribute> - <id>CLASS</id> - <default>CHIP</default> - </attribute> - <attribute> - <id>POSITION</id> - </attribute> - <attribute> - <id>FSI_MASTER_CHIP</id> - </attribute> - <attribute> - <id>ALTFSI_MASTER_CHIP</id> - </attribute> - <attribute> - <id>FSI_MASTER_TYPE</id> - <default>NO_MASTER</default> - </attribute> - <attribute> - <id>MRU_ID</id> - </attribute> - <attribute> - <id>FSI_MASTER_PORT</id> - </attribute> - <attribute> - <id>ALTFSI_MASTER_PORT</id> - </attribute> - <attribute> - <id>FSI_SLAVE_CASCADE</id> - </attribute> - <attribute> - <id>FSI_OPTION_FLAGS</id> - </attribute> - <attribute> - <id>EC</id> - </attribute> - <attribute> - <id>CHIP_ID</id> - </attribute> - <attribute> - <id>FRU_ID</id> - </attribute> - <attribute> - <id>HDAT_EC</id> - </attribute> - <attribute> - <id>MINI_EC</id> - </attribute> + <id>chip</id> + <parent>base</parent> + <attribute> + <default>CHIP</default> + <id>CLASS</id> + </attribute> + <attribute> + <id>POSITION</id> + </attribute> + <attribute> + <id>FSI_MASTER_CHIP</id> + </attribute> + <attribute> + <id>ALTFSI_MASTER_CHIP</id> + </attribute> + <attribute> + <default>NO_MASTER</default> + <id>FSI_MASTER_TYPE</id> + </attribute> + <attribute> + <id>MRU_ID</id> + </attribute> + <attribute> + <id>FSI_MASTER_PORT</id> + </attribute> + <attribute> + <id>ALTFSI_MASTER_PORT</id> + </attribute> + <attribute> + <id>FSI_SLAVE_CASCADE</id> + </attribute> + <attribute> + <id>FSI_OPTION_FLAGS</id> + </attribute> + <attribute> + <id>EC</id> + </attribute> + <attribute> + <id>CHIP_ID</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> + <attribute> + <id>HDAT_EC</id> + </attribute> + <attribute> + <id>MINI_EC</id> + </attribute> </targetType> <targetType> - <id>chip-processor</id> - <parent>chip</parent> - <attribute> - <id>TYPE</id> - <default>PROC</default> - </attribute> - <attribute> - <id>PROC_MASTER_TYPE</id> - </attribute> - <attribute> - <id>PRIMARY_CAPABILITIES</id> - <default> - <field><id>supportsFsiScom</id><value>1</value></field> - <field><id>supportsXscom</id><value>1</value></field> - <field><id>supportsInbandScom</id><value>0</value></field> - <field><id>reserved</id><value>0</value></field> - </default> - </attribute> - <attribute> - <id>SCOM_SWITCHES</id> - </attribute> - <attribute> - <!-- Processor chips have SCOM accessible FSI GP regs --> - <id>FSI_GP_REG_SCOM_ACCESS</id> - <default>1</default> - </attribute> - <attribute><id>FABRIC_GROUP_ID</id></attribute> - <attribute><id>PROC_EFF_FABRIC_GROUP_ID</id></attribute> - <attribute><id>FABRIC_CHIP_ID</id></attribute> - <attribute><id>PROC_EFF_FABRIC_CHIP_ID</id></attribute> - <attribute> - <!-- Processor chips have an SBE --> - <id>CHIP_HAS_SBE</id> - <default>1</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!-- GARD --> - </attribute> - - <attribute><id>VPD_REC_NUM</id></attribute> - <!-- New attributes for mss/proc_setup_bars --> - <!-- proc_setup_bars_memory_attributes.xml --> - <attribute><id>MSS_MEM_MC_IN_GROUP</id></attribute> - <attribute><id>PROC_MEM_BASES</id></attribute> - <attribute><id>PROC_MEM_SIZES</id></attribute> - <attribute><id>PROC_MIRROR_BASES</id></attribute> - <attribute><id>PROC_MIRROR_SIZES</id></attribute> - <!-- proc_setup_bars_l3_attributes.xml --> - <attribute><id>PROC_L3_BAR1_REG</id></attribute> - <attribute><id>PROC_L3_BAR2_REG</id></attribute> - <attribute><id>PROC_L3_BAR_GROUP_MASK_REG</id></attribute> - <!-- proc_fab_smp_fabric_attributes.xml --> - <attribute><id>PROC_PCIE_NOT_F_LINK</id></attribute> - <attribute><id>MSS_MCS_GROUP_32</id></attribute> - <attribute><id>MSS_MEM_IPL_COMPLETE</id></attribute> - <!-- Start pm_plat_attributes.xml --> - <attribute><id>PM_UNDERVOLTING_FRQ_MINIMUM</id></attribute> - <attribute><id>PM_UNDERVOLTING_FREQ_MAXIMUM</id></attribute> - <attribute><id>PM_SPIVID_PORT_ENABLE</id></attribute> - <attribute><id>PM_APSS_CHIP_SELECT</id></attribute> - <attribute><id>PM_PBAX_NODEID</id></attribute> - <attribute><id>PBAX_GROUPID</id></attribute> - <attribute><id>PBAX_CHIPID</id></attribute> - <attribute><id>PBAX_BRDCST_ID_VECTOR</id></attribute> - <attribute><id>PM_SLEEP_ENTRY</id></attribute> - <attribute><id>PM_SLEEP_EXIT</id></attribute> - <attribute><id>PM_SLEEP_TYPE</id></attribute> - <attribute><id>PM_WINKLE_ENTRY</id></attribute> - <attribute><id>PM_WINKLE_EXIT</id></attribute> - <attribute><id>PM_WINKLE_TYPE</id></attribute> - <!-- End pm_plat_attributes.xml --> - <!-- Start pm_hwp_attributes.xml --> - <attribute><id>PM_AISS_TIMEOUT</id></attribute> - <attribute><id>PM_EXTERNAL_VRM_STEPDELAY_RANGE</id></attribute> - <attribute><id>PM_EXTERNAL_VRM_STEPDELAY_VALUE</id></attribute> - <attribute><id>PM_IVRMS_ENABLED</id></attribute> - <attribute><id>PM_OCC_HEARTBEAT_TIME</id></attribute> - <attribute><id>PM_PBAX_RCV_RESERV_TIMEOUT</id></attribute> - <attribute><id>PM_PBAX_SND_RESERV_TIMEOUT</id></attribute> - <attribute><id>PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE</id></attribute> - <attribute><id>PM_PBAX_SND_RETRY_THRESHOLD</id></attribute> - <attribute><id>PM_PFET_POWERDOWN_CORE_DELAY0</id></attribute> - <attribute><id>PM_PFET_POWERDOWN_CORE_DELAY0_VALUE</id></attribute> - <attribute><id>PM_PFET_POWERDOWN_CORE_DELAY1</id></attribute> - <attribute><id>PM_PFET_POWERDOWN_CORE_DELAY1_VALUE</id></attribute> - <attribute><id>PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT</id></attribute> - <attribute><id>PM_PFET_POWERDOWN_ECO_DELAY0</id></attribute> - <attribute><id>PM_PFET_POWERDOWN_ECO_DELAY0_VALUE</id></attribute> - <attribute><id>PM_PFET_POWERDOWN_ECO_DELAY1</id></attribute> - <attribute><id>PM_PFET_POWERDOWN_ECO_DELAY1_VALUE</id></attribute> - <attribute><id>PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT</id></attribute> - <attribute><id>PM_PFET_POWERUP_CORE_DELAY0</id></attribute> - <attribute><id>PM_PFET_POWERUP_CORE_DELAY0_VALUE</id></attribute> - <attribute><id>PM_PFET_POWERUP_CORE_DELAY1</id></attribute> - <attribute><id>PM_PFET_POWERUP_CORE_DELAY1_VALUE</id></attribute> - <attribute><id>PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT</id></attribute> - <attribute><id>PM_PFET_POWERUP_ECO_DELAY0</id></attribute> - <attribute><id>PM_PFET_POWERUP_ECO_DELAY0_VALUE</id></attribute> - <attribute><id>PM_PFET_POWERUP_ECO_DELAY1</id></attribute> - <attribute><id>PM_PFET_POWERUP_ECO_DELAY1_VALUE</id></attribute> - <attribute><id>PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT</id></attribute> - <attribute><id>PM_PMC_HANGPULSE_DIVIDER</id></attribute> - <attribute><id>PM_POWER_PROXY_TRACE_TIMER</id></attribute> - <attribute><id>PM_PPT_TIMER_MATCH_VALUE</id></attribute> - <attribute><id>PM_PPT_TIMER_TICK</id></attribute> - <attribute><id>PM_PSTATE0_FREQUENCY</id></attribute> - <attribute><id>PM_PSTATE_STEPSIZE</id></attribute> - <attribute><id>PM_PVSAFE_PSTATE</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_ENABLE</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_FULL_CSB_PSTATE</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_HFRHIGH_PSTATE</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_HFRLOW_PSTATE</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_LFRLOW_PSTATE</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_LFRUPPER_PSTATE</id></attribute> - <attribute><id>PM_SAFE_PSTATE</id></attribute> - <attribute><id>PM_SLEEP_WINKLE_REQUEST_TIMEOUT</id></attribute> - <attribute><id>PM_SPIPSS_CLOCK_DIVIDER</id></attribute> - <attribute><id>PM_SPIPSS_CLOCK_PHASE</id></attribute> - <attribute><id>PM_SPIPSS_CLOCK_POLARITY</id></attribute> - <attribute><id>PM_SPIPSS_FRAME_SIZE</id></attribute> - <attribute><id>PM_SPIPSS_INTER_FRAME_DELAY</id></attribute> - <attribute><id>PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id></attribute> - <attribute><id>PM_SPIPSS_IN_COUNT</id></attribute> - <attribute><id>PM_SPIPSS_IN_DELAY</id></attribute> - <attribute><id>PM_SPIPSS_OUT_COUNT</id></attribute> - <attribute><id>PM_SPIVID_CLOCK_DIVIDER</id></attribute> - <attribute><id>PM_SPIVID_CLOCK_PHASE</id></attribute> - <attribute><id>PM_SPIVID_CLOCK_POLARITY</id></attribute> - <attribute><id>PM_SPIVID_CRC_CHECK_ENABLE</id></attribute> - <attribute><id>PM_SPIVID_CRC_GEN_ENABLE</id></attribute> - <attribute><id>PM_SPIVID_CRC_POLYNOMIAL_ENABLES</id></attribute> - <attribute><id>PM_SPIVID_FRAME_SIZE</id></attribute> - <attribute><id>PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS</id></attribute> - <attribute><id>PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE</id></attribute> - <attribute><id>PM_SPIVID_INTER_RETRY_DELAY</id></attribute> - <attribute><id>PM_SPIVID_INTER_RETRY_DELAY_VALUE</id></attribute> - <attribute><id>PM_SPIVID_IN_DELAY_FRAME1</id></attribute> - <attribute><id>PM_SPIVID_IN_DELAY_FRAME2</id></attribute> - <attribute><id>PM_SPIVID_MAJORITY_VOTE_ENABLE</id></attribute> - <attribute><id>PM_SPIVID_MAX_RETRIES</id></attribute> - <attribute><id>PROC_DPLL_DIVIDER</id></attribute> - <attribute><id>PSTATES_ENABLED</id></attribute> - <attribute><id>RESCLK_ENABLED</id></attribute> - <attribute><id>VDM_ENABLED</id></attribute> - <attribute><id>IVRM_ENABLED</id></attribute> - <attribute><id>WOF_ENABLED</id></attribute> - <!-- End pm_hwp_attributes.xml --> - <attribute><id>SKIP_HW_VREF_CAL</id></attribute> - <attribute><id>SKIP_RD_VREF_VREFSENSE_OVERRIDE</id></attribute> - <!-- Begin poreve_memory_attributes.xml --> - <attribute><id>SBE_SEEPROM_I2C_ADDRESS_BYTES</id></attribute> - <attribute><id>SBE_SEEPROM_I2C_DEVICE_ADDRESS</id></attribute> - <attribute><id>SBE_SEEPROM_I2C_PORT</id></attribute> - <attribute><id>PNOR_I2C_ADDRESS_BYTES</id></attribute> - <!-- End Supporting poreve_memory_attributes.xml --> -<!-- TODO RTC 82688. This next attribute moves to hostboot only - with this story --> - <attribute><id>PROC_SECURITY_SETUP_VECTOR</id></attribute> - - <attribute><id>PROC_MIRROR_BASES_ACK</id></attribute> - <attribute><id>PROC_MIRROR_SIZES_ACK</id></attribute> - <attribute><id>PROC_MEM_BASES_ACK</id></attribute> - <attribute><id>PROC_MEM_SIZES_ACK</id></attribute> - <attribute><id>CPM_INFLECTION_POINTS</id></attribute> - <attribute><id>PROC_SBE_MASTER_CHIP</id></attribute> - <attribute><id>BACKUP_SEEPROM_SELECT</id></attribute> - <attribute><id>PROC_SELECT_BOOT_SEEPROM_IMAGE</id></attribute> - <attribute><id>TOD_ROLE</id></attribute> - <attribute><id>PM_OCC_LFIR_MASK</id></attribute> - <attribute><id>PM_PBA_FIR_MASK</id></attribute> - <attribute><id>PM_PMC_LFIR_MASK</id></attribute> - <attribute><id>PM_FIRINIT_DONE_ONCE_FLAG</id></attribute> - <attribute> - <id>I2C_SWITCHES</id> - <default> - <field><id>useFsiI2C</id><value>1</value></field> - <field><id>useHostI2C</id><value>0</value></field> - <field><id>reserved</id><value>0</value></field> - </default> - </attribute> - <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute> - <attribute><id>HOT_PLUG_POWER_CONTROLLER_INFO</id></attribute> - <attribute><id>PROC_R_LOADLINE_VDD_UOHM</id></attribute> - <attribute><id>PROC_R_DISTLOSS_VDD_UOHM</id></attribute> - <attribute><id>PROC_VRM_VOFFSET_VDD_UV</id></attribute> - <attribute><id>PROC_R_LOADLINE_VDN_UOHM</id></attribute> - <attribute><id>PROC_R_DISTLOSS_VDN_UOHM</id></attribute> - <attribute><id>PROC_VRM_VOFFSET_VDN_UV</id></attribute> - <attribute><id>PROC_R_LOADLINE_VCS_UOHM</id></attribute> - <attribute><id>PROC_R_DISTLOSS_VCS_UOHM</id></attribute> - <attribute><id>PROC_VRM_VOFFSET_VCS_UV</id></attribute> - <attribute><id>TOD_CPU_DATA</id></attribute> - <attribute><id>ICACHE_ASSOC_SETS</id></attribute> - <attribute><id>ICACHE_SIZE</id></attribute> - <attribute><id>ICACHE_LINE_SIZE</id></attribute> - <attribute><id>ICACHE_BLOCK_SIZE</id></attribute> - <attribute><id>DCACHE_LINE_SIZE</id></attribute> - <attribute><id>DCACHE_ASSOC_SETS</id></attribute> - <attribute><id>DATA_CACHE_SIZE</id></attribute> - <attribute><id>DATA_CACHE_LINE_SIZE</id></attribute> - <attribute><id>L2_CACHE_LINE_SIZE</id></attribute> - <attribute><id>L2_CACHE_SIZE</id></attribute> - <attribute><id>L2_CACHE_ASSOC_SETS</id></attribute> - <attribute><id>L3_CACHE_LINE_SIZE</id></attribute> - <attribute><id>L3_CACHE_SIZE</id></attribute> - <attribute><id>TLB_DATA_ENTRIES</id></attribute> - <attribute><id>TLB_INSTR_ENTRIES</id></attribute> - <attribute><id>TLB_DATA_ASSOC_SETS</id></attribute> - <attribute><id>TLB_INSTR_ASSOC_SETS</id></attribute> - <attribute><id>TLB_RESERVE_SIZE</id></attribute> - <attribute><id>TIME_BASE</id></attribute> - <attribute><id>CPU_ATTR</id></attribute> - <attribute><id>ADU_XSCOM_BAR_BASE_ADDR</id></attribute> - <attribute><id>PROC_OCC_SANDBOX_SIZE</id></attribute> - <attribute><id>PROC_FABRIC_SYSTEM_MASTER_CHIP</id></attribute> - <attribute><id>PROC_FABRIC_GROUP_MASTER_CHIP</id></attribute> - <attribute><id>PROC_FABRIC_A_ATTACHED_CHIP_CNFG</id></attribute> - <attribute><id>PROC_FABRIC_X_ATTACHED_CHIP_CNFG</id></attribute> - <attribute><id>PROC_FABRIC_A_ATTACHED_CHIP_ID</id></attribute> - <attribute><id>PROC_FABRIC_X_ATTACHED_CHIP_ID</id></attribute> - <attribute><id>PROC_FABRIC_A_ADDR_DIS</id></attribute> - <attribute><id>PROC_FABRIC_X_ADDR_DIS</id></attribute> - <attribute><id>UNIT_TEST_MCA_MEMORY_SIZES</id></attribute> - <attribute><id>PROC_FABRIC_OPTICS_CONFIG_MODE</id></attribute> - <attribute><id>PROC_FABRIC_A_AGGREGATE</id></attribute> - <attribute><id>PROC_FABRIC_X_AGGREGATE</id></attribute> - <attribute><id>XIVE_HW_RESET</id></attribute> - <attribute><id>DISABLE_I2C_ENGINE2_PORT0_DIAG_MODE</id></attribute> - <attribute><id>NDL_MESHCTRL_SETUP</id></attribute> - <attribute><id>PREVIOUS_SBE_ERROR</id></attribute> -</targetType> - -<targetType> - <id>unit</id> - <parent>base</parent> - <attribute> - <id>CLASS</id> - <default>UNIT</default> - </attribute> - <attribute> - <id>MRU_ID</id> - </attribute> - <attribute> - <id>PRIMARY_CAPABILITIES</id> - <default> - <field><id>supportsFsiScom</id><value>1</value></field> - <field><id>supportsXscom</id><value>1</value></field> - <field><id>supportsInbandScom</id><value>0</value></field> - <field><id>reserved</id><value>0</value></field> - </default> - </attribute> - <attribute> - <id>CHIP_UNIT</id> - <default>0</default> - </attribute> - <attribute> - <id>CHIPLET_ID</id> - </attribute> - <attribute><id>REL_POS</id></attribute> + <id>chip-processor</id> + <parent>chip</parent> + <attribute> + <default>PROC</default> + <id>TYPE</id> + </attribute> + <attribute> + <id>PROC_MASTER_TYPE</id> + </attribute> + <attribute> + <default> + <field> + <id>supportsFsiScom</id> + <value>1</value> + </field> + <field> + <id>supportsXscom</id> + <value>1</value> + </field> + <field> + <id>supportsInbandScom</id> + <value>0</value> + </field> + <field> + <id>reserved</id> + <value>0</value> + </field> + </default> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute><id>FABRIC_GROUP_ID</id></attribute> + <attribute><id>FABRIC_CHIP_ID</id></attribute> + <attribute> + <id>SCOM_SWITCHES</id> + </attribute> + <attribute> + <id>PROC_EFF_FABRIC_GROUP_ID</id> + </attribute> + <attribute> + <id>PROC_EFF_FABRIC_CHIP_ID</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000001</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + </attribute> + <attribute> + <id>MSS_MEM_MC_IN_GROUP</id> + </attribute> + <attribute> + <id>PROC_MEM_BASES</id> + </attribute> + <attribute> + <id>PROC_MEM_SIZES</id> + </attribute> + <attribute> + <id>PROC_MIRROR_BASES</id> + </attribute> + <attribute> + <id>PROC_MIRROR_SIZES</id> + </attribute> + <attribute> + <id>MSS_MCS_GROUP_32</id> + </attribute> + <attribute> + <id>MSS_MEM_IPL_COMPLETE</id> + </attribute> + <attribute> + <id>PM_APSS_CHIP_SELECT</id> + </attribute> + <attribute> + <id>PBAX_GROUPID</id> + </attribute> + <attribute> + <id>PBAX_CHIPID</id> + </attribute> + <attribute> + <id>PBAX_BRDCST_ID_VECTOR</id> + </attribute> + <attribute> + <id>PM_SPIPSS_CLOCK_DIVIDER</id> + </attribute> + <attribute> + <id>PM_SPIPSS_CLOCK_PHASE</id> + </attribute> + <attribute> + <id>PM_SPIPSS_CLOCK_POLARITY</id> + </attribute> + <attribute> + <id>PM_SPIPSS_FRAME_SIZE</id> + </attribute> + <attribute> + <id>PM_SPIPSS_INTER_FRAME_DELAY_SETTING</id> + </attribute> + <attribute> + <id>PM_SPIPSS_IN_DELAY</id> + </attribute> + <attribute> + <id>PROC_DPLL_DIVIDER</id> + </attribute> + <attribute> + <id>SKIP_HW_VREF_CAL</id> + </attribute> + <attribute> + <id>SKIP_RD_VREF_VREFSENSE_OVERRIDE</id> + </attribute> + <attribute> + <id>SBE_SEEPROM_I2C_DEVICE_ADDRESS</id> + </attribute> + <attribute><id>HOT_PLUG_POWER_CONTROLLER_INFO</id></attribute> + <attribute><id>PM_UNDERVOLTING_FRQ_MINIMUM</id></attribute> + <attribute><id>PM_UNDERVOLTING_FREQ_MAXIMUM</id></attribute> + <attribute><id>PM_SPIVID_PORT_ENABLE</id></attribute> + <attribute><id>PM_PBAX_NODEID</id></attribute> + <attribute><id>PM_SLEEP_ENTRY</id></attribute> + <attribute><id>PM_SLEEP_EXIT</id></attribute> + <attribute><id>PM_SLEEP_TYPE</id></attribute> + <attribute><id>PM_WINKLE_ENTRY</id></attribute> + <attribute><id>PM_WINKLE_EXIT</id></attribute> + <attribute><id>PM_WINKLE_TYPE</id></attribute> + <attribute> + <id>SBE_SEEPROM_I2C_PORT</id> + </attribute> + <attribute> + <id>PROC_MIRROR_BASES_ACK</id> + </attribute> + <attribute> + <id>PROC_MIRROR_SIZES_ACK</id> + </attribute> + <attribute> + <id>PROC_MEM_BASES_ACK</id> + </attribute> + <attribute> + <id>PROC_MEM_SIZES_ACK</id> + </attribute> + <attribute> + <id>PROC_SBE_MASTER_CHIP</id> + </attribute> + <attribute> + <id>BACKUP_SEEPROM_SELECT</id> + </attribute> + <attribute> + <id>TOD_ROLE</id> + </attribute> + <attribute> + <id>PM_FIRINIT_DONE_ONCE_FLAG</id> + </attribute> + <attribute> + <default> + <field> + <id>useFsiI2C</id> + <value>1</value> + </field> + <field> + <id>useHostI2C</id> + <value>0</value> + </field> + <field> + <id>reserved</id> + <value>0</value> + </field> + </default> + <id>I2C_SWITCHES</id> + </attribute> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>PROC_R_LOADLINE_VDD_UOHM</id> + </attribute> + <attribute> + <id>PROC_R_DISTLOSS_VDD_UOHM</id> + </attribute> + <attribute> + <id>PROC_VRM_VOFFSET_VDD_UV</id> + </attribute> + <attribute> + <id>PROC_R_LOADLINE_VDN_UOHM</id> + </attribute> + <attribute> + <id>PROC_R_DISTLOSS_VDN_UOHM</id> + </attribute> + <attribute> + <id>PROC_VRM_VOFFSET_VDN_UV</id> + </attribute> + <attribute> + <id>PROC_R_LOADLINE_VCS_UOHM</id> + </attribute> + <attribute> + <id>PROC_R_DISTLOSS_VCS_UOHM</id> + </attribute> + <attribute> + <id>PROC_VRM_VOFFSET_VCS_UV</id> + </attribute> + <attribute> + <id>TOD_CPU_DATA</id> + </attribute> + <attribute> + <id>ICACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <id>ICACHE_SIZE</id> + </attribute> + <attribute> + <id>ICACHE_LINE_SIZE</id> + </attribute> + <attribute> + <id>ICACHE_BLOCK_SIZE</id> + </attribute> + <attribute> + <id>DCACHE_LINE_SIZE</id> + </attribute> + <attribute> + <id>DCACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <id>DATA_CACHE_SIZE</id> + </attribute> + <attribute> + <id>DATA_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <id>L2_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <id>L2_CACHE_SIZE</id> + </attribute> + <attribute> + <id>L2_CACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <id>L3_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <id>L3_CACHE_SIZE</id> + </attribute> + <attribute> + <id>TLB_DATA_ENTRIES</id> + </attribute> + <attribute> + <id>TLB_INSTR_ENTRIES</id> + </attribute> + <attribute> + <id>TLB_DATA_ASSOC_SETS</id> + </attribute> + <attribute> + <id>TLB_INSTR_ASSOC_SETS</id> + </attribute> + <attribute> + <id>TLB_RESERVE_SIZE</id> + </attribute> + <attribute> + <id>TIME_BASE</id> + </attribute> + <attribute> + <id>CPU_ATTR</id> + </attribute> + <attribute> + <id>PROC_OCC_SANDBOX_SIZE</id> + </attribute> + <attribute> + <id>PROC_FABRIC_SYSTEM_MASTER_CHIP</id> + </attribute> + <attribute> + <id>PROC_FABRIC_GROUP_MASTER_CHIP</id> + </attribute> + <attribute> + <id>PROC_FABRIC_A_ATTACHED_CHIP_CNFG</id> + </attribute> + <attribute> + <id>PROC_FABRIC_X_ATTACHED_CHIP_CNFG</id> + </attribute> + <attribute> + <id>PROC_FABRIC_A_ATTACHED_CHIP_ID</id> + </attribute> + <attribute> + <id>PROC_FABRIC_X_ATTACHED_CHIP_ID</id> + </attribute> + <attribute> + <id>PROC_FABRIC_A_ADDR_DIS</id> + </attribute> + <attribute> + <id>PROC_FABRIC_X_ADDR_DIS</id> + </attribute> + <attribute> + <id>PROC_FABRIC_OPTICS_CONFIG_MODE</id> + </attribute> + <attribute> + <id>PROC_FABRIC_A_AGGREGATE</id> + </attribute> + <attribute> + <id>PROC_FABRIC_X_AGGREGATE</id> + </attribute> + <attribute> + <id>XIVE_HW_RESET</id> + </attribute> + <attribute> + <id>DISABLE_I2C_ENGINE2_PORT0_DIAG_MODE</id> + </attribute> + <attribute> + <id>NDL_MESHCTRL_SETUP</id> + </attribute> + <attribute><id>PREVIOUS_SBE_ERROR</id></attribute> </targetType> -<!-- Memory Buffer Target Types --> - -<!-- Centaur chip/DMI --> - <targetType> - <id>chip-membuf-centaur</id> - <parent>chip</parent> - <attribute> - <id>TYPE</id> - <default>MEMBUF</default> - </attribute> - <attribute> - <id>MODEL</id> - <default>CENTAUR</default> - </attribute> - <attribute> - <id>PRIMARY_CAPABILITIES</id> - <default> - <field><id>supportsFsiScom</id><value>1</value></field> - <field><id>supportsXscom</id><value>0</value></field> - <field><id>supportsInbandScom</id><value>1</value></field> - <field><id>reserved</id><value>0</value></field> - </default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000003</default> <!--GARD | MEMDIAG --> - </attribute> - <attribute> - <id>SCOM_SWITCHES</id> - <default> - <field><id>useSbeScom</id><value>1</value></field> - <field><id>useFsiScom</id><value>0</value></field> - <field><id>useXscom</id><value>0</value></field> - <field><id>useInbandScom</id><value>0</value></field> - <field><id>reserved</id><value>0</value></field> - </default> - </attribute> - <attribute> - <id>ISDIMM_MBVPD_INDEX</id> - </attribute> - <attribute> - <id>I2C_BUS_SPEED_ARRAY</id> - <default>0,0,0,0,0,400,0,400,400,0,0,0,0,0,0,0</default> - </attribute> - <attribute><id>MSS_FREQ</id></attribute> - <attribute><id>MSS_LAB_OVERRIDE_FOR_MEM_PLL</id></attribute> - <attribute><id>ECID</id></attribute> - <attribute> - <id>CENTAUR_ECID_FRU_ID</id> - <default>0xFF</default> - </attribute> - <attribute><id>MRW_MEM_SENSOR_CACHE_ADDR_MAP</id></attribute> - <attribute> - <!-- Centaur memory buffer chips do not have SCOM accessible FSI GP regs --> - <id>FSI_GP_REG_SCOM_ACCESS</id> - <default>0</default> - </attribute> - <attribute> - <!-- Centaur memory buffer chips do not have an SBE --> - <id>CHIP_HAS_SBE</id> - <default>0</default> - </attribute> - <attribute><id>MSS_CACHE_ENABLE</id></attribute> - - <attribute><id>EI_BUS_TX_LANE_INVERT</id></attribute> - <!-- Begin poreve_memory_attributes.xml --> - <attribute><id>SBE_SEEPROM_I2C_ADDRESS_BYTES</id></attribute> - <attribute><id>SBE_SEEPROM_I2C_DEVICE_ADDRESS</id></attribute> - <attribute><id>SBE_SEEPROM_I2C_PORT</id></attribute> - <attribute><id>PNOR_I2C_ADDRESS_BYTES</id></attribute> - <!-- End poreve_memory_attributes.xml --> - <attribute><id>VPD_REC_NUM</id></attribute> - <attribute><id>MSS_PSRO</id></attribute> - <attribute><id>MSS_NWELL_MISPLACEMENT</id></attribute> - <attribute><id>EI_BUS_TX_MSBSWAP</id></attribute> - <attribute><id>MSS_FREQ_OVERRIDE</id></attribute> - <attribute><id>MEMB_TP_BNDY_PLL_SCAN_SELECT</id></attribute> - <attribute><id>MSS_FREQ_BIAS_PERCENTAGE</id></attribute> - <attribute><id>CDIMM_SENSOR_MAP_PRIMARY</id></attribute> - <attribute><id>CDIMM_SENSOR_MAP_SECONDARY</id></attribute> - <attribute><id>MSS_BLUEWATERFALL_BROKEN</id></attribute> - <attribute><id>DMI_DFE_OVERRIDE</id></attribute> - <attribute><id>MSS_INIT_STATE</id></attribute> - <attribute><id>MSS_NEST_CAPABLE_FREQUENCIES</id></attribute> - <attribute><id>MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT</id></attribute> - <attribute><id>MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE</id></attribute> - <attribute><id>MSS_VOLT_OVERRIDE</id></attribute> - <attribute> - <id>I2C_SWITCHES</id> - <default> - <field><id>useFsiI2C</id><value>1</value></field> - <field><id>useHostI2C</id><value>0</value></field> - <field><id>reserved</id><value>0</value></field> - </default> - </attribute> - <attribute><id>CDM_DOMAIN</id><default>MEM</default></attribute> - <attribute><id>FRU_ID</id></attribute> - <attribute><id>MSS_VREF_CAL_CNTL</id></attribute> + <id>unit</id> + <parent>base</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <id>MRU_ID</id> + </attribute> + <attribute><id>CHIP_UNIT</id></attribute> + <attribute> + <default> + <field> + <id>supportsFsiScom</id> + <value>1</value> + </field> + <field> + <id>supportsXscom</id> + <value>1</value> + </field> + <field> + <id>supportsInbandScom</id> + <value>0</value> + </field> + <field> + <id>reserved</id> + <value>0</value> + </field> + </default> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute> + <id>CHIPLET_ID</id> + </attribute> + <attribute> + <id>REL_POS</id> + </attribute> </targetType> -<!--Dummy card to use as a DIMM for initial I2C/EEPROM testing --> <targetType> - <id>card</id> - <parent>base</parent> - <attribute> - <id>CLASS</id> - <default>CARD</default> - </attribute> - + <id>chip-membuf-centaur</id> + <parent>chip</parent> + <attribute> + <default>MEMBUF</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>CENTAUR</default> + <id>MODEL</id> + </attribute> + <attribute> + <default> + <field> + <id>supportsFsiScom</id> + <value>1</value> + </field> + <field> + <id>supportsXscom</id> + <value>0</value> + </field> + <field> + <id>supportsInbandScom</id> + <value>1</value> + </field> + <field> + <id>reserved</id> + <value>0</value> + </field> + </default> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000003</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default> + <field> + <id>useSbeScom</id> + <value>1</value> + </field> + <field> + <id>useFsiScom</id> + <value>0</value> + </field> + <field> + <id>useXscom</id> + <value>0</value> + </field> + <field> + <id>useInbandScom</id> + <value>0</value> + </field> + <field> + <id>reserved</id> + <value>0</value> + </field> + </default> + <id>SCOM_SWITCHES</id> + </attribute> + <attribute> + <default>0,0,0,0,0,400,0,400,400,0,0,0,0,0,0,0</default> + <id>I2C_BUS_SPEED_ARRAY</id> + </attribute> + <attribute> + <id>MSS_FREQ</id> + </attribute> + <attribute> + <id>ECID</id> + </attribute> + <attribute> + <default>0xFF</default> + <id>CENTAUR_ECID_FRU_ID</id> + </attribute> + <attribute> + <id>SBE_SEEPROM_I2C_DEVICE_ADDRESS</id> + </attribute> + <attribute> + <id>SBE_SEEPROM_I2C_PORT</id> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + </attribute> + <attribute> + <id>EI_BUS_TX_MSBSWAP</id> + </attribute> + <attribute> + <id>MSS_FREQ_OVERRIDE</id> + </attribute> + <attribute> + <id>MSS_FREQ_BIAS_PERCENTAGE</id> + </attribute> + <attribute> + <id>MSS_VOLT_OVERRIDE</id> + </attribute> + <attribute> + <default> + <field> + <id>useFsiI2C</id> + <value>1</value> + </field> + <field> + <id>useHostI2C</id> + <value>0</value> + </field> + <field> + <id>reserved</id> + <value>0</value> + </field> + </default> + <id>I2C_SWITCHES</id> + </attribute> + <attribute> + <default>MEM</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> </targetType> <targetType> - <id>lcard-dimm</id> - <parent>card</parent> - <attribute> - <id>TYPE</id> - <default>DIMM</default> - </attribute> - <attribute> - <id>CLASS</id> - <default>LOGICAL_CARD</default> - </attribute> - <attribute> - <id>POSITION</id> - </attribute> - <attribute> - <id>MBA_PORT</id> - </attribute> - <attribute> - <id>MBA_DIMM</id> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000003</default> <!--GARD | MEMDIAG --> - </attribute> - <attribute><id>TEMP_SENSOR_I2C_CONFIG</id></attribute> - <attribute><id>VPD_REC_NUM</id></attribute> - <attribute><id>MSS_EFF_VPD_VERSION</id></attribute> - <attribute><id>CDM_DOMAIN</id><default>DIMM</default></attribute> - - <attribute><id>FRU_ID</id></attribute> - <attribute><id>SPD_OVERRIDE_ENABLE</id></attribute> - <attribute><id>SPD_OVERRIDE</id></attribute> - <attribute><id>REL_POS</id></attribute> + <id>card</id> + <parent>base</parent> + <attribute> + <default>CARD</default> + <id>CLASS</id> + </attribute> </targetType> <targetType> - <id>lcard-dimm-jedec</id> - <parent>lcard-dimm</parent> - <attribute><id>MODEL</id><default>JEDEC</default></attribute> - <attribute><id>CEN_DQ_TO_DIMM_CONN_DQ</id></attribute> + <id>lcard-dimm</id> + <parent>card</parent> + <attribute> + <default>DIMM</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>LOGICAL_CARD</default> + <id>CLASS</id> + </attribute> + <attribute> + <id>POSITION</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000003</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>TEMP_SENSOR_I2C_CONFIG</id> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + </attribute> + <attribute> + <id>MSS_EFF_VPD_VERSION</id> + </attribute> + <attribute> + <default>DIMM</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> + <attribute> + <id>SPD_OVERRIDE_ENABLE</id> + </attribute> + <attribute> + <id>SPD_OVERRIDE</id> + </attribute> + <attribute><id>REL_POS</id></attribute> </targetType> <targetType> - <id>lcard-dimm-cdimm</id> - <parent>lcard-dimm</parent> - <attribute><id>MODEL</id><default>CDIMM</default></attribute> + <id>lcard-dimm-jedec</id> + <attribute> + <default>JEDEC</default> + <id>MODEL</id> + </attribute> + <parent>lcard-dimm</parent> + <attribute> + <id>CEN_DQ_TO_DIMM_CONN_DQ</id> + </attribute> </targetType> <targetType> - <id>lcard-dimm-ddr4</id> - <parent>lcard-dimm</parent> + <id>lcard-dimm-cdimm</id> + <parent>lcard-dimm</parent> + <attribute> + <default>CDIMM</default> + <id>MODEL</id> + </attribute> </targetType> <targetType> - <id>occ</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>OCC</default> - </attribute> - <attribute> - <id>MODEL</id> - <default>POWER9</default> - </attribute> - <attribute> - <id>OCC_MASTER_CAPABLE</id> - </attribute> - <attribute> - <id>FRU_ID</id> - </attribute> + <id>lcard-dimm-ddr4</id> + <parent>lcard-dimm</parent> </targetType> -<!-- ****************************************** --> -<!-- P9 targets --> -<!-- ****************************************** --> +<targetType> + <id>occ</id> + <parent>unit</parent> + <attribute> + <default>OCC</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>POWER9</default> + <id>MODEL</id> + </attribute> + <attribute> + <id>OCC_MASTER_CAPABLE</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> +</targetType> -<!-- TODO: RTC 129517 Need to update attributes for each target --> +<targetType> + <id>sys-sys-power9</id> + <parent>base</parent> + <attribute><id>FUSED_CORE_MODE_HB</id></attribute> + <attribute><id>WOF_TABLE_LID_NUMBER</id></attribute> + <attribute><id>SOCKET_POWER_NOMINAL</id></attribute> + <attribute><id>SOCKET_POWER_TURBO</id></attribute> + <attribute><id>FREQ_CORE_MAX</id></attribute> + <attribute><id>ULTRA_TURBO_FREQ_MHZ</id></attribute> + <attribute><id>PIB_I2C_NEST_PLL</id></attribute> + <attribute><id>NEST_PLL_FREQ_BUCKETS</id></attribute> + <attribute><id>NEST_PLL_FREQ_LIST</id></attribute> + <attribute><id>SBE_UPDATE_DISABLE</id></attribute> + <attribute><id>NEST_PLL_FREQ_I2CDIV_LIST</id></attribute> + <attribute><id>PROC_REFCLOCK_RCVR_TERM</id></attribute> + <attribute><id>PCI_REFCLOCK_RCVR_TERM</id></attribute> + <attribute><id>SYNC_BETWEEN_STEPS</id></attribute> + <attribute><id>MIRROR_BASE_ADDRESS</id></attribute> + <attribute> + <default>SYS</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>SYS</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>POWER9</default> + <id>MODEL</id> + </attribute> + <attribute> + <default>0x00010000</default> + <id>HUID</id> + </attribute> + <attribute> + <id>EXECUTION_PLATFORM</id> + </attribute> + <attribute> + <default>physical:sys-0</default> + <id>PHYS_PATH</id> + </attribute> + <attribute> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>SCRATCH_UINT8_2</id> + </attribute> + <attribute> + <id>SCRATCH_UINT32_1</id> + </attribute> + <attribute> + <id>SCRATCH_UINT32_2</id> + </attribute> + <attribute> + <id>SCRATCH_UINT64_1</id> + </attribute> + <attribute> + <id>SCRATCH_UINT64_2</id> + </attribute> + <attribute> + <id>SCRATCH_UINT8_ARRAY_1</id> + </attribute> + <attribute> + <id>SCRATCH_UINT8_ARRAY_2</id> + </attribute> + <attribute> + <id>SCRATCH_UINT32_ARRAY_1</id> + </attribute> + <attribute> + <id>SCRATCH_UINT32_ARRAY_2</id> + </attribute> + <attribute> + <id>SCRATCH_UINT64_ARRAY_1</id> + </attribute> + <attribute> + <id>SCRATCH_UINT64_ARRAY_2</id> + </attribute> + <attribute> + <id>SCRATCH_INT8_1</id> + </attribute> + <attribute> + <id>SCRATCH_INT8_2</id> + </attribute> + <attribute> + <id>SCRATCH_INT32_1</id> + </attribute> + <attribute> + <id>SCRATCH_INT32_2</id> + </attribute> + <attribute> + <id>SCRATCH_INT64_1</id> + </attribute> + <attribute> + <id>SCRATCH_INT64_2</id> + </attribute> + <attribute> + <id>SCRATCH_INT8_ARRAY_1</id> + </attribute> + <attribute> + <id>SCRATCH_INT8_ARRAY_2</id> + </attribute> + <attribute> + <id>SCRATCH_INT32_ARRAY_1</id> + </attribute> + <attribute> + <id>SCRATCH_INT32_ARRAY_2</id> + </attribute> + <attribute> + <id>SCRATCH_INT64_ARRAY_1</id> + </attribute> + <attribute> + <id>SCRATCH_INT64_ARRAY_2</id> + </attribute> + <attribute> + <default>affinity:sys-0</default> + <id>AFFINITY_PATH</id> + </attribute> + <attribute> + <default>0x000603FC00000000</default> + <id>XSCOM_BASE_ADDRESS</id> + </attribute> + <attribute> + <default>0x0006030000000000</default> + <id>LPC_BUS_ADDR</id> + </attribute> + <attribute> + <default>0</default> + <id>IS_SIMULATION</id> + </attribute> + <attribute> + <id>HB_HRMOR_NODAL_BASE</id> + </attribute> + <attribute> + <id>TPM_REQUIRED</id> + </attribute> + <attribute> + <id>MSS_MRW_SUPPORTED_FREQ</id> + </attribute> + <attribute> + <id>MAX_PROC_CHIPS_PER_NODE</id> + </attribute> + <attribute> + <id>MAX_EXS_PER_PROC_CHIP</id> + </attribute> + <attribute> + <default>43</default> + <id>MAX_CHIPLETS_PER_PROC</id> + </attribute> + <attribute> + <id>MAX_MCS_PER_SYSTEM</id> + </attribute> + <attribute> + <id>TEST_NEGATIVE_FCN</id> + </attribute> + <attribute> + <id>RECONFIGURE_LOOP</id> + </attribute> + <attribute> + <id>RECONFIG_LOOP_TESTS</id> + </attribute> + <attribute> + <id>ISTEP_PAUSE_ENABLE</id> + </attribute> + <attribute> + <id>ISTEP_PAUSE_CONFIG</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> + <attribute> + <id>BMC_FRU_ID</id> + </attribute> + <attribute> + <id>DD1_SLOW_PCI_REF_CLOCK</id> + </attribute> + <attribute> + <id>DPO_MIN_FREQ_PERCENT</id> + </attribute> + <attribute> + <id>FREQ_PROC_REFCLOCK_KHZ</id> + </attribute> + <attribute> + <id>FREQ_MEM_REFCLOCK</id> + </attribute> + <attribute> + <id>MAX_ALLOWED_DIMM_FREQ</id> + </attribute> + <attribute> + <id>REQUIRED_SYNCH_MODE</id> + </attribute> + <attribute> + <id>BOOT_FREQ_MHZ</id> + </attribute> + <attribute> + <id>FREQ_A_MHZ</id> + </attribute> + <attribute> + <id>ASYNC_NEST_FREQ_MHZ</id> + </attribute> + <attribute> + <id>FREQ_PCIE_MHZ</id> + </attribute> + <attribute> + <id>FREQ_X_MHZ</id> + </attribute> + <attribute> + <id>PROC_EPS_TABLE_TYPE</id> + </attribute> + <attribute> + <id>PROC_FABRIC_PUMP_MODE</id> + </attribute> + <attribute> + <id>MSS_MRW_THERMAL_MEMORY_POWER_LIMIT</id> + </attribute> + <attribute> + <id>EXTERNAL_VRM_STEPSIZE</id> + </attribute> + <attribute> + <id>EXTERNAL_VRM_STEPDELAY</id> + </attribute> + <attribute> + <id>SPIPSS_FREQUENCY</id> + </attribute> + <attribute> + <id>MEM_MIRROR_PLACEMENT_POLICY</id> + </attribute> + <attribute> + <id>MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id> + </attribute> + <attribute> + <id>MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE</id> + </attribute> + <attribute> + <id>MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS</id> + </attribute> + <attribute> + <id>MSS_MRW_MAX_DRAM_DATABUS_UTIL</id> + </attribute> + <attribute> + <id>MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id> + </attribute> + <attribute> + <id>MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id> + </attribute> + <attribute> + <id>MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS</id> + </attribute> + <attribute> + <id>MSS_MRW_POWER_CONTROL_REQUESTED</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L2_CACHE_CES</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L2_DIR_CES</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L3_CACHE_CES</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L3_DIR_CES</id> + </attribute> + <attribute> + <id>FIELD_TH_P8EX_L2_LINE_DELETES</id> + </attribute> + <attribute> + <id>FIELD_TH_P8EX_L3_LINE_DELETES</id> + </attribute> + <attribute> + <id>FIELD_TH_P8EX_L2_COL_REPAIRS</id> + </attribute> + <attribute> + <id>FIELD_TH_P8EX_L3_COL_REPAIRS</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L2_LINE_DELETES</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L3_LINE_DELETES</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L2_COL_REPAIRS</id> + </attribute> + <attribute> + <id>MNFG_TH_P8EX_L3_COL_REPAIRS</id> + </attribute> + <attribute> + <id>MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO</id> + </attribute> + <attribute> + <id>MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO</id> + </attribute> + <attribute> + <id>MNFG_TH_CEN_MBA_RT_RCE_PER_RANK</id> + </attribute> + <attribute> + <id>MNFG_TH_CEN_L4_CACHE_CES</id> + </attribute> + <attribute> + <id>MNFG_TH_RCD_PARITY_ERRORS</id> + </attribute> + <attribute> + <id>MNFG_TH_MEMORY_IUES</id> + </attribute> + <attribute> + <id>MNFG_TH_MEMORY_IMPES</id> + </attribute> + <attribute> + <id>RCD_PARITY_RECONFIG_LOOPS_ALLOWED</id> + </attribute> + <attribute> + <id>MAX_PROC_CHIPS_PER_NODE</id> + </attribute> + <attribute> + <id>MAX_EXS_PER_PROC_CHIP</id> + </attribute> + <attribute> + <id>MAX_MBAS_PER_MEMBUF_CHIP</id> + </attribute> + <attribute> + <id>MAX_MBA_PORTS_PER_MBA</id> + </attribute> + <attribute> + <id>MAX_DIMMS_PER_MBA_PORT</id> + </attribute> + <attribute> + <id>MAX_CHIPLETS_PER_PROC</id> + </attribute> + <attribute> + <id>MAX_MCS_PER_SYSTEM</id> + </attribute> + <attribute> + <id>FABRIC_TO_PHYSICAL_NODE_MAP</id> + </attribute> + <attribute> + <id>RUN_MAX_MEM_PATTERNS</id> + </attribute> + <attribute> + <id>SP_FUNCTIONS</id> + </attribute> + <attribute> + <id>HB_SETTINGS</id> + </attribute> + <attribute> + <id>CEC_IPL_TYPE</id> + </attribute> + <attribute> + <id>PAYLOAD_KIND</id> + </attribute> + <attribute> + <id>PAYLOAD_BASE</id> + </attribute> + <attribute> + <id>PAYLOAD_ENTRY</id> + </attribute> + <attribute> + <id>ENABLED_THREADS</id> + </attribute> + <attribute> + <id>ISTEP_MODE</id> + </attribute> + <attribute> + <id>RECONFIG_LOOP_TESTS_ENABLE</id> + </attribute> + <attribute> + <id>ISTEP_PAUSE_ENABLE</id> + </attribute> + <attribute> + <id>ISTEP_PAUSE_CONFIG</id> + </attribute> + <attribute> + <id>CDM_POLICIES</id> + </attribute> + <attribute> + <id>HOSTSVC_PLID</id> + </attribute> + <attribute> + <id>MNFG_FLAGS</id> + </attribute> + <attribute> + <id>FABRIC_TO_PHYSICAL_NODE_MAP</id> + </attribute> + <attribute> + <id>NUMERIC_POD_TYPE_TEST</id> + </attribute> + <attribute> + <id>TEST_NULL_STRING</id> + </attribute> + <attribute> + <default>Z</default> + <id>TEST_MIN_STRING</id> + </attribute> + <attribute> + <id>TEST_MAX_STRING</id> + </attribute> + <attribute> + <id>TEST_NO_DEFAULT_STRING</id> + </attribute> + <attribute> + <id>DO_ABUS_DECONFIG</id> + </attribute> + <attribute> + <id>PLCK_IPL_ATTR_OVERRIDES_EXIST</id> + </attribute> + <attribute> + <id>PAYLOAD_IN_MIRROR_MEM</id> + </attribute> + <attribute> + <id>FUSED_CORE_OPTION</id> + </attribute> + <attribute> + <id>EFFECTIVE_EC</id> + </attribute> + <attribute> + <id>HB_RSV_MEM_SIZE_MB</id> + </attribute> + <attribute> + <id>THREAD_COUNT</id> + </attribute> + <attribute> + <id>SYSTEM_IPL_PHASE</id> + </attribute> + <attribute> + <id>FREQ_CORE_CEILING_MHZ</id> + </attribute> + <attribute> + <id>PROC_FABRIC_A_BUS_WIDTH</id> + </attribute> + <attribute> + <id>PROC_FABRIC_X_BUS_WIDTH</id> + </attribute> + <attribute> + <id>PROC_FABRIC_CCSM_MODE</id> + </attribute> + <attribute> + <id>PROC_FABRIC_SMP_OPTICS_MODE</id> + </attribute> + <attribute> + <id>PROC_FABRIC_CAPI_MODE</id> + </attribute> + <attribute> + <id>HDAT_RSV_MEM_NUM_SECTIONS</id> + </attribute> + <attribute> + <id>HDAT_HBRT_NUM_SECTIONS</id> + </attribute> + <attribute> + <id>HDAT_HBRT_SECTION_SIZE</id> + </attribute> + <attribute> + <id>MSS_MRW_PREFETCH_ENABLE</id> + </attribute> + <attribute> + <id>MSS_MRW_CLEANER_ENABLE</id> + </attribute> + <attribute> + <id>MSS_VDDR_OVERIDE_SPD</id> + </attribute> + <attribute> + <id>MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> + </attribute> + <attribute> + <id>MSS_MRW_THERMAL_MEMORY_POWER_LIMIT</id> + </attribute> + <attribute> + <id>MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id> + </attribute> + <attribute> + <id>MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE</id> + </attribute> + <attribute> + <id>MSS_MRW_MEM_M_DRAM_CLOCKS</id> + </attribute> + <attribute> + <id>MSS_MRW_MAX_DRAM_DATABUS_UTIL</id> + </attribute> + <attribute> + <id>MSS_MRW_MCS_PREFETCH_RETRY_THRESHOLD</id> + </attribute> + <attribute> + <id>MSS_MRW_POWER_CONTROL_REQUESTED</id> + </attribute> + <attribute> + <id>MSS_MRW_IDLE_POWER_CONTROL_REQUESTED</id> + </attribute> + <attribute> + <id>MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id> + </attribute> + <attribute> + <id>MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id> + </attribute> + <attribute> + <id>MSS_MRW_AVDD_OFFSET_DISABLE</id> + </attribute> + <attribute> + <id>MSS_MRW_VDD_OFFSET_DISABLE</id> + </attribute> + <attribute> + <id>MSS_MRW_VCS_OFFSET_DISABLE</id> + </attribute> + <attribute> + <id>MSS_MRW_VPP_OFFSET_DISABLE</id> + </attribute> + <attribute> + <id>MSS_MRW_VDDR_OFFSET_DISABLE</id> + </attribute> + <attribute> + <id>MSS_MRW_FINE_REFRESH_MODE</id> + </attribute> + <attribute> + <id>MSS_MRW_TEMP_REFRESH_RANGE</id> + </attribute> + <attribute> + <id>MSS_MRW_RESET_DELAY_BEFORE_CAL</id> + </attribute> + <attribute> + <id>MSS_MRW_DRAM_2N_MODE</id> + </attribute> + <attribute> + <id>MRW_HW_MIRRORING_ENABLE</id> + </attribute> + <attribute> + <id>BOOT_FLAGS</id> + </attribute> + <attribute> + <id>NEST_PLL_BUCKET</id> + </attribute> + <attribute> + <id>RISK_LEVEL</id> + </attribute> + <attribute> + <id>SYS_FORCE_ALL_CORES</id> + </attribute> + <attribute> + <id>DISABLE_HBBL_VECTORS</id> + </attribute> + <attribute> + <id>SECURITY_ENABLE</id> + </attribute> + <attribute> + <id>SECURITY_MODE</id> + </attribute> + <attribute> + <id>PIBMEM_REPAIR0</id> + </attribute> + <attribute> + <id>PIBMEM_REPAIR1</id> + </attribute> + <attribute> + <id>PIBMEM_REPAIR2</id> + </attribute> + <attribute> + <id>PROC_FABRIC_CORE_FLOOR_RATIO</id> + </attribute> + <attribute> + <id>PROC_FABRIC_CORE_CEILING_RATIO</id> + </attribute> + <attribute> + <id>PROC_EPS_GB_PERCENTAGE</id> + </attribute> + <attribute> + <id>PROC_EPS_READ_CYCLES_T0</id> + </attribute> + <attribute> + <id>PROC_EPS_READ_CYCLES_T1</id> + </attribute> + <attribute> + <id>PROC_EPS_READ_CYCLES_T2</id> + </attribute> + <attribute> + <id>PROC_EPS_WRITE_CYCLES_T1</id> + </attribute> + <attribute> + <id>PROC_EPS_WRITE_CYCLES_T2</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR3_VDDR_SLOPE</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR4_VDDR_SLOPE</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT</id> + </attribute> + <attribute> + <id>MRW_DDR3_VDDR_MAX_LIMIT</id> + </attribute> + <attribute> + <id>MRW_DDR4_VDDR_MAX_LIMIT</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id> + </attribute> + <attribute> + <id>MSS_VOLT_VPP_SLOPE</id> + </attribute> + <attribute> + <id>MSS_VOLT_VPP_INTERCEPT</id> + </attribute> + <attribute> + <id>MSS_INTERLEAVE_ENABLE</id> + </attribute> + <attribute> + <id>SUPPORTS_DYNAMIC_MEM_VOLT</id> + </attribute> + <attribute> + <id>MSS_VDD_PROGRAM</id> + </attribute> + <attribute> + <id>MSS_AVDD_PROGRAM</id> + </attribute> + <attribute> + <id>MSS_VCS_PROGRAM</id> + </attribute> + <attribute> + <id>MSS_VPP_PROGRAM</id> + </attribute> + <attribute> + <id>MSS_VDDR_PROGRAM</id> + </attribute> + <attribute> + <id>PROC_PCIE_MMIO_BAR0_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_PCIE_MMIO_BAR1_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_PCIE_REGISTER_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_XSCOM_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_LPC_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_PCIE_BAR_SIZE</id> + </attribute> + <attribute> + <id>PROC_FSP_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_FSP_BAR_SIZE</id> + </attribute> + <attribute> + <id>PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_NX_RNG_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_FSP_MMIO_MASK_SIZE</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET_MASK</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET_MASK</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_TM1_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_TM1_BAR_PAGE_SIZE</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_IC_BAR_BASE_ADDR_OFFSET</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_IC_BAR_PAGE_SIZE</id> + </attribute> + <attribute> + <id>VDM_DROOP_SMALL_OVERRIDE</id> + </attribute> + <attribute> + <id>VDM_DROOP_LARGE_OVERRIDE</id> + </attribute> + <attribute> + <id>VDM_DROOP_EXTREME_OVERRIDE</id> + </attribute> + <attribute> + <id>VDM_OVERVOLT_OVERRIDE</id> + </attribute> + <attribute> + <id>VDM_FMAX_OVERRIDE_KHZ</id> + </attribute> + <attribute> + <id>VDM_FMIN_OVERRIDE_KHZ</id> + </attribute> + <attribute> + <id>VDM_VID_COMPARE_OVERRIDE_MV</id> + </attribute> + <attribute> + <id>IVRM_DEADZONE_MV</id> + </attribute> + <attribute> + <id>PM_SAFE_FREQUENCY_MHZ</id> + </attribute> + <attribute> + <id>PM_SAFE_VOLTAGE_MV</id> + </attribute> + <attribute> + <id>FSP_BAR_SIZE</id> + </attribute> + <attribute> + <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4</id> + </attribute> + <attribute> + <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR3</id> + </attribute> + <attribute> + <id>STOP11_DISABLE</id> + </attribute> + <attribute> + <id>SYSTEM_RESCLK_STEP_DELAY</id> + </attribute> + <attribute> + <id>DPLL_VDM_RESPONSE</id> + </attribute> + <attribute> + <id>MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id> + </attribute> + <attribute> + <id>WOF_POWER_LIMIT</id> + </attribute> + <attribute> + <id>AVSBUS_FREQUENCY</id> + </attribute> + <attribute> + <id>PROC_FABRIC_ASYNC_SAFE_MODE</id> + </attribute> + <attribute> + <id>STOP8_DISABLE</id> + </attribute> + <attribute> + <id>STOP4_DISABLE</id> + </attribute> + <attribute> + <id>STOP5_DISABLE</id> + </attribute> + <attribute> + <id>SUPPORTED_STOP_STATES</id> + </attribute> + <attribute> + <id>SYSTEM_FAMILY</id> + </attribute> + <attribute> + <id>SYSTEM_TYPE</id> + </attribute> + <attribute> + <id>MSS_CAL_ABORT_ON_ERROR</id> + </attribute> + <attribute> + <id>SBE_IMAGE_MINIMUM_VALID_ECS</id> + </attribute> + <attribute> + <id>MAX_SBE_SEEPROM_SIZE</id> + </attribute> + <attribute> + <id>SBE_SYS_CONFIG</id> + </attribute> + <attribute> + <id>CP_REFCLOCK_RCVR_TERM</id> + </attribute> + <attribute> + <id>IO_REFCLOCK_RCVR_TERM</id> + </attribute> + <attribute> + <id>MSS_MRW_PWR_INTERCEPT</id> + </attribute> + <attribute> + <id>MSS_MRW_PWR_SLOPE</id> + </attribute> + <attribute> + <id>IVRM_STRENGTH_LOOKUP</id> + </attribute> + <attribute> + <id>IVRM_VIN_MULTIPLIER</id> + </attribute> + <attribute> + <id>IVRM_VIN_MAX_MV</id> + </attribute> + <attribute> + <id>IVRM_STEP_DELAY_NS</id> + </attribute> + <attribute> + <id>IVRM_STABILIZATION_DELAY_NS</id> + </attribute> + <attribute> + <id>MSS_MRW_REFRESH_RATE_REQUEST</id> + </attribute> + <attribute> + <id>MSS_MRW_TEMP_REFRESH_MODE</id> + </attribute> + <attribute> + <id>MSS_VCCD_OVERRIDE</id> + </attribute> + <attribute> + <id>RAW_MTM</id> + </attribute> + <attribute> + <id>MSS_MEM_PORT_POS_OF_FAIL_THROTTLE</id> + </attribute> + <attribute> + <id>SYSTEM_RING_DBG_MODE</id> + </attribute> + <attribute> + <id>MSS_MRW_DRAM_WRITE_CRC</id> + </attribute> + <attribute> + <id>POUND_W_STATIC_DATA_ENABLE</id> + </attribute> + <attribute> + <id>PGPE_HCODE_FUNCTION_ENABLE</id> + </attribute> + <attribute> + <id>PERF_24x7_INVOCATION_TIME_MS</id> + </attribute> + <attribute> + <id>AUX_FUNC_INVOCATION_TIME_MS</id> + </attribute> + <attribute> + <id>MFG_TRACE_ENABLE</id> + </attribute> + <attribute> + <id>FREQ_PROC_REFCLOCK</id> + </attribute> + <attribute> + <id>X_EREPAIR_THRESHOLD_FIELD</id> + </attribute> + <attribute><id>A_EREPAIR_THRESHOLD_FIELD</id></attribute> + <attribute><id>DMI_EREPAIR_THRESHOLD_FIELD</id></attribute> + <attribute><id>X_EREPAIR_THRESHOLD_MNFG</id></attribute> + <attribute><id>A_EREPAIR_THRESHOLD_MNFG</id></attribute> + <attribute><id>DMI_EREPAIR_THRESHOLD_MNFG</id></attribute> + <attribute><id>MSS_MBA_ADDR_INTERLEAVE_BIT</id></attribute> + <attribute><id>MSS_MBA_CACHELINE_INTERLEAVE_MODE</id></attribute> + <attribute><id>PM_SPIVID_FREQUENCY</id></attribute> + <attribute><id>PM_SAFE_FREQUENCY</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id></attribute> + <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id></attribute> + <attribute><id>MRW_MEM_THROTTLE_DENOMINATOR</id></attribute> + <attribute><id>PM_SYSTEM_IVRM_VPD_MIN_LEVEL</id></attribute> + <attribute><id>MNFG_DMI_MIN_EYE_WIDTH</id></attribute> + <attribute><id>MNFG_DMI_MIN_EYE_HEIGHT</id></attribute> + <attribute><id>MNFG_ABUS_MIN_EYE_WIDTH</id></attribute> + <attribute><id>MNFG_ABUS_MIN_EYE_HEIGHT</id></attribute> + <attribute><id>MNFG_XBUS_MIN_EYE_WIDTH</id></attribute> + <attribute><id>REDUNDANT_CLOCKS</id></attribute> + <attribute><id>BRAZOS_RX_FIFO_OVERRIDE</id></attribute> + <attribute><id>MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id></attribute> + <attribute><id>MAX_DMI_PER_PROC</id></attribute> + <attribute><id>PIB_I2C_REFCLOCK</id></attribute> +</targetType> -<!-- sys-sys-power9 --> <targetType> - <id>sys-sys-power9</id> - <parent>base</parent> - <attribute><id>CLASS</id><default>SYS</default></attribute> - <attribute><id>TYPE</id><default>SYS</default></attribute> - <attribute><id>MODEL</id><default>POWER9</default></attribute> - <attribute><id>HUID</id><default>0x00010000</default></attribute> - <attribute><id>EXECUTION_PLATFORM</id></attribute> - <attribute> - <id>PHYS_PATH</id> - <default>physical:sys-0</default> - </attribute> - <attribute><id>SCRATCH_UINT8_1</id></attribute> - <attribute><id>SCRATCH_UINT8_2</id></attribute> - <attribute><id>SCRATCH_UINT32_1</id></attribute> - <attribute><id>SCRATCH_UINT32_2</id></attribute> - <attribute><id>SCRATCH_UINT64_1</id></attribute> - <attribute><id>SCRATCH_UINT64_2</id></attribute> - <attribute><id>SCRATCH_UINT8_ARRAY_1</id></attribute> - <attribute><id>SCRATCH_UINT8_ARRAY_2</id></attribute> - <attribute><id>SCRATCH_UINT32_ARRAY_1</id></attribute> - <attribute><id>SCRATCH_UINT32_ARRAY_2</id></attribute> - <attribute><id>SCRATCH_UINT64_ARRAY_1</id></attribute> - <attribute><id>SCRATCH_UINT64_ARRAY_2</id></attribute> - <attribute><id>SCRATCH_INT8_1</id></attribute> - <attribute><id>SCRATCH_INT8_2</id></attribute> - <attribute><id>SCRATCH_INT32_1</id></attribute> - <attribute><id>SCRATCH_INT32_2</id></attribute> - <attribute><id>SCRATCH_INT64_1</id></attribute> - <attribute><id>SCRATCH_INT64_2</id></attribute> - <attribute><id>SCRATCH_INT8_ARRAY_1</id></attribute> - <attribute><id>SCRATCH_INT8_ARRAY_2</id></attribute> - <attribute><id>SCRATCH_INT32_ARRAY_1</id></attribute> - <attribute><id>SCRATCH_INT32_ARRAY_2</id></attribute> - <attribute><id>SCRATCH_INT64_ARRAY_1</id></attribute> - <attribute><id>SCRATCH_INT64_ARRAY_2</id></attribute> - <attribute> - <id>AFFINITY_PATH</id> - <default>affinity:sys-0</default> - </attribute> - <attribute><id>XSCOM_BASE_ADDRESS</id><default>0x000603FC00000000</default></attribute> - <attribute> - <id>IS_SIMULATION</id> - <default>0</default> - </attribute> - <attribute><id>HB_HRMOR_NODAL_BASE</id></attribute> - <attribute><id>TPM_REQUIRED</id></attribute> - <attribute><id>MSS_MRW_SUPPORTED_FREQ</id></attribute> - <!-- Max/min config attributes --> - <attribute><id>MAX_PROC_CHIPS_PER_NODE</id></attribute> - <attribute><id>MAX_EXS_PER_PROC_CHIP</id></attribute> - <attribute> - <id>MAX_CHIPLETS_PER_PROC</id> - <!-- This number is from latest P9 chiplet list and ID diagram --> - <default>43</default> - </attribute> - <attribute><id>MAX_MCS_PER_SYSTEM</id></attribute> - <attribute><id>MAX_DMI_PER_PROC</id></attribute> - <attribute><id>TEST_NEGATIVE_FCN</id></attribute> - <!-- End max/min config attributes --> - <attribute><id>RECONFIGURE_LOOP</id></attribute> - <attribute><id>RECONFIG_LOOP_TESTS</id></attribute> - <attribute><id>MULTI_SCOM_BUFFER_MAX_SIZE</id></attribute> - <attribute><id>ISTEP_PAUSE_ENABLE</id></attribute> - <attribute><id>ISTEP_PAUSE_CONFIG</id></attribute> - <attribute><id>FRU_ID</id></attribute> - <attribute><id>BMC_FRU_ID</id></attribute> - <attribute><id>PROC_REFCLOCK_RCVR_TERM</id></attribute> - <attribute><id>PCI_REFCLOCK_RCVR_TERM</id></attribute> - <attribute><id>DD1_SLOW_PCI_REF_CLOCK</id></attribute> - <attribute><id>MIN_FREQ_MHZ</id></attribute> - <attribute><id>DPO_MIN_FREQ_PERCENT</id></attribute> - <attribute><id>FREQ_PROC_REFCLOCK</id></attribute> - <attribute><id>FREQ_PROC_REFCLOCK_KHZ</id></attribute> - <attribute><id>FREQ_MEM_REFCLOCK</id></attribute> - <attribute><id>MAX_ALLOWED_DIMM_FREQ</id></attribute> - <attribute><id>REQUIRED_SYNCH_MODE</id></attribute> - <attribute><id>BOOT_FREQ_MHZ</id></attribute> - <attribute><id>FREQ_A_MHZ</id></attribute> - <attribute><id>FREQ_PB_MHZ</id></attribute> - <attribute><id>ASYNC_NEST_FREQ_MHZ</id></attribute> - <attribute><id>FREQ_PCIE_MHZ</id></attribute> - <attribute><id>FREQ_X_MHZ</id></attribute> - <attribute><id>MSS_MBA_ADDR_INTERLEAVE_BIT</id></attribute> - <attribute><id>MSS_MBA_CACHELINE_INTERLEAVE_MODE</id></attribute> - <attribute><id>PROC_EPS_TABLE_TYPE</id></attribute> - <attribute><id>PROC_FABRIC_PUMP_MODE</id></attribute> - <attribute><id>X_EREPAIR_THRESHOLD_FIELD</id></attribute> - <attribute><id>A_EREPAIR_THRESHOLD_FIELD</id></attribute> - <attribute><id>DMI_EREPAIR_THRESHOLD_FIELD</id></attribute> - <attribute><id>X_EREPAIR_THRESHOLD_MNFG</id></attribute> - <attribute><id>A_EREPAIR_THRESHOLD_MNFG</id></attribute> - <attribute><id>DMI_EREPAIR_THRESHOLD_MNFG</id></attribute> - <attribute><id>MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA</id></attribute> - <attribute><id>MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id></attribute> - <attribute><id>MSS_MRW_THERMAL_MEMORY_POWER_LIMIT</id></attribute> - <attribute><id>EXTERNAL_VRM_TRANSITION_START_NS</id></attribute> - <attribute><id>EXTERNAL_VRM_TRANSITION_RATE_INC_UV_PER_US</id></attribute> - <attribute><id>EXTERNAL_VRM_TRANSITION_RATE_DEC_UV_PER_US</id></attribute> - <attribute><id>EXTERNAL_VRM_TRANSITION_STABILIZATION_TIME_NS</id></attribute> - <attribute><id>EXTERNAL_VRM_STEPSIZE</id></attribute> - <attribute><id>EXTERNAL_VRM_STEPDELAY</id></attribute> - <attribute><id>PM_SPIVID_FREQUENCY</id></attribute> - <attribute><id>PM_SAFE_FREQUENCY</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_FULL_CLOCK_SECTOR_BUFFER_FREQUENCY</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_LOWER_FREQUENCY</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_LOW_BAND_UPPER_FREQUENCY</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_LOWER_FREQUENCY</id></attribute> - <attribute><id>PM_RESONANT_CLOCK_HIGH_BAND_UPPER_FREQUENCY</id></attribute> - <attribute><id>SPIPSS_FREQUENCY</id></attribute> - <attribute><id>MEM_MIRROR_PLACEMENT_POLICY</id></attribute> - <attribute><id>MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id></attribute> - <attribute><id>MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE</id></attribute> - <attribute><id>MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS</id></attribute> - <attribute><id>MRW_MEM_THROTTLE_DENOMINATOR</id></attribute> - <attribute><id>MSS_MRW_MAX_DRAM_DATABUS_UTIL</id></attribute> - <attribute><id>MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id></attribute> - <attribute><id>MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE</id></attribute> - <attribute><id>MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id></attribute> - <attribute><id>MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id></attribute> - <attribute><id>MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS</id></attribute> - <attribute><id>SYSTEM_IVRM_DISABLE</id></attribute> - <attribute><id>PM_SYSTEM_IVRM_VPD_MIN_LEVEL</id></attribute> - <attribute><id>MRW_STRICT_MBA_PLUG_RULE_CHECKING</id></attribute> - <attribute><id>MNFG_DMI_MIN_EYE_WIDTH</id></attribute> - <attribute><id>MNFG_DMI_MIN_EYE_HEIGHT</id></attribute> - <attribute><id>MNFG_ABUS_MIN_EYE_WIDTH</id></attribute> - <attribute><id>MNFG_ABUS_MIN_EYE_HEIGHT</id></attribute> - <attribute><id>MNFG_XBUS_MIN_EYE_WIDTH</id></attribute> - <attribute><id>REDUNDANT_CLOCKS</id></attribute> - <attribute><id>MSS_DRAMINIT_RESET_DISABLE</id></attribute> - <attribute><id>MSS_MRW_POWER_CONTROL_REQUESTED</id></attribute> - <attribute><id>MNFG_TH_P8EX_L2_CACHE_CES</id></attribute> - <attribute><id>MNFG_TH_P8EX_L2_DIR_CES</id></attribute> - <attribute><id>MNFG_TH_P8EX_L3_CACHE_CES</id></attribute> - <attribute><id>MNFG_TH_P8EX_L3_DIR_CES</id></attribute> - <attribute><id>FIELD_TH_P8EX_L2_LINE_DELETES</id></attribute> - <attribute><id>FIELD_TH_P8EX_L3_LINE_DELETES</id></attribute> - <attribute><id>FIELD_TH_P8EX_L2_COL_REPAIRS</id></attribute> - <attribute><id>FIELD_TH_P8EX_L3_COL_REPAIRS</id></attribute> - <attribute><id>MNFG_TH_P8EX_L2_LINE_DELETES</id></attribute> - <attribute><id>MNFG_TH_P8EX_L3_LINE_DELETES</id></attribute> - <attribute><id>MNFG_TH_P8EX_L2_COL_REPAIRS</id></attribute> - <attribute><id>MNFG_TH_P8EX_L3_COL_REPAIRS</id></attribute> - <attribute><id>MNFG_TH_CEN_MBA_RT_SOFT_CE_TH_ALGO</id></attribute> - <attribute><id>MNFG_TH_CEN_MBA_IPL_SOFT_CE_TH_ALGO</id></attribute> - <attribute><id>MNFG_TH_CEN_MBA_RT_RCE_PER_RANK</id></attribute> - <attribute><id>MNFG_TH_CEN_L4_CACHE_CES</id></attribute> - <attribute><id>MNFG_TH_RCD_PARITY_ERRORS</id></attribute> - <attribute><id>MNFG_TH_MEMORY_IUES</id></attribute> - <attribute><id>MNFG_TH_MEMORY_IMPES</id></attribute> - <attribute><id>RCD_PARITY_RECONFIG_LOOPS_ALLOWED</id></attribute> - <attribute><id>OPT_MEMMAP_GROUP_POLICY</id></attribute> - <attribute><id>BRAZOS_RX_FIFO_OVERRIDE</id></attribute> - <attribute><id>MRW_MBA_CACHELINE_INTERLEAVE_MODE_CONTROL</id></attribute> - <attribute><id>MAX_PROC_CHIPS_PER_NODE</id></attribute> - <attribute><id>MAX_EXS_PER_PROC_CHIP</id></attribute> - <attribute><id>MAX_MBAS_PER_MEMBUF_CHIP</id></attribute> - <attribute><id>MAX_MBA_PORTS_PER_MBA</id></attribute> - <attribute><id>MAX_DIMMS_PER_MBA_PORT</id></attribute> - <attribute><id>MAX_CHIPLETS_PER_PROC</id></attribute> - <attribute><id>FABRIC_TO_PHYSICAL_NODE_MAP</id></attribute> - <attribute><id>RUN_MAX_MEM_PATTERNS</id></attribute> - <attribute><id>HIDDEN_ERRLOGS_ENABLE</id></attribute> - <attribute><id>SP_FUNCTIONS</id></attribute> - <attribute><id>HB_SETTINGS</id></attribute> - <attribute><id>CEC_IPL_TYPE</id></attribute> - <attribute><id>PAYLOAD_KIND</id></attribute> - <attribute><id>PAYLOAD_BASE</id></attribute> - <attribute><id>PAYLOAD_ENTRY</id></attribute> - <attribute><id>MFG_TRACE_ENABLE</id></attribute> - <attribute><id>ENABLED_THREADS</id></attribute> - <attribute><id>ISTEP_MODE</id></attribute> - <attribute><id>RECONFIG_LOOP_TESTS_ENABLE</id></attribute> - <attribute><id>ISTEP_PAUSE_ENABLE</id></attribute> - <attribute><id>ISTEP_PAUSE_CONFIG</id></attribute> - <attribute><id>CDM_POLICIES</id></attribute> - <attribute><id>HOSTSVC_PLID</id></attribute> - <attribute><id>NOMINAL_FREQ_MHZ</id></attribute> - <attribute><id>MNFG_FLAGS</id></attribute> - <attribute><id>FABRIC_TO_PHYSICAL_NODE_MAP</id></attribute> - <attribute><id>MFG_TRACE_ENABLE</id></attribute> - <attribute><id>NUMERIC_POD_TYPE_TEST</id></attribute> - <attribute><id>DUMMY_RW</id></attribute> - <attribute><id>TEST_NULL_STRING</id></attribute> - <attribute><id>TEST_MIN_STRING</id><default>Z</default></attribute> - <attribute><id>TEST_MAX_STRING</id></attribute> - <attribute><id>TEST_NO_DEFAULT_STRING</id></attribute> - <attribute><id>SYNC_BETWEEN_STEPS</id></attribute> - <attribute><id>DO_ABUS_DECONFIG</id></attribute> - <attribute><id>PLCK_IPL_ATTR_OVERRIDES_EXIST</id></attribute> - <attribute><id>PAYLOAD_IN_MIRROR_MEM</id></attribute> - <!-- AVP override for fused cores or normal cores --> - <attribute><id>FUSED_CORE_OPTION</id></attribute> - <attribute><id>FUSED_CORE_MODE</id></attribute> - <attribute><id>MIRROR_BASE_ADDRESS</id></attribute> - <attribute><id>EFFECTIVE_EC</id></attribute> - <attribute><id>HB_RSV_MEM_SIZE_MB</id></attribute> - <attribute><id>FREQ_CORE_MAX</id></attribute> - <attribute><id>THREAD_COUNT</id></attribute> - <attribute><id>PFET_POWERUP_DELAY_NS</id></attribute> - <attribute><id>PFET_POWERDOWN_DELAY_NS</id></attribute> - <attribute><id>PFET_VDD_VOFF_SEL</id></attribute> - <attribute><id>PFET_VCS_VOFF_SEL</id></attribute> - <attribute><id>SYSTEM_IPL_PHASE</id></attribute> - <attribute><id>FREQ_CORE_CEILING_MHZ</id></attribute> - <attribute><id>ULTRA_TURBO_FREQ_MHZ</id></attribute> - <attribute><id>SOCKET_POWER_NOMINAL</id></attribute> - <attribute><id>SOCKET_POWER_TURBO</id></attribute> - <attribute><id>PROC_FABRIC_A_BUS_WIDTH</id></attribute> - <attribute><id>PROC_FABRIC_X_BUS_WIDTH</id></attribute> - <attribute><id>PROC_FABRIC_CCSM_MODE</id></attribute> - <attribute><id>PROC_FABRIC_SMP_OPTICS_MODE</id></attribute> - <attribute><id>PROC_FABRIC_CAPI_MODE</id></attribute> - <!-- HDAT Hostboot Runtime Data Info --> - <attribute><id>HDAT_RSV_MEM_NUM_SECTIONS</id></attribute> - <attribute><id>HDAT_HBRT_NUM_SECTIONS</id></attribute> - <attribute><id>HDAT_HBRT_SECTION_SIZE</id></attribute> - <attribute><id>PIB_I2C_REFCLOCK</id></attribute> - <attribute><id>PIB_I2C_NEST_PLL</id></attribute> - <attribute><id>MSS_MRW_PREFETCH_ENABLE</id></attribute> - <attribute><id>MSS_MRW_CLEANER_ENABLE</id></attribute> - <attribute><id>MRW_DRAMINIT_RESET_DISABLE</id></attribute> - <attribute><id>MSS_VDDR_OVERIDE_SPD</id></attribute> - <attribute><id>MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT</id></attribute> - <attribute><id>MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id></attribute> - <attribute><id>MSS_MRW_THERMAL_MEMORY_POWER_LIMIT</id></attribute> - <attribute><id>MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT</id></attribute> - <attribute><id>MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE</id></attribute> - <attribute><id>MSS_MRW_MEM_M_DRAM_CLOCKS</id></attribute> - <attribute><id>MSS_MRW_MAX_DRAM_DATABUS_UTIL</id></attribute> - <attribute><id>MSS_MRW_MCS_PREFETCH_RETRY_THRESHOLD</id></attribute> - <attribute><id>MSS_MRW_POWER_CONTROL_REQUESTED</id></attribute> - <attribute><id>MSS_MRW_IDLE_POWER_CONTROL_REQUESTED</id></attribute> - <attribute><id>MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id></attribute> - <attribute><id>MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id></attribute> - <attribute><id>MSS_MRW_AVDD_OFFSET_DISABLE</id></attribute> - <attribute><id>MSS_MRW_VDD_OFFSET_DISABLE</id></attribute> - <attribute><id>MSS_MRW_VCS_OFFSET_DISABLE</id></attribute> - <attribute><id>MSS_MRW_VPP_OFFSET_DISABLE</id></attribute> - <attribute><id>MSS_MRW_VDDR_OFFSET_DISABLE</id></attribute> - <attribute><id>MSS_MRW_FINE_REFRESH_MODE</id></attribute> - <attribute><id>MSS_MRW_TEMP_REFRESH_RANGE</id></attribute> - <attribute><id>MSS_MRW_RESET_DELAY_BEFORE_CAL</id></attribute> - <attribute><id>MSS_MRW_DRAM_2N_MODE</id></attribute> - <attribute><id>MRW_HW_MIRRORING_ENABLE</id></attribute> - <attribute><id>LPC_BUS_ADDR</id><default>0x0006030000000000</default></attribute> - - <!-- attributes for sbe_start --> - <attribute><id>SBE_UPDATE_DISABLE</id></attribute> - <attribute><id>BOOT_FLAGS</id></attribute> - <attribute><id>NEST_PLL_BUCKET</id></attribute> - <attribute><id>NEST_PLL_FREQ_BUCKETS</id></attribute> - <attribute><id>NEST_PLL_FREQ_LIST</id></attribute> - <attribute><id>NEST_PLL_FREQ_I2CDIV_LIST</id></attribute> - <attribute><id>RISK_LEVEL</id></attribute> - <attribute><id>SYS_FORCE_ALL_CORES</id></attribute> - <attribute><id>DISABLE_HBBL_VECTORS</id></attribute> - <attribute><id>SECURITY_ENABLE</id></attribute> - <attribute><id>PIBMEM_REPAIR0</id></attribute> - <attribute><id>PIBMEM_REPAIR1</id></attribute> - <attribute><id>PIBMEM_REPAIR2</id></attribute> - - <!-- proc_fbc_eff_config --> - <attribute><id>PROC_FABRIC_CORE_FLOOR_RATIO</id></attribute> - <attribute><id>PROC_FABRIC_CORE_CEILING_RATIO</id></attribute> - <attribute><id>PROC_EPS_GB_PERCENTAGE</id></attribute> - <attribute><id>PROC_EPS_READ_CYCLES_T0</id></attribute> - <attribute><id>PROC_EPS_READ_CYCLES_T1</id></attribute> - <attribute><id>PROC_EPS_READ_CYCLES_T2</id></attribute> - <attribute><id>PROC_EPS_WRITE_CYCLES_T1</id></attribute> - <attribute><id>PROC_EPS_WRITE_CYCLES_T2</id></attribute> - <!-- End proc_fbc_eff_config --> - <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE</id></attribute> - <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT</id></attribute> - <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE</id></attribute> - <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT</id></attribute> - <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT</id></attribute> - <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT</id></attribute> - <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id></attribute> - <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id></attribute> - <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id></attribute> - <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id></attribute> - <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id></attribute> - <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id></attribute> - <attribute><id>MSS_VOLT_VPP_SLOPE</id></attribute> - <attribute><id>MSS_VOLT_VPP_INTERCEPT</id></attribute> - <attribute><id>MSS_INTERLEAVE_ENABLE</id></attribute> - <attribute><id>MSS_INTERLEAVE_GRANULARITY</id></attribute> - -<!-- Enable memory voltages --> - <attribute><id>SUPPORTS_DYNAMIC_MEM_VOLT</id></attribute> - <attribute><id>MSS_VDD_PROGRAM</id></attribute> - <attribute><id>MSS_AVDD_PROGRAM</id></attribute> - <attribute><id>MSS_VCS_PROGRAM</id></attribute> - <attribute><id>MSS_VPP_PROGRAM</id></attribute> - <attribute><id>MSS_VDDR_PROGRAM</id></attribute> - -<!-- p9_setup_bars - Begin --> - <attribute><id>PROC_PCIE_MMIO_BAR0_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_PCIE_MMIO_BAR1_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_PCIE_REGISTER_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_XSCOM_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_LPC_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_PCIE_BAR_SIZE</id></attribute> - <attribute><id>PROC_FSP_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_FSP_BAR_SIZE</id></attribute> - <attribute><id>PROC_PSI_BRIDGE_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_NPU_PHY0_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_NPU_PHY1_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_NX_RNG_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_FSP_MMIO_MASK_SIZE</id></attribute> - <attribute><id>PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_INT_CQ_PC_BAR_BASE_ADDR_OFFSET_MASK</id></attribute> - <attribute><id>PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_INT_CQ_VC_BAR_BASE_ADDR_OFFSET_MASK</id></attribute> - <attribute><id>PROC_INT_CQ_TM1_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_INT_CQ_TM1_BAR_PAGE_SIZE</id></attribute> - <attribute><id>PROC_INT_CQ_IC_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PROC_INT_CQ_IC_BAR_PAGE_SIZE</id></attribute> -<!-- p9_setup_bars - End --> - - <attribute><id>VDM_DROOP_SMALL_OVERRIDE</id></attribute> - <attribute><id>VDM_DROOP_LARGE_OVERRIDE</id></attribute> - <attribute><id>VDM_DROOP_EXTREME_OVERRIDE</id></attribute> - <attribute><id>VDM_OVERVOLT_OVERRIDE</id></attribute> - <attribute><id>VDM_EXTREME_THOTTLE_ENABLE</id></attribute> - <attribute><id>VDM_SMALL_FREQ_DROP_N_S_OVERRIDE</id></attribute> - <attribute><id>VDM_LARGE_FREQ_DROP_N_L_OVERRIDE</id></attribute> - <attribute><id>VDM_FREQ_RETURN_L_S_OVERRIDE</id></attribute> - <attribute><id>VDM_FREQ_RETURN_S_N_OVERRIDE</id></attribute> - <attribute><id>VDM_FMAX_OVERRIDE_KHZ</id></attribute> - <attribute><id>VDM_FMIN_OVERRIDE_KHZ</id></attribute> - <attribute><id>VDM_VID_COMPARE_OVERRIDE_MV</id></attribute> - <attribute><id>IVRM_DEADZONE_MV</id></attribute> - <attribute><id>PM_SAFE_FREQUENCY_MHZ</id></attribute> - <attribute><id>PM_SAFE_VOLTAGE_MV</id></attribute> - <attribute><id>MSS_MRW_OFFSET_WLO</id></attribute> - <attribute><id>MSS_MRW_OFFSET_GPO</id></attribute> - <attribute><id>MSS_MRW_OFFSET_RLO</id></attribute> - <attribute><id>MSS_MRW_TSYS_DATA</id></attribute> - <attribute><id>MSS_MRW_TSYS_ADR</id></attribute> - <attribute><id>FSP_BAR_SIZE</id></attribute> - <attribute><id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4</id></attribute> - <attribute><id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR3</id></attribute> - <attribute><id>STOP11_DISABLE</id></attribute> - <attribute><id>SYSTEM_RESCLK_STEP_DELAY</id></attribute> - <attribute><id>DPLL_VDM_RESPONSE</id></attribute> - <attribute><id>MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id></attribute> - <attribute><id>SYSTEM_WOF_DISABLE</id></attribute> - <attribute><id>WOF_VRATIO_SELECT</id></attribute> - <attribute><id>WOF_ENABLE_VRATIO</id></attribute> - <attribute><id>WOF_ENABLE_FRATIO</id></attribute> - <attribute><id>WOF_POWER_LIMIT</id></attribute> - <attribute><id>SYS_VFRT_STATIC_DATA_ENABLE</id></attribute> - <attribute><id>WOF_TABLE_LID_NUMBER</id></attribute> - <attribute><id>SYSTEM_PSTATES_MODE</id></attribute> - <attribute><id>AVSBUS_FREQUENCY</id></attribute> - <attribute><id>PROC_FABRIC_ASYNC_SAFE_MODE</id></attribute> - <attribute><id>SYSTEM_VDM_DISABLE</id></attribute> - <attribute><id>STOP8_DISABLE</id></attribute> - <attribute><id>STOP4_DISABLE</id></attribute> - <attribute><id>STOP5_DISABLE</id></attribute> - <attribute><id>SUPPORTED_STOP_STATES</id></attribute> - <attribute><id>SYSTEM_FAMILY</id></attribute> - <attribute><id>SYSTEM_TYPE</id></attribute> - <attribute><id>MSS_CAL_ABORT_ON_ERROR</id></attribute> - <attribute><id>SBE_IMAGE_MINIMUM_VALID_ECS</id></attribute> - <attribute><id>MAX_SBE_SEEPROM_SIZE</id></attribute> - <attribute><id>SBE_SYS_CONFIG</id></attribute> - <attribute><id>CP_REFCLOCK_RCVR_TERM</id></attribute> - <attribute><id>IO_REFCLOCK_RCVR_TERM</id></attribute> - <attribute><id>SECTOR_BUFFER_STRENGTH</id></attribute> - <attribute><id>PULSE_MODE_ENABLE</id></attribute> - <attribute><id>PULSE_MODE_VALUE</id></attribute> - <attribute><id>MSS_MRW_PWR_INTERCEPT</id></attribute> - <attribute><id>MSS_MRW_PWR_SLOPE</id></attribute> - <attribute><id>IVRM_STRENGTH_LOOKUP</id></attribute> - <attribute><id>IVRM_VIN_MULTIPLIER</id></attribute> - <attribute><id>IVRM_VIN_MAX_MV</id></attribute> - <attribute><id>IVRM_STEP_DELAY_NS</id></attribute> - <attribute><id>IVRM_STABILIZATION_DELAY_NS</id></attribute> - <attribute><id>SYSTEM_RESCLK_DISABLE</id></attribute> - <attribute><id>MSS_MRW_REFRESH_RATE_REQUEST</id></attribute> - <attribute><id>MSS_MRW_TEMP_REFRESH_MODE</id></attribute> - <attribute><id>MSS_VCCD_OVERRIDE</id></attribute> - <attribute><id>RAW_MTM</id></attribute> - <attribute><id>MSS_MEM_PORT_POS_OF_FAIL_THROTTLE</id></attribute> - <attribute><id>SYSTEM_RING_DBG_MODE</id></attribute> - <attribute><id>NEST_LEAKAGE_PERCENT</id></attribute> - <attribute><id>MSS_MRW_DRAM_WRITE_CRC</id></attribute> - <attribute><id>POUND_W_STATIC_DATA_ENABLE</id></attribute> - <attribute><id>PGPE_HCODE_FUNCTION_ENABLE</id></attribute> - <attribute><id>PERF_24x7_INVOCATION_TIME_MS</id></attribute> - <attribute><id>AUX_FUNC_INVOCATION_TIME_MS</id></attribute> - <attribute><id>SYSTEM_CORECACHE_SKEWADJ_DISABLE</id></attribute> - <attribute><id>SYSTEM_CORECACHE_DCADJ_DISABLE</id></attribute> - <attribute><id>MC_PLL_BUCKET</id></attribute> -</targetType> - -<!-- enc-node-power9 --> -<targetType> - <id>enc-node-power9</id> - <parent>base</parent> - <attribute> - <id>CLASS</id> - <default>ENC</default> - </attribute> - <attribute> - <id>TYPE</id> - <default>NODE</default> - </attribute> - <attribute> - <id>MODEL</id> - <default>POWER9</default> - </attribute> - <attribute><id>FIELD_CORE_OVERRIDE</id></attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000009</default> <!-- HOSTSVC_HBEL and GARD --> - </attribute> - <attribute><id>CDM_DOMAIN</id><default>NODE</default></attribute> - <attribute><id>FRU_ID</id></attribute> - <attribute><id>EEPROM_VPD_PRIMARY_INFO</id></attribute> - <attribute><id>MSS_VOLT_VPP_SLOPE_EFF_CONFIG</id></attribute> - <attribute><id>MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG</id></attribute> - <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG</id></attribute> - <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG</id></attribute> - <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute> - <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG</id></attribute> - <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG</id></attribute> - <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute> - <attribute><id>HDAT_RSV_MEM_NUM_SECTIONS</id></attribute> - <attribute><id>HDAT_HBRT_NUM_SECTIONS</id></attribute> - <attribute><id>HDAT_HBRT_SECTION_SIZE</id></attribute> - <attribute><id>VPD_REC_NUM</id></attribute> -</targetType> - -<!-- chip-tpm-cectpm --> -<targetType> - <id>chip-tpm-cectpm</id> - <parent>chip</parent> - <attribute> - <id>TYPE</id> - <default>TPM</default> - </attribute> - <attribute> - <id>MODEL</id> - <default>CECTPM</default> - </attribute> - <attribute><id>TPM_INFO</id></attribute> + <id>enc-node-power9</id> + <parent>base</parent> + <attribute> + <default>ENC</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>NODE</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>POWER9</default> + <id>MODEL</id> + </attribute> + <attribute> + <id>FIELD_CORE_OVERRIDE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000009</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default>NODE</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>FRU_ID</id> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + </attribute> + <attribute> + <id>HDAT_RSV_MEM_NUM_SECTIONS</id> + </attribute> + <attribute> + <id>HDAT_HBRT_NUM_SECTIONS</id> + </attribute> + <attribute> + <id>HDAT_HBRT_SECTION_SIZE</id> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + </attribute> + <attribute><id>MSS_VOLT_VPP_SLOPE_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG</id></attribute> + <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG</id></attribute> + <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute> +</targetType> +<targetType> + <id>chip-tpm-cectpm</id> + <parent>chip</parent> + <attribute> + <default>TPM</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>CECTPM</default> + <id>MODEL</id> + </attribute> + <attribute> + <id>TPM_INFO</id> + </attribute> </targetType> -<!-- chip-processor-power9 --> <targetType> - <id>chip-processor-power9</id> - <parent>chip-processor</parent> - <attribute><id>DUMMY_RW</id></attribute> - <attribute><id>DUMMY_HEAP_ZERO_DEFAULT</id></attribute> - <attribute><id>MSS_MEM_MC_IN_GROUP</id></attribute> - <attribute><id>EEPROM_VPD_PRIMARY_INFO</id></attribute> - <attribute><id>EEPROM_VPD_BACKUP_INFO</id></attribute> - <attribute><id>EEPROM_SBE_PRIMARY_INFO</id></attribute> - <attribute><id>EEPROM_SBE_BACKUP_INFO</id></attribute> - <attribute> - <id>I2C_BUS_SPEED_ARRAY</id> - <default>0,0,0,0,0,0,0,0,0,0,0,0</default> - </attribute> + <id>chip-processor-power9</id> + <parent>chip-processor</parent> + <attribute> + <id>DUMMY_HEAP_ZERO_DEFAULT</id> + </attribute> + <attribute> + <id>MSS_MEM_MC_IN_GROUP</id> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + </attribute> + <attribute> + <id>EEPROM_VPD_BACKUP_INFO</id> + </attribute> + <attribute> + <id>EEPROM_SBE_PRIMARY_INFO</id> + </attribute> + <attribute> + <id>EEPROM_SBE_BACKUP_INFO</id> + </attribute> + <attribute> + <default>0,0,0,0,0,0,0,0,0,0,0,0</default> + <id>I2C_BUS_SPEED_ARRAY</id> + </attribute> + <attribute> + <id>FSP_BAR_SIZE</id> + </attribute> + <attribute> + <id>PHB_BASE_ADDRS</id> + </attribute> + <attribute> + <id>PCI_BASE_ADDRS_64</id> + </attribute> + <attribute> + <id>PCI_BASE_ADDRS_32</id> + </attribute> + <attribute> + <id>RNG_BAR_SIZE</id> + </attribute> + <attribute> + <id>IMT_BASE_ADDR</id> + </attribute> + <attribute> + <id>IMT_BAR_SIZE</id> + </attribute> + <attribute> + <id>VAS_HYPERVISOR_WINDOW_CONTEXT_ADDR</id> + </attribute> + <attribute> + <id>VAS_USER_WINDOW_CONTEXT_ADDR</id> + </attribute> + <attribute> + <id>NVIDIA_NPU_PRIVILEGED_ADDR</id> + </attribute> + <attribute> + <id>NVIDIA_NPU_USER_REG_ADDR</id> + </attribute> + <attribute> + <id>NVIDIA_PHY0_REG_ADDR</id> + </attribute> + <attribute> + <id>NVIDIA_PHY1_REG_ADDR</id> + </attribute> + <attribute> + <id>XIVE_CONTROLLER_BAR_ADDR</id> + </attribute> + <attribute> + <id>PSI_HB_ESB_ADDR</id> + </attribute> + <attribute> + <id>XIVE_THREAD_MGMT1_BAR_ADDR</id> + </attribute> + <attribute> + <id>NX_RNG_ADDR</id> + </attribute> + <attribute> + <id>ECID</id> + </attribute> + <attribute> + <id>XSCOM_BASE_ADDRESS</id> + </attribute> + <attribute> + <id>PSTATEGPE_BOOT_COPIER_IVPR_OFFSET</id> + </attribute> + <attribute> + <id>STOPGPE_BOOT_COPIER_IVPR_OFFSET</id> + </attribute> + <attribute> + <id>EQ_GARD</id> + </attribute> + <attribute> + <id>EC_GARD</id> + </attribute> + <attribute> + <id>I2C_BUS_DIV_REF</id> + </attribute> + <attribute> + <id>VCS_BOOT_VOLTAGE</id> + </attribute> + <attribute> + <id>VDN_BOOT_VOLTAGE</id> + </attribute> + <attribute> + <id>VDD_BOOT_VOLTAGE</id> + </attribute> + <attribute> + <id>VDD_AVSBUS_RAIL</id> + </attribute> + <attribute> + <id>VDD_AVSBUS_BUSNUM</id> + </attribute> + <attribute> + <id>VDN_AVSBUS_RAIL</id> + </attribute> + <attribute> + <id>VDN_AVSBUS_BUSNUM</id> + </attribute> + <attribute> + <id>VCS_AVSBUS_RAIL</id> + </attribute> + <attribute> + <id>VCS_AVSBUS_BUSNUM</id> + </attribute> + <attribute> + <id>CLOCK_PLL_MUX</id> + </attribute> + <attribute> + <id>CLOCK_PLL_MUX0</id> + </attribute> + <attribute> + <id>BOOT_FREQ_MULT</id> + </attribute> + <attribute> + <id>PFET_OFF_CONTROLS</id> + </attribute> + <attribute> + <id>MC_SYNC_MODE</id> + </attribute> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>OBUS_RATIO_VALUE</id> + </attribute> + <attribute> + <id>ISTEP_MODE</id> + </attribute> + <attribute> + <id>SBE_RUNTIME_MODE</id> + </attribute> + <attribute> + <id>IS_SP_MODE</id> + </attribute> + <attribute> + <id>SBE_FFDC_ENABLE</id> + </attribute> + <attribute> + <id>SBE_INTERNAL_FFDC_ENABLE</id> + </attribute> + <attribute> + <id>OCC_LFIR</id> + </attribute> + <attribute> + <id>PBA_LFIR</id> + </attribute> + <attribute> + <id>EXTERNAL_VRM_STEPSIZE</id> + </attribute> + <attribute> + <id>EXTERNAL_VRM_STEPDELAY</id> + </attribute> + <attribute> + <id>AVSBUS_FREQUENCY</id> + </attribute> + <attribute> + <id>PROC_FABRIC_X_ATTACHED_LINK_ID</id> + </attribute> + <attribute> + <id>PROC_FABRIC_X_ATTACHED_CHIP_ID</id> + </attribute> + <attribute> + <id>PROC_FABRIC_A_ATTACHED_LINK_ID</id> + </attribute> + <attribute> + <id>PROC_FABRIC_A_ATTACHED_CHIP_ID</id> + </attribute> + <attribute> + <id>PROC_FABRIC_X_LINK_DELAY</id> + </attribute> + <attribute> + <id>PROC_FABRIC_X_ADDR_DIS</id> + </attribute> + <attribute> + <id>PROC_FABRIC_X_AGGREGATE</id> + </attribute> + <attribute> + <id>PROC_FABRIC_A_LINK_DELAY</id> + </attribute> + <attribute> + <id>PROC_FABRIC_A_ADDR_DIS</id> + </attribute> + <attribute> + <id>PROC_FABRIC_A_AGGREGATE</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>PROC_NHTM_BAR_BASE_ADDR</id> + </attribute> + <attribute> + <id>PROC_NHTM_BAR_SIZE</id> + </attribute> + <attribute> + <id>PROC_CHTM_BAR_BASE_ADDR</id> + </attribute> + <attribute> + <id>PROC_CHTM_BAR_SIZES</id> + </attribute> + <attribute> + <id>NHTM_TRACE_TYPE</id> + </attribute> + <attribute> + <id>CHTM_TRACE_TYPE</id> + </attribute> + <attribute> + <id>HTMSC_TTYPEFILT_PAT</id> + </attribute> + <attribute> + <id>HTMSC_TSIZEFILT_PAT</id> + </attribute> + <attribute> + <id>HTMSC_TTYPEFILT_MASK</id> + </attribute> + <attribute> + <id>HTMSC_TSIZEFILT_MASK</id> + </attribute> + <attribute> + <id>HTMSC_TTYPEFILT_INVERT</id> + </attribute> + <attribute> + <id>HTMSC_CRESPFILT_INVERT</id> + </attribute> + <attribute> + <id>HTMSC_FILT_PAT</id> + </attribute> + <attribute> + <id>HTMSC_FILT_CRESP_PAT</id> + </attribute> + <attribute> + <id>HTMSC_FILT_MASK</id> + </attribute> + <attribute> + <id>HTMSC_FILT_CRESP_MASK</id> + </attribute> + <attribute> + <id>NHTM_HTMSC_MODE_CONTENT_SEL</id> + </attribute> + <attribute> + <id>NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES</id> + </attribute> + <attribute> + <id>NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL</id> + </attribute> + <attribute> + <id>NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE</id> + </attribute> + <attribute> + <id>NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION</id> + </attribute> + <attribute> + <id>NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD</id> + </attribute> + <attribute> + <id>NHTM_HTMSC_MODE_SYNC_STAMP_FORCE</id> + </attribute> + <attribute> + <id>NHTM_HTMSC_MODE_WRITETOIO</id> + </attribute> + <attribute> + <id>CHTM_HTMSC_MODE_CONTENT_SEL</id> + </attribute> + <attribute> + <id>CHTM_HTMSC_MODE_CAPTURE</id> + </attribute> + <attribute> + <id>CHTM_HTMSC_MODE_CORE_INSTR_STALL</id> + </attribute> + <attribute> + <id>HTMSC_MODE_WRAP</id> + </attribute> + <attribute> + <id>HTMSC_MODE_DIS_TSTAMP</id> + </attribute> + <attribute> + <id>HTMSC_MODE_SINGLE_TSTAMP</id> + </attribute> + <attribute> + <id>HTMSC_MODE_MARKERS_ONLY</id> + </attribute> + <attribute> + <id>HTMSC_MODE_DIS_FORCE_GROUP_SCOPE</id> + </attribute> + <attribute> + <id>HTMSC_MODE_VGTARGET</id> + </attribute> + <attribute> + <id>HTMSC_MEM_SCOPE</id> + </attribute> + <attribute> + <id>HTMSC_MEM_PRIORITY</id> + </attribute> + <attribute> + <id>NHTM_CTRL_TRIG</id> + </attribute> + <attribute> + <id>NHTM_CTRL_MARK</id> + </attribute> + <attribute> + <id>CHTM_CTRL_TRIG</id> + </attribute> + <attribute> + <id>CHTM_CTRL_MARK</id> + </attribute> + <attribute> + <id>HTMSC_CTRL_DBG0_STOP</id> + </attribute> + <attribute> + <id>HTMSC_CTRL_DBG1_STOP</id> + </attribute> + <attribute> + <id>HTMSC_CTRL_RUN_STOP</id> + </attribute> + <attribute> + <id>HTMSC_CTRL_OTHER_DBG0_STOP</id> + </attribute> + <attribute> + <id>HTMSC_CTRL_XSTOP_STOP</id> + </attribute> + <attribute> + <id>HTMSC_CTRL_CHIP0_STOP</id> + </attribute> + <attribute> + <id>HTMSC_CTRL_CHIP1_STOP</id> + </attribute> + <attribute> + <id>HTMSC_IMA_PDBAR_SPLIT_CORE_MODE</id> + </attribute> + <attribute> + <id>HTMSC_IMA_PDBAR_SCOPE</id> + </attribute> + <attribute> + <id>HTMSC_IMA_PDBAR_ADDR</id> + </attribute> + <attribute> + <id>PROC_FABRIC_SYSTEM_ID</id> + </attribute> + <attribute> + <id>PROC_OCC_SANDBOX_BASE_ADDR</id> + </attribute> + <attribute> + <id>CP_FILTER_BYPASS</id> + </attribute> + <attribute> + <id>SS_FILTER_BYPASS</id> + </attribute> + <attribute> + <id>IO_FILTER_BYPASS</id> + </attribute> + <attribute> + <id>DUMP_STOP_INFO_SUPPRESS_ERROR_TRACE</id> + </attribute> + <attribute> + <id>DUMP_STOP_INFO_ENABLE_ERRORLOG</id> + </attribute> + <attribute> + <default>32</default> + <id>DATA_CACHE_SIZE</id> + </attribute> + <attribute> + <default>10240</default> + <id>L3_CACHE_SIZE</id> + </attribute> + <attribute> + <default>8</default> + <id>ICACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <default>1024</default> + <id>TLB_DATA_ENTRIES</id> + </attribute> + <attribute> + <default>0</default> + <id>TLB_INSTR_ENTRIES</id> + </attribute> + <attribute> + <default>4</default> + <id>TLB_DATA_ASSOC_SETS</id> + </attribute> + <attribute> + <default>0</default> + <id>TLB_INSTR_ASSOC_SETS</id> + </attribute> + <attribute> + <default>128</default> + <id>TLB_RESERVE_SIZE</id> + </attribute> + <attribute> + <default>128</default> + <id>DATA_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <default>128</default> + <id>L3_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <default>128</default> + <id>DCACHE_LINE_SIZE</id> + </attribute> + <attribute> + <default>8</default> + <id>DCACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <default>128</default> + <id>ICACHE_BLOCK_SIZE</id> + </attribute> + <attribute> + <default>32</default> + <id>ICACHE_SIZE</id> + </attribute> + <attribute> + <default>128</default> + <id>ICACHE_LINE_SIZE</id> + </attribute> + <attribute> + <default>0x0000001D</default> + <id>CPU_ATTR</id> + </attribute> + <attribute> + <default>128</default> + <id>L2_CACHE_LINE_SIZE</id> + </attribute> + <attribute> + <default>512</default> + <id>L2_CACHE_SIZE</id> + </attribute> + <attribute> + <default>8</default> + <id>L2_CACHE_ASSOC_SETS</id> + </attribute> + <attribute> + <id>BOOT_FREQ_MHZ</id> + </attribute> + <attribute> + <id>PROC_NPU_PHY0_BAR_ENABLE</id> + </attribute> + <attribute> + <id>PROC_NPU_PHY1_BAR_ENABLE</id> + </attribute> + <attribute> + <id>PROC_NPU_MMIO_BAR_ENABLE</id> + </attribute> + <attribute> + <id>PROC_NX_RNG_BAR_ENABLE</id> + </attribute> + <attribute> + <id>PROC_FSP_BAR_ENABLE</id> + </attribute> + <attribute> + <id>PROC_PSI_BRIDGE_BAR_ENABLE</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_PC_BAR_ENABLE</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_VC_BAR_ENABLE</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_TM1_BAR_ENABLE</id> + </attribute> + <attribute> + <id>PROC_INT_CQ_IC_BAR_ENABLE</id> + </attribute> + <attribute> + <id>PROC_NX_RNG_FAILED_INT_ENABLE</id> + </attribute> + <attribute> + <id>PROC_NX_RNG_FAILED_INT_ADDR</id> + </attribute> + <attribute> + <id>NEST_MEM_X_O_PCI_BYPASS</id> + </attribute> + <attribute> + <id>DPLL_BYPASS</id> + </attribute> + <attribute> + <id>FREQ_BIAS_ULTRATURBO</id> + </attribute> + <attribute> + <id>FREQ_BIAS_TURBO</id> + </attribute> + <attribute> + <id>FREQ_BIAS_NOMINAL</id> + </attribute> + <attribute> + <id>FREQ_BIAS_POWERSAVE</id> + </attribute> + <attribute> + <id>VOLTAGE_EXT_VDD_BIAS_ULTRATURBO</id> + </attribute> + <attribute> + <id>VOLTAGE_EXT_VDD_BIAS_TURBO</id> + </attribute> + <attribute> + <id>VOLTAGE_EXT_VDD_BIAS_NOMINAL</id> + </attribute> + <attribute> + <id>VOLTAGE_EXT_VDD_BIAS_POWERSAVE</id> + </attribute> + <attribute> + <id>VOLTAGE_EXT_VCS_BIAS</id> + </attribute> + <attribute> + <id>VOLTAGE_EXT_VDN_BIAS</id> + </attribute> + <attribute> + <id>VOLTAGE_INT_VDD_BIAS_ULTRATURBO</id> + </attribute> + <attribute> + <id>VOLTAGE_INT_VDD_BIAS_TURBO</id> + </attribute> + <attribute> + <id>VOLTAGE_INT_VDD_BIAS_NOMINAL</id> + </attribute> + <attribute> + <id>VOLTAGE_INT_VDD_BIAS_POWERSAVE</id> + </attribute> + <attribute> + <id>TDP_RDP_CURRENT_FACTOR</id> + </attribute> + <attribute> + <id>SYSTEM_RESCLK_FREQ_REGIONS</id> + </attribute> + <attribute> + <id>SYSTEM_RESCLK_FREQ_REGION_INDEX</id> + </attribute> + <attribute> + <id>SYSTEM_RESCLK_VALUE</id> + </attribute> + <attribute> + <id>SYSTEM_RESCLK_L3_VALUE</id> + </attribute> + <attribute> + <id>SYSTEM_RESCLK_L3_VOLTAGE_THRESHOLD_MV</id> + </attribute> + <attribute> + <id>NEST_VDD_ID</id> + </attribute> + <attribute> + <id>NEST_VDN_ID</id> + </attribute> + <attribute> + <id>NEST_VCS_ID</id> + </attribute> + <attribute> + <id>NEST_VIO_ID</id> + </attribute> + <attribute> + <id>NEST_VDDR_ID</id> + </attribute> + <attribute> + <id>MSS_FREQ</id> + </attribute> + <attribute> + <id>WAIT_N2</id> + </attribute> + <attribute> + <id>WAIT_N1</id> + </attribute> + <attribute> + <id>WAIT_N0</id> + </attribute> + <attribute> + <id>START_SEEPROM_ADDR</id> + </attribute> + <attribute> + <id>MASTER_CORE</id> + </attribute> + <attribute> + <id>MASTER_EX</id> + </attribute> + <attribute> + <id>CHIP_REGIONS_TO_ENABLE</id> + </attribute> + <attribute> + <id>PROC_PB_BNDY_DMIPLL_DATA</id> + </attribute> + <attribute> + <id>MB_BIT_RATE_DIVISOR_PLL</id> + </attribute> + <attribute> + <id>LEN_OF_SEEPROM_DATA</id> + </attribute> + <attribute> + <id>BRANCH_PIBMEM_ADDR</id> + </attribute> + <attribute> + <id>I2C_BUS_DIV_NEST</id> + </attribute> + <attribute> + <id>VCS_I2C_RAIL</id> + </attribute> + <attribute> + <id>START_PIBMEM_ADDR</id> + </attribute> + <attribute> + <id>VCS_I2C_BUSNUM</id> + </attribute> + <attribute> + <id>PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA</id> + </attribute> + <attribute> + <id>MB_BIT_RATE_DIVISOR_REFCLK</id> + </attribute> + <attribute> + <id>WAIT_N3</id> + </attribute> + <attribute> + <id>PROC_PERV_BNDY_PLL_DATA</id> + </attribute> + <attribute> + <id>DEVICE_ID</id> + </attribute> + <attribute> + <id>TOD_CPU_DATA</id> + </attribute> + <attribute> + <id>PM_SPWUP_IGNORE_XSTOP_FLAG</id> + </attribute> + <attribute> + <id>SECUREBOOT_PROTECT_DECONFIGURED_TPM</id> + </attribute> + <attribute> + <id>CME_INSTRUCTION_TRACE_ENABLE</id> + </attribute> + <attribute> + <id>DO_MSS_WR_VREF</id> + </attribute> + <attribute> + <id>DO_MSS_VREF_DAC</id> + </attribute> + <attribute> + <id>DO_MSS_TRAINING_BAD_BITS</id> + </attribute> + <attribute> + <id>CME_CHTM_TRACE_ENABLE</id> + </attribute> + <attribute> + <id>CME_CHTM_TRACE_MEMORY_CONFIG</id> + </attribute> + <attribute><id>FSP_BASE_ADDR</id></attribute> + <attribute><id>PSI_BRIDGE_BASE_ADDR</id></attribute> + <attribute><id>INTP_BASE_ADDR</id></attribute> + <attribute><id>PROC_DCM_INSTALLED</id></attribute> + <attribute><id>SBE_IS_STARTED</id></attribute> + <attribute><id>PROC_PCIE_PHB_ACTIVE</id></attribute> + <attribute><id>PROC_LPC_BAR_BASE_ADDR_OFFSET</id></attribute> + <attribute><id>LPC_BUS_ADDR</id></attribute> + <attribute><id>PRD_HWP_PLID</id></attribute> +</targetType> - <!-- From PHYP Memory Map --> - <attribute><id>NPU_MMIO_BAR_BASE_ADDR</id></attribute> - <attribute><id>NPU_MMIO_BAR_SIZE</id></attribute> - <attribute><id>FSP_BASE_ADDR</id></attribute> - <attribute><id>FSP_BAR_SIZE</id></attribute> - <attribute><id>PSI_BRIDGE_BASE_ADDR</id></attribute> - <attribute><id>INTP_BASE_ADDR</id></attribute> - <attribute><id>PHB_BASE_ADDRS</id></attribute> - <attribute><id>PCI_BASE_ADDRS_64</id></attribute> - <attribute><id>PCI_BASE_ADDRS_32</id></attribute> - <attribute><id>MEM_BASE</id></attribute> - <attribute><id>MIRROR_BASE</id></attribute> - <attribute><id>RNG_BAR_SIZE</id></attribute> - <attribute><id>IMT_BASE_ADDR</id></attribute> - <attribute><id>IMT_BAR_SIZE</id></attribute> - <attribute><id>VAS_HYPERVISOR_WINDOW_CONTEXT_ADDR</id></attribute> - <attribute><id>VAS_USER_WINDOW_CONTEXT_ADDR</id></attribute> - <attribute><id>LPC_BUS_ADDR</id></attribute> - <attribute><id>NVIDIA_NPU_PRIVILEGED_ADDR</id></attribute> - <attribute><id>NVIDIA_NPU_USER_REG_ADDR</id></attribute> - <attribute><id>NVIDIA_PHY0_REG_ADDR</id></attribute> - <attribute><id>NVIDIA_PHY1_REG_ADDR</id></attribute> - <attribute><id>XIVE_CONTROLLER_BAR_ADDR</id></attribute> - <attribute><id>PSI_HB_ESB_ADDR</id></attribute> - <attribute><id>XIVE_THREAD_MGMT1_BAR_ADDR</id></attribute> - <attribute><id>NX_RNG_ADDR</id></attribute> - <!-- end Memory Map --> - - <attribute><id>ECID</id></attribute> - <attribute><id>I2C_SLAVE_ADDRESS</id></attribute> - <attribute> - <id>PROC_PCIE_NUM_PHB</id> - <default>6</default> - </attribute> - <attribute> - <id>PROC_PCIE_NUM_IOP</id> - <default>3</default> - </attribute> - <attribute> - <id>PROC_PCIE_NUM_PEC</id> - <default>3</default> - </attribute> - <attribute> - <id>PROC_PCIE_NUM_LANES</id> - <default>48</default> - </attribute> - <attribute><id>PROC_PCIE_PHB_ACTIVE</id></attribute> - <attribute><id>PROC_DCM_INSTALLED</id></attribute> - <attribute><id>XSCOM_BASE_ADDRESS</id></attribute> - <attribute><id>PROC_LPC_BAR_BASE_ADDR_OFFSET</id></attribute> - <attribute><id>PSTATEGPE_BOOT_COPIER_IVPR_OFFSET</id></attribute> - <attribute><id>STOPGPE_BOOT_COPIER_IVPR_OFFSET</id></attribute> - <attribute><id>EQ_GARD</id></attribute> - <attribute><id>EC_GARD</id></attribute> - <attribute><id>I2C_BUS_DIV_REF</id></attribute> - <attribute><id>I2C_BUS_DIV_REF_VALID</id></attribute> - <attribute><id>NODE_POS</id></attribute> - <attribute><id>BOOT_FREQ</id></attribute> - <attribute><id>VCS_BOOT_VOLTAGE</id></attribute> - <attribute><id>VDN_BOOT_VOLTAGE</id></attribute> - <attribute><id>VDD_BOOT_VOLTAGE</id></attribute> - <attribute><id>VDD_AVSBUS_RAIL</id></attribute> - <attribute><id>VDD_AVSBUS_BUSNUM</id></attribute> - <attribute><id>VDN_AVSBUS_RAIL</id></attribute> - <attribute><id>VDN_AVSBUS_BUSNUM</id></attribute> - <attribute><id>VCS_AVSBUS_RAIL</id></attribute> - <attribute><id>VCS_AVSBUS_BUSNUM</id></attribute> - <attribute><id>CHIP_POS</id></attribute> - <attribute><id>CLOCK_PLL_MUX</id></attribute> - <attribute><id>CLOCK_PLL_MUX0</id></attribute> - <attribute><id>BOOT_FREQ_MULT</id></attribute> - <attribute><id>PFET_OFF_CONTROLS</id></attribute> - <attribute><id>MC_SYNC_MODE</id></attribute> - <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute> - <attribute><id>OBUS_RATIO_VALUE</id></attribute> - <attribute><id>OB0_PLL_BUCKET</id></attribute> - <attribute><id>OB1_PLL_BUCKET</id></attribute> - <attribute><id>OB2_PLL_BUCKET</id></attribute> - <attribute><id>OB3_PLL_BUCKET</id></attribute> - <attribute><id>FREQ_O_MHZ</id></attribute> - <attribute><id>FUNCTIONAL_EQ_EC_VALID</id></attribute> - <attribute><id>FW_MODE_FLAGS_VALID</id></attribute> - <attribute><id>ISTEP_MODE</id></attribute> - <attribute><id>SBE_RUNTIME_MODE</id></attribute> - <attribute><id>IS_SP_MODE</id></attribute> - <attribute><id>SBE_FFDC_ENABLE</id></attribute> - <attribute><id>SBE_INTERNAL_FFDC_ENABLE</id></attribute> - <attribute><id>BOOT_FREQUENCY_VALID</id></attribute> - <attribute><id>HWP_CONTROL_FLAGS_VALID</id></attribute> - <attribute><id>CHIP_SELECTION_VALID</id></attribute> - <attribute><id>CHIP_SELECTION</id></attribute> - <attribute><id>SCRATCH6_VALID</id></attribute> - <attribute><id>SCRATCH7_VALID</id></attribute> - <attribute><id>OCC_LFIR</id></attribute> - <attribute><id>PBA_LFIR</id></attribute> - <attribute><id>EXTERNAL_VRM_STEPSIZE</id></attribute> - <attribute><id>EXTERNAL_VRM_STEPDELAY</id></attribute> - <attribute><id>AVSBUS_FREQUENCY</id></attribute> - <!-- proc_fbc_eff_config_links --> - <attribute><id>PROC_FABRIC_X_ATTACHED_LINK_ID</id></attribute> - <attribute><id>PROC_FABRIC_X_ATTACHED_CHIP_ID</id></attribute> - <attribute><id>PROC_FABRIC_A_ATTACHED_LINK_ID</id></attribute> - <attribute><id>PROC_FABRIC_A_ATTACHED_CHIP_ID</id></attribute> - <attribute><id>PROC_FABRIC_X_LINK_DELAY</id></attribute> - <attribute><id>PROC_FABRIC_X_ADDR_DIS</id></attribute> - <attribute><id>PROC_FABRIC_X_AGGREGATE</id></attribute> - <attribute><id>PROC_FABRIC_A_LINK_DELAY</id></attribute> - <attribute><id>PROC_FABRIC_A_ADDR_DIS</id></attribute> - <attribute><id>PROC_FABRIC_A_AGGREGATE</id></attribute> - <!-- End proc_fbc_eff_config_links --> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>PROC_NHTM_BAR_BASE_ADDR</id></attribute> - <attribute><id>PROC_NHTM_BAR_SIZE</id></attribute> - <attribute><id>PROC_CHTM_BAR_BASE_ADDR</id></attribute> - <attribute><id>PROC_CHTM_BAR_SIZES</id></attribute> - <attribute><id>NHTM_TRACE_TYPE</id></attribute> - <attribute><id>CHTM_TRACE_TYPE</id></attribute> - <attribute><id>HTMSC_TTYPEFILT_PAT</id></attribute> - <attribute><id>HTMSC_TSIZEFILT_PAT</id></attribute> - <attribute><id>HTMSC_TTYPEFILT_MASK</id></attribute> - <attribute><id>HTMSC_TSIZEFILT_MASK</id></attribute> - <attribute><id>HTMSC_TTYPEFILT_INVERT</id></attribute> - <attribute><id>HTMSC_CRESPFILT_INVERT</id></attribute> - <attribute><id>HTMSC_FILT_PAT</id></attribute> - <attribute><id>HTMSC_FILT_CRESP_PAT</id></attribute> - <attribute><id>HTMSC_FILT_MASK</id></attribute> - <attribute><id>HTMSC_FILT_CRESP_MASK</id></attribute> - <attribute><id>NHTM_HTMSC_MODE_CONTENT_SEL</id></attribute> - <attribute><id>NHTM_HTMSC_MODE_CAPTURE_GENERATED_WRITES</id></attribute> - <attribute><id>NHTM_HTMSC_MODE_CAPTURE_ENABLE_FILTER_ALL</id></attribute> - <attribute><id>NHTM_HTMSC_MODE_CAPTURE_PRECISE_CRESP_MODE</id></attribute> - <attribute><id>NHTM_HTMSC_MODE_CAPTURE_LIMIT_MEM_ALLOCATION</id></attribute> - <attribute><id>NHTM_HTMSC_MODE_CAPTURE_PMISC_ONLY_CMD</id></attribute> - <attribute><id>NHTM_HTMSC_MODE_SYNC_STAMP_FORCE</id></attribute> - <attribute><id>NHTM_HTMSC_MODE_WRITETOIO</id></attribute> - <attribute><id>CHTM_HTMSC_MODE_CONTENT_SEL</id></attribute> - <attribute><id>CHTM_HTMSC_MODE_CAPTURE</id></attribute> - <attribute><id>CHTM_HTMSC_MODE_CORE_INSTR_STALL</id></attribute> - <attribute><id>HTMSC_MODE_WRAP</id></attribute> - <attribute><id>HTMSC_MODE_DIS_TSTAMP</id></attribute> - <attribute><id>HTMSC_MODE_SINGLE_TSTAMP</id></attribute> - <attribute><id>HTMSC_MODE_MARKERS_ONLY</id></attribute> - <attribute><id>HTMSC_MODE_DIS_FORCE_GROUP_SCOPE</id></attribute> - <attribute><id>HTMSC_MODE_VGTARGET</id></attribute> - <attribute><id>HTMSC_MEM_SCOPE</id></attribute> - <attribute><id>HTMSC_MEM_PRIORITY</id></attribute> - <attribute><id>NHTM_CTRL_TRIG</id></attribute> - <attribute><id>NHTM_CTRL_MARK</id></attribute> - <attribute><id>CHTM_CTRL_TRIG</id></attribute> - <attribute><id>CHTM_CTRL_MARK</id></attribute> - <attribute><id>HTMSC_CTRL_DBG0_STOP</id></attribute> - <attribute><id>HTMSC_CTRL_DBG1_STOP</id></attribute> - <attribute><id>HTMSC_CTRL_RUN_STOP</id></attribute> - <attribute><id>HTMSC_CTRL_OTHER_DBG0_STOP</id></attribute> - <attribute><id>HTMSC_CTRL_XSTOP_STOP</id></attribute> - <attribute><id>HTMSC_CTRL_CHIP0_STOP</id></attribute> - <attribute><id>HTMSC_CTRL_CHIP1_STOP</id></attribute> - <attribute><id>HTMSC_IMA_PDBAR_SPLIT_CORE_MODE</id></attribute> - <attribute><id>HTMSC_IMA_PDBAR_SCOPE</id></attribute> - <attribute><id>HTMSC_IMA_PDBAR_ADDR</id></attribute> - <attribute><id>PROC_FABRIC_SYSTEM_ID</id></attribute> - <attribute><id>PROC_OCC_SANDBOX_BASE_ADDR</id></attribute> - <attribute><id>CP_FILTER_BYPASS</id></attribute> - <attribute><id>SS_FILTER_BYPASS</id></attribute> - <attribute><id>IO_FILTER_BYPASS</id></attribute> - <attribute><id>DUMP_STOP_INFO_SUPPRESS_ERROR_TRACE</id></attribute> - <attribute><id>DUMP_STOP_INFO_ENABLE_ERRORLOG</id></attribute> - <attribute><id>SBE_IS_STARTED</id></attribute> - <attribute><id>HTM_QUEUES</id></attribute> - <attribute><id>CORE_THROTTLE_ASSERT_COUNT</id></attribute> - <attribute><id>CORE_THROTTLE_DEASSERT_COUNT</id></attribute> - - <!-- Processor characteristics for HDAT --> - <attribute> - <id>DATA_CACHE_SIZE</id> - <default>32</default><!-- 32KB --> - </attribute> - <attribute> - <id>L3_CACHE_SIZE</id> - <default>10240</default><!-- 10MB --> - </attribute> - <attribute> - <id>ICACHE_ASSOC_SETS</id> - <default>8</default><!-- 8-way associativity --> - </attribute> - <attribute> - <id>TLB_DATA_ENTRIES</id> - <default>1024</default> - </attribute> - <attribute> - <id>TLB_INSTR_ENTRIES</id> - <default>0</default> - </attribute> - <attribute> - <id>TLB_DATA_ASSOC_SETS</id> - <default>4</default> - </attribute> - <attribute> - <id>TLB_INSTR_ASSOC_SETS</id> - <default>0</default> - </attribute> - <attribute> - <id>TLB_RESERVE_SIZE</id> - <default>128</default> - </attribute> - <attribute> - <id>DATA_CACHE_LINE_SIZE</id> - <default>128</default> - </attribute> - <attribute> - <id>L3_CACHE_LINE_SIZE</id> - <default>128</default> - </attribute> - <attribute> - <id>DCACHE_LINE_SIZE</id> - <default>128</default> - </attribute> - <attribute> - <id>DCACHE_ASSOC_SETS</id> - <default>8</default> - </attribute> - <attribute> - <id>ICACHE_BLOCK_SIZE</id> - <default>128</default> - </attribute> - <attribute> - <id>ICACHE_SIZE</id> - <default>32</default> - </attribute> - <attribute> - <id>ICACHE_LINE_SIZE</id> - <default>128</default> - </attribute> - <attribute> - <id>CPU_ATTR</id> - <default>0x0000001D</default> - </attribute> - <attribute> - <id>L2_CACHE_LINE_SIZE</id> - <default>128</default> - </attribute> - <attribute> - <id>L2_CACHE_SIZE</id> - <default>512</default> - </attribute> - <attribute> - <id>L2_CACHE_ASSOC_SETS</id> - <default>8</default> - </attribute> - <!-- End processor characteristics for HDAT --> - <attribute><id>LPC_BASE_ADDR</id></attribute> - <attribute><id>BOOT_FREQ_MHZ</id></attribute> - -<!-- p9_setup_bars - Begin --> - <attribute><id>PROC_NPU_PHY0_BAR_ENABLE</id></attribute> - <attribute><id>PROC_NPU_PHY1_BAR_ENABLE</id></attribute> - <attribute><id>PROC_NPU_MMIO_BAR_ENABLE</id></attribute> - <attribute><id>PROC_NX_RNG_BAR_ENABLE</id></attribute> - <attribute><id>PROC_FSP_BAR_ENABLE</id></attribute> - <attribute><id>PROC_PSI_BRIDGE_BAR_ENABLE</id></attribute> - <attribute><id>PROC_INT_CQ_PC_BAR_ENABLE</id></attribute> - <attribute><id>PROC_INT_CQ_VC_BAR_ENABLE</id></attribute> - <attribute><id>PROC_INT_CQ_TM1_BAR_ENABLE</id></attribute> - <attribute><id>PROC_INT_CQ_IC_BAR_ENABLE</id></attribute> -<!-- p9_setup_bars - End --> - - <attribute><id>PROC_NX_RNG_FAILED_INT_ENABLE</id></attribute> - <attribute><id>PROC_NX_RNG_FAILED_INT_ADDR</id></attribute> - <attribute><id>NEST_MEM_X_O_PCI_BYPASS</id></attribute> - <attribute><id>DPLL_BYPASS</id></attribute> - <attribute><id>FREQ_BIAS_ULTRATURBO</id></attribute> - <attribute><id>FREQ_BIAS_TURBO</id></attribute> - <attribute><id>FREQ_BIAS_NOMINAL</id></attribute> - <attribute><id>FREQ_BIAS_POWERSAVE</id></attribute> - <attribute><id>VOLTAGE_EXT_VDD_BIAS_ULTRATURBO</id></attribute> - <attribute><id>VOLTAGE_EXT_VDD_BIAS_TURBO</id></attribute> - <attribute><id>VOLTAGE_EXT_VDD_BIAS_NOMINAL</id></attribute> - <attribute><id>VOLTAGE_EXT_VDD_BIAS_POWERSAVE</id></attribute> - <attribute><id>VOLTAGE_EXT_VCS_BIAS</id></attribute> - <attribute><id>VOLTAGE_EXT_VDN_BIAS</id></attribute> - <attribute><id>VOLTAGE_INT_VDD_BIAS_ULTRATURBO</id></attribute> - <attribute><id>VOLTAGE_INT_VDD_BIAS_TURBO</id></attribute> - <attribute><id>VOLTAGE_INT_VDD_BIAS_NOMINAL</id></attribute> - <attribute><id>VOLTAGE_INT_VDD_BIAS_POWERSAVE</id></attribute> - <attribute><id>TDP_RDP_CURRENT_FACTOR</id></attribute> - <attribute><id>SYSTEM_RESCLK_FREQ_REGIONS</id></attribute> - <attribute><id>SYSTEM_RESCLK_FREQ_REGION_INDEX</id></attribute> - <attribute><id>SYSTEM_RESCLK_VALUE</id></attribute> - <attribute><id>SYSTEM_RESCLK_L3_VALUE</id></attribute> - <attribute><id>SYSTEM_RESCLK_L3_VOLTAGE_THRESHOLD_MV</id></attribute> - - <!-- Process Voltage Rail Ids --> - <attribute><id>NEST_VDD_ID</id></attribute> - <attribute><id>NEST_VDN_ID</id></attribute> - <attribute><id>NEST_VCS_ID</id></attribute> - <attribute><id>NEST_VIO_ID</id></attribute> - <attribute><id>NEST_VDDR_ID</id></attribute> - <attribute><id>MSS_FREQ</id></attribute> - <attribute><id>WAIT_N2</id></attribute> - <attribute><id>WAIT_N1</id></attribute> - <attribute><id>WAIT_N0</id></attribute> - <attribute><id>START_SEEPROM_ADDR</id></attribute> - <attribute><id>MASTER_CORE</id></attribute> - <attribute><id>MASTER_EX</id></attribute> - <attribute><id>CHIP_REGIONS_TO_ENABLE</id></attribute> - <attribute><id>PROC_PB_BNDY_DMIPLL_DATA</id></attribute> - <attribute><id>MB_BIT_RATE_DIVISOR_PLL</id></attribute> - <attribute><id>LEN_OF_SEEPROM_DATA</id></attribute> - <attribute><id>BRANCH_PIBMEM_ADDR</id></attribute> - <attribute><id>I2C_BUS_DIV_NEST</id></attribute> - <attribute><id>VCS_I2C_RAIL</id></attribute> - <attribute><id>START_PIBMEM_ADDR</id></attribute> - <attribute><id>VCS_I2C_BUSNUM</id></attribute> - <attribute><id>PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA</id></attribute> - <attribute><id>MB_BIT_RATE_DIVISOR_REFCLK</id></attribute> - <attribute><id>WAIT_N3</id></attribute> - <attribute><id>PROC_PERV_BNDY_PLL_DATA</id></attribute> - <attribute><id>DEVICE_ID</id></attribute> - <attribute><id>TOD_CPU_DATA</id></attribute> - <attribute><id>PM_SPWUP_IGNORE_XSTOP_FLAG</id></attribute> - <attribute><id>SECUREBOOT_PROTECT_DECONFIGURED_TPM</id></attribute> - <attribute><id>CME_INSTRUCTION_TRACE_ENABLE</id></attribute> - <attribute><id>MSS_RUN_DCD_CALIBRATION</id></attribute> - <!-- START memory workaround for DD1.02 --> - <attribute><id>DO_MSS_WR_VREF</id></attribute> - <attribute><id>DO_MSS_VREF_DAC</id></attribute> - <attribute><id>DO_MSS_TRAINING_BAD_BITS</id></attribute> - <!-- END memory workaround for DD1.02 --> - <attribute><id>CME_CHTM_TRACE_ENABLE</id></attribute> - <attribute><id>CME_CHTM_TRACE_MEMORY_CONFIG</id></attribute> - <attribute><id>PRD_HWP_PLID</id></attribute> - <attribute><id>VDM_VID_COMPARE_BIAS_0P5PCT</id></attribute> - -</targetType><!-- chip-processor-power9 --> - -<!-- chip-processor-nimbus --> -<targetType> - <id>chip-processor-nimbus</id> - <parent>chip-processor-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> -</targetType><!-- chip-processor-nimbus --> +<targetType> + <id>chip-processor-nimbus</id> + <parent>chip-processor-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> +</targetType> -<!-- chip-processor-cumulus --> <targetType> - <id>chip-processor-cumulus</id> - <parent>chip-processor-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>chip-processor-cumulus</id> + <parent>chip-processor-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- p9 sub-units --> @@ -1388,71 +2374,139 @@ 6 EQs on Nimbus Quad: 2 ex's and one ep --> <targetType> - <id>unit-eq-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>EQ</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!-- GARD --> - </attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>POUNDV_BUCKET_NUM</id><default>0</default></attribute> - <attribute><id>POUNDV_BUCKET_NUM_OVERRIDE</id><default>0</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - <attribute><id>CDM_DOMAIN</id><default>CPU</default></attribute> - <attribute><id>QUAD_PPM_ERRMASK</id></attribute> - <attribute><id>SENSEADJ_STEP</id></attribute> + <id>unit-eq-power9</id> + <parent>unit</parent> + <attribute> + <default>EQ</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000001</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <default>0</default> + <id>POUNDV_BUCKET_NUM</id> + </attribute> + <attribute> + <default>0</default> + <id>POUNDV_BUCKET_NUM_OVERRIDE</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>CPU</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>QUAD_PPM_ERRMASK</id> + </attribute> + <attribute> + <id>SENSEADJ_STEP</id> + </attribute> </targetType> <!-- EX: Use same EX target for both Nimbus and Cumulus 2 EXs per EQ EX (L2/L3, 2x Core) --> <targetType> - <id>unit-ex-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>EX</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!-- GARD --> - </attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>CDM_DOMAIN</id><default>CPU</default></attribute> - <attribute><id>CME_LOCAL_FIRMASK</id></attribute> - <attribute><id>L2_HASCLOCKS</id></attribute> - <attribute><id>L3_HASCLOCKS</id></attribute> - <attribute><id>C0_EXEC_HASCLOCKS</id></attribute> - <attribute><id>C1_EXEC_HASCLOCKS</id></attribute> - <attribute><id>C0_PC_HASCLOCKS</id></attribute> - <attribute><id>C1_PC_HASCLOCKS</id></attribute> - <attribute><id>L2_HASPOWER</id></attribute> - <attribute><id>L3_HASPOWER</id></attribute> - <attribute><id>C0_HASPOWER</id></attribute> - <attribute><id>C1_HASPOWER</id></attribute> + <id>unit-ex-power9</id> + <parent>unit</parent> + <attribute> + <default>EX</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000001</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <default>CPU</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>CME_LOCAL_FIRMASK</id> + </attribute> + <attribute> + <id>L2_HASCLOCKS</id> + </attribute> + <attribute> + <id>L3_HASCLOCKS</id> + </attribute> + <attribute> + <id>C0_EXEC_HASCLOCKS</id> + </attribute> + <attribute> + <id>C1_EXEC_HASCLOCKS</id> + </attribute> + <attribute> + <id>C0_PC_HASCLOCKS</id> + </attribute> + <attribute> + <id>C1_PC_HASCLOCKS</id> + </attribute> + <attribute> + <id>L2_HASPOWER</id> + </attribute> + <attribute> + <id>L3_HASPOWER</id> + </attribute> + <attribute> + <id>C0_HASPOWER</id> + </attribute> + <attribute> + <id>C1_HASPOWER</id> + </attribute> </targetType> <!-- CORE: Use same CORE target for both Nimbus and Cumulus A collection of 4 threads --> <targetType> - <id>unit-core-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>CORE</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!-- GARD --> - </attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - <attribute><id>CDM_DOMAIN</id><default>CPU</default></attribute> - <attribute><id>CORE_PPM_ERRMASK</id></attribute> + <id>unit-core-power9</id> + <parent>unit</parent> + <attribute> + <default>CORE</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000001</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>CPU</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>CORE_PPM_ERRMASK</id> + </attribute> </targetType> <!-- MCS @@ -1460,471 +2514,1019 @@ (MCUnit left has two, MCUnit right has two) Cumulus: None --> <targetType> - <id>unit-mcs-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>MCS</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000003</default> <!-- GARD | MEMDIAG --> - </attribute> - <attribute><id>EEPROM_VPD_PRIMARY_INFO</id></attribute> - <attribute><id>IBSCOM_MCS_BASE_ADDR</id></attribute> - <attribute><id>EI_BUS_TX_MSBSWAP</id></attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - <attribute><id>MSS_DIMM_MFG_ID_CODE</id></attribute> - <attribute><id>EFF_NUM_RANKS_PER_DIMM</id></attribute> - <attribute><id>EFF_DRAM_WIDTH</id></attribute> - <attribute><id>EFF_DRAM_RANK_MIX</id></attribute> - <attribute><id>EFF_DIMM_SPARE</id></attribute> - <attribute><id>EFF_DRAM_WR_VREF</id></attribute> - <attribute><id>EFF_DRAM_WR_VREF_SCHMOO</id></attribute> - <attribute><id>EFF_DRAM_WRDDR4_VREF_SCHMOO</id></attribute> - <attribute><id>EFF_DIMM_SIZE</id></attribute> - <attribute><id>EFF_DRAM_CL</id></attribute> - <attribute><id>EFF_DRAM_AL</id></attribute> - <attribute><id>EFF_DRAM_CWL</id></attribute> - <attribute><id>EFF_DRAM_RBT</id></attribute> - <attribute><id>EFF_DRAM_TM</id></attribute> - <attribute><id>EFF_DRAM_DLL_RESET</id></attribute> - <attribute><id>EFF_DRAM_DLL_PPD</id></attribute> - <attribute><id>EFF_DRAM_DLL_ENABLE</id></attribute> - <attribute><id>EFF_DRAM_WR_LVL_ENABLE</id></attribute> - <attribute><id>EFF_DRAM_OUTPUT_BUFFER</id></attribute> - <attribute><id>EFF_DRAM_PASR</id></attribute> - <attribute><id>EFF_DRAM_ASR</id></attribute> - <attribute><id>EFF_DRAM_SRT</id></attribute> - <attribute><id>EFF_MPR_LOC</id></attribute> - <attribute><id>EFF_MPR_MODE</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC00</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC01</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC02</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC03</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC04</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC05</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC06_07</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC08</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC09</id></attribute> - <!--HWSV needs to update names so we can remove this--> - <attribute><id>EFF_DIMM_DDR4_RC10</id></attribute> - <!--HWSV needs to update names so we can remove this--> - <attribute><id>EFF_DIMM_DDR4_RC11</id></attribute> - <!--HWSV needs to update names so we can remove this--> - <attribute><id>EFF_DIMM_DDR4_RC12</id></attribute> - <!--HWSV needs to update names so we can remove this--> - <attribute><id>EFF_DIMM_DDR4_RC13</id></attribute> - <!--HWSV needs to update names so we can remove this--> - <attribute><id>EFF_DIMM_DDR4_RC14</id></attribute> - <!--HWSV needs to update names so we can remove this--> - <attribute><id>EFF_DIMM_DDR4_RC15</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC0A</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC0B</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC0C</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC0D</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC0E</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC0F</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC_1x</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC_2x</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC_3x</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC_4x</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC_5x</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC_6x</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC_7x</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC_8x</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC_9x</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC_Ax</id></attribute> - <attribute><id>EFF_DIMM_DDR4_RC_Bx</id></attribute> - <attribute><id>EFF_DIMM_RCD_MIRROR_MODE</id></attribute> - <attribute><id>EFF_SCHMOO_MODE</id></attribute> - <attribute><id>EFF_SCHMOO_ADDR_MODE</id></attribute> - <attribute><id>EFF_SCHMOO_TEST_VALID</id></attribute> - <attribute><id>EFF_SCHMOO_PARAM_VALID</id></attribute> - <attribute><id>EFF_SCHMOO_WR_EYE_MIN_MARGIN</id></attribute> - <attribute><id>EFF_SCHMOO_RD_EYE_MIN_MARGIN</id></attribute> - <attribute><id>EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id></attribute> - <attribute><id>EFF_SCHMOO_RD_GATE_MIN_MARGIN</id></attribute> - <attribute><id>EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id></attribute> - <attribute><id>EFF_MEMCAL_INTERVAL</id></attribute> - <attribute><id>EFF_ZQCAL_INTERVAL</id></attribute> - <attribute><id>EFF_IBM_TYPE</id></attribute> - <attribute><id>EFF_NUM_DROPS_PER_PORT</id></attribute> - <attribute><id>EFF_NUM_MASTER_RANKS_PER_DIMM</id></attribute> - <attribute><id>EFF_NUM_PACKAGES_PER_RANK</id></attribute> - <attribute><id>EFF_PRIM_DIE_COUNT</id></attribute> - <attribute><id>MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT</id></attribute> - <attribute><id>MSS_MEM_M_DRAM_CLOCKS</id></attribute> - <attribute><id>MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id></attribute> - <attribute><id>MSS_MEM_WATT_TARGET</id></attribute> - <attribute><id>MSS_MASTER_PWR_SLOPE</id></attribute> - <attribute><id>MSS_SUPPLIER_PWR_SLOPE</id></attribute> - <attribute><id>MSS_TOTAL_PWR_SLOPE</id></attribute> - <attribute><id>MSS_TOTAL_PWR_INTERCEPT</id></attribute> - <attribute><id>MSS_PORT_MAXPOWER</id></attribute> - <attribute><id>MSS_SUPPLIER_PWR_INTERCEPT</id></attribute> - <attribute><id>MSS_DIMM_MAXBANDWIDTH_GBS</id></attribute> - <attribute><id>MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id></attribute> - <attribute><id>MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id></attribute> - <attribute><id>MSS_DIMM_MAXPOWER</id></attribute> - <attribute><id>MSS_CHANNEL_PAIR_MAXPOWER</id></attribute> - <attribute><id>MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT</id></attribute> - <attribute><id>MSS_RUNTIME_MEM_M_DRAM_CLOCKS</id></attribute> - <attribute><id>MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id></attribute> - <attribute><id>MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id></attribute> - <attribute><id>EFF_DRAM_LPASR</id></attribute> - <attribute><id>EFF_MPR_PAGE</id></attribute> - <attribute><id>EFF_GEARDOWN_MODE</id></attribute> - <attribute><id>EFF_PER_DRAM_ACCESS</id></attribute> - <attribute><id>EFF_TEMP_READOUT</id></attribute> - <attribute><id>EFF_CRC_WR_LATENCY</id></attribute> - <attribute><id>EFF_MPR_RD_FORMAT</id></attribute> - <attribute><id>EFF_MAX_POWERDOWN_MODE</id></attribute> - <attribute><id>EFF_TEMP_REFRESH_MODE</id></attribute> - <attribute><id>EFF_INTERNAL_VREF_MONITOR</id></attribute> - <attribute><id>EFF_CS_CMD_LATENCY</id></attribute> - <attribute><id>EFF_SELF_REF_ABORT</id></attribute> - <attribute><id>EFF_RD_PREAMBLE_TRAIN</id></attribute> - <attribute><id>EFF_RD_PREAMBLE</id></attribute> - <attribute><id>EFF_WR_PREAMBLE</id></attribute> - <attribute><id>EFF_CA_PARITY_LATENCY</id></attribute> - <attribute><id>EFF_CRC_ERROR_CLEAR</id></attribute> - <attribute><id>EFF_CA_PARITY_ERROR_STATUS</id></attribute> - <attribute><id>EFF_ODT_INPUT_BUFF</id></attribute> - <attribute><id>EFF_CA_PARITY</id></attribute> - <attribute><id>EFF_DATA_MASK</id></attribute> - <attribute><id>EFF_WRITE_DBI</id></attribute> - <attribute><id>EFF_READ_DBI</id></attribute> - <attribute><id>EFF_VREF_DQ_TRAIN_VALUE</id></attribute> - <attribute><id>EFF_VREF_DQ_TRAIN_RANGE</id></attribute> - <attribute><id>EFF_VREF_DQ_TRAIN_ENABLE</id></attribute> - <attribute><id>EFF_WRITE_CRC</id></attribute> - <attribute><id>MSS_CAL_STEP_ENABLE</id></attribute> - <attribute><id>MSS_SLEW_RATE_DATA</id></attribute> - <attribute><id>MSS_SLEW_RATE_ADR</id></attribute> - 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<attribute><id>VPD_REC_NUM</id></attribute> - <attribute><id>EFF_DRAM_GEN</id></attribute> - <attribute><id>EFF_DIMM_TYPE</id></attribute> - <attribute><id>EFF_HYBRID_MEMORY_TYPE</id></attribute> - <attribute><id>EFF_HYBRID</id></attribute> - <attribute><id>EFF_DRAM_DENSITY</id></attribute> - <attribute><id>EFF_DRAM_BANK_BITS</id></attribute> - <attribute><id>EFF_DRAM_BANK_GROUP_BITS</id></attribute> - <attribute><id>EFF_DRAM_COLUMN_BITS</id></attribute> - <attribute><id>EFF_DRAM_ROW_BITS</id></attribute> - <attribute><id>EFF_PRIM_STACK_TYPE</id></attribute> - <attribute><id>EFF_DRAM_PPR</id></attribute> - <attribute><id>EFF_DRAM_SOFT_PPR</id></attribute> - <attribute><id>EFF_DRAM_TRCD</id></attribute> - <attribute><id>EFF_DRAM_TRP</id></attribute> - <attribute><id>EFF_DRAM_TRAS</id></attribute> - <attribute><id>EFF_DRAM_TRC</id></attribute> - <attribute><id>EFF_DRAM_TRFC</id></attribute> - <attribute><id>EFF_DRAM_TFAW</id></attribute> - <attribute><id>EFF_DRAM_TRRD_S</id></attribute> - <attribute><id>EFF_DRAM_TRRD_L</id></attribute> - <attribute><id>EFF_DRAM_TCCD_L</id></attribute> - <attribute><id>EFF_DRAM_TWR</id></attribute> - <attribute><id>EFF_DRAM_TWTR_S</id></attribute> - <attribute><id>EFF_DRAM_TWTR_L</id></attribute> - <attribute><id>EFF_DRAM_TMAW</id></attribute> - <attribute><id>CDM_DOMAIN</id><default>MEM</default></attribute> - <attribute><id>MEMVPD_POS</id></attribute> - <attribute><id>VPD_OVERRIDE_MT</id></attribute> - <attribute><id>VPD_OVERRIDE_MT_ENABLE</id></attribute> - <attribute><id>VPD_OVERRIDE_MR</id></attribute> - <attribute><id>VPD_OVERRIDE_MR_ENABLE</id></attribute> - <attribute><id>VPD_OVERRIDE_DQ</id></attribute> - <attribute><id>VPD_OVERRIDE_DQ_ENABLE</id></attribute> - <attribute><id>VPD_OVERRIDE_CK</id></attribute> - <attribute><id>VPD_OVERRIDE_CK_ENABLE</id></attribute> - <attribute><id>MSS_VPD_MT_0_VERSION_LAYOUT</id></attribute> - <attribute><id>MSS_VPD_MT_1_VERSION_DATA</id></attribute> - <attribute><id>MSS_VPD_MT_2_SIGNATURE_HASH</id></attribute> - <attribute><id>MSS_VPD_MR_0_VERSION_LAYOUT</id></attribute> - <attribute><id>MSS_VPD_MR_1_VERSION_DATA</id></attribute> - <attribute><id>MSS_VPD_MR_2_SIGNATURE_HASH</id></attribute> - <attribute><id>MSS_VPD_MR_DPHY_GPO</id></attribute> - <attribute><id>MSS_VPD_MR_DPHY_RLO</id></attribute> - <attribute><id>MSS_VPD_MR_DPHY_WLO</id></attribute> - <attribute><id>MSS_OCC_THROTTLED_N_CMDS</id></attribute> - <attribute><id>MSS_VPD_CKE_MAP</id></attribute> - <attribute><id>MSS_VPD_DQ_MAP</id></attribute> - <attribute><id>EFF_DIMM_RANKS_CONFIGED</id></attribute> - <attribute><id>MSS_DIMM_MAXBANDWIDTH_MRS</id></attribute> - <attribute><id>DMI_REFCLOCK_SWIZZLE</id></attribute> - <attribute><id>MSS_MASTER_PWR_INTERCEPT</id></attribute> - <attribute><id>MSS_IGNORE_PLUG_RULES</id></attribute> - <attribute><id>EFF_DRAM_MFG_ID</id></attribute> - <attribute><id>EFF_DRAM_TRRD_DLR</id></attribute> - <attribute><id>BAD_DQ_BITMAP</id></attribute> - <attribute><id>MSS_DIMM_THERMAL_LIMIT</id></attribute> - <attribute><id>MSS_VREF_CAL_ENABLE</id></attribute> - <attribute><id>MSS_MRW_UNSUPPORTED_RANK_CONFIG</id></attribute> - <attribute><id>MSS_RTT_NOM_OVERRIDE_DISABLE</id></attribute> - <attribute><id>EFF_DRAM_RTT_NOM</id></attribute> - <attribute><id>EFF_DRAM_RTT_WR</id></attribute> - <attribute><id>EFF_DRAM_RTT_PARK</id></attribute> - <attribute><id>EFF_RANK_GROUP_OVERRIDE</id></attribute> - <attribute><id>MSS_RDVREF_CAL_ENABLE</id></attribute> - <attribute><id>MSS_VREF_DAC_NIBBLE</id></attribute> - <attribute><id>MSS_MVPD_FWMS</id></attribute> - <attribute><id>MSS_PHY_SEQ_REFRESH</id></attribute> - <attribute><id>EFF_REGISTER_TYPE</id></attribute> - <attribute><id>EFF_RCD_MFG_ID</id></attribute> - <attribute><id>EFF_REGISTER_REV</id></attribute> -</targetType> - -<targetType> - <id>unit-mcs-nimbus</id> - <parent>unit-mcs-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> + <id>unit-mcs-power9</id> + <parent>unit</parent> + <attribute> + <default>MCS</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000003</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>EEPROM_VPD_PRIMARY_INFO</id> + </attribute> + <attribute><id>IBSCOM_MCS_BASE_ADDR</id></attribute> + <attribute> + <id>EI_BUS_TX_MSBSWAP</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>EFF_NUM_RANKS_PER_DIMM</id> + </attribute> + <attribute> + <id>EFF_DRAM_WIDTH</id> + </attribute> + <attribute> + <id>EFF_DRAM_RANK_MIX</id> + </attribute> + <attribute> + <id>EFF_DIMM_SPARE</id> + </attribute> + <attribute> + <id>EFF_DRAM_WR_VREF</id> + </attribute> + <attribute> + <id>EFF_DRAM_WR_VREF_SCHMOO</id> + </attribute> + <attribute> + <id>EFF_DRAM_WRDDR4_VREF_SCHMOO</id> + </attribute> + <attribute> + <id>EFF_DIMM_SIZE</id> + </attribute> + <attribute> + <id>EFF_DRAM_CL</id> + </attribute> + <attribute> + <id>EFF_DRAM_AL</id> + </attribute> + <attribute> + <id>EFF_DRAM_CWL</id> + </attribute> + <attribute> + <id>EFF_DRAM_RBT</id> + </attribute> + <attribute> + <id>EFF_DRAM_TM</id> + </attribute> + <attribute> + <id>EFF_DRAM_DLL_RESET</id> + </attribute> + <attribute> + <id>EFF_DRAM_DLL_PPD</id> + </attribute> + <attribute> + <id>EFF_DRAM_DLL_ENABLE</id> + </attribute> + <attribute> + <id>EFF_DRAM_WR_LVL_ENABLE</id> + </attribute> + <attribute> + <id>EFF_DRAM_OUTPUT_BUFFER</id> + </attribute> + <attribute> + <id>EFF_DRAM_PASR</id> + </attribute> + <attribute> + <id>EFF_DRAM_ASR</id> + </attribute> + <attribute> + <id>EFF_DRAM_SRT</id> + </attribute> + <attribute> + <id>EFF_MPR_LOC</id> + </attribute> + <attribute> + <id>EFF_MPR_MODE</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC00</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC01</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC02</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC03</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC04</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC05</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC06_07</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC08</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC09</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC0A</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC0B</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC0C</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC0D</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC0E</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC0F</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC_1x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC_2x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC_3x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC_4x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC_5x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC_6x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC_7x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC_8x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC_9x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC_Ax</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_RC_Bx</id> + </attribute> + <attribute> + <id>EFF_DIMM_RCD_MIRROR_MODE</id> + </attribute> + <attribute> + <id>EFF_SCHMOO_MODE</id> + </attribute> + <attribute> + <id>EFF_SCHMOO_ADDR_MODE</id> + </attribute> + <attribute> + <id>EFF_SCHMOO_TEST_VALID</id> + </attribute> + <attribute> + <id>EFF_SCHMOO_PARAM_VALID</id> + </attribute> + <attribute> + <id>EFF_SCHMOO_WR_EYE_MIN_MARGIN</id> + </attribute> + <attribute> + <id>EFF_SCHMOO_RD_EYE_MIN_MARGIN</id> + </attribute> + <attribute> + <id>EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id> + </attribute> + <attribute> + <id>EFF_SCHMOO_RD_GATE_MIN_MARGIN</id> + </attribute> + <attribute> + <id>EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id> + </attribute> + <attribute> + <id>EFF_MEMCAL_INTERVAL</id> + </attribute> + <attribute> + <id>EFF_ZQCAL_INTERVAL</id> + </attribute> + <attribute> + <id>EFF_IBM_TYPE</id> + </attribute> + <attribute> + <id>EFF_NUM_MASTER_RANKS_PER_DIMM</id> + </attribute> + <attribute> + <id>EFF_PRIM_DIE_COUNT</id> + </attribute> + <attribute> + <id>MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> + </attribute> + <attribute> + <id>MSS_MEM_M_DRAM_CLOCKS</id> + </attribute> + <attribute> + <id>MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id> + </attribute> + <attribute> + <id>MSS_MEM_WATT_TARGET</id> + </attribute> + <attribute> + <id>MSS_TOTAL_PWR_SLOPE</id> + </attribute> + <attribute> + <id>MSS_TOTAL_PWR_INTERCEPT</id> + </attribute> + <attribute> + <id>MSS_PORT_MAXPOWER</id> + </attribute> + <attribute> + <id>MSS_DIMM_MAXBANDWIDTH_GBS</id> + </attribute> + <attribute> + <id>MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id> + </attribute> + <attribute> + <id>MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id> + </attribute> + <attribute> + <id>MSS_DIMM_MAXPOWER</id> + </attribute> + <attribute> + <id>MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> + </attribute> + <attribute> + <id>MSS_RUNTIME_MEM_M_DRAM_CLOCKS</id> + </attribute> + <attribute> + <id>MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id> + </attribute> + <attribute> + <id>MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id> + </attribute> + <attribute> + <id>EFF_DRAM_LPASR</id> + </attribute> + <attribute> + <id>EFF_MPR_PAGE</id> + </attribute> + <attribute> + <id>EFF_GEARDOWN_MODE</id> + </attribute> + <attribute> + <id>EFF_PER_DRAM_ACCESS</id> + </attribute> + <attribute> + <id>EFF_TEMP_READOUT</id> + </attribute> + <attribute> + <id>EFF_CRC_WR_LATENCY</id> + </attribute> + <attribute> + <id>EFF_MPR_RD_FORMAT</id> + </attribute> + <attribute> + <id>EFF_MAX_POWERDOWN_MODE</id> + </attribute> + <attribute> + <id>EFF_INTERNAL_VREF_MONITOR</id> + </attribute> + <attribute> + <id>EFF_CS_CMD_LATENCY</id> + </attribute> + <attribute> + <id>EFF_SELF_REF_ABORT</id> + </attribute> + <attribute> + <id>EFF_RD_PREAMBLE_TRAIN</id> + </attribute> + <attribute> + <id>EFF_RD_PREAMBLE</id> + </attribute> + <attribute> + <id>EFF_WR_PREAMBLE</id> + </attribute> + <attribute> + <id>EFF_CA_PARITY_LATENCY</id> + </attribute> + <attribute> + <id>EFF_CRC_ERROR_CLEAR</id> + </attribute> + <attribute> + <id>EFF_CA_PARITY_ERROR_STATUS</id> + </attribute> + <attribute> + <id>EFF_ODT_INPUT_BUFF</id> + </attribute> + <attribute> + <id>EFF_CA_PARITY</id> + </attribute> + <attribute> + <id>EFF_DATA_MASK</id> + </attribute> + <attribute> + <id>EFF_WRITE_DBI</id> + </attribute> + <attribute> + <id>EFF_READ_DBI</id> + </attribute> + <attribute> + <id>EFF_VREF_DQ_TRAIN_VALUE</id> + </attribute> + <attribute> + <id>EFF_VREF_DQ_TRAIN_RANGE</id> + </attribute> + <attribute> + <id>EFF_VREF_DQ_TRAIN_ENABLE</id> + </attribute> + <attribute> + <id>EFF_WRITE_CRC</id> + </attribute> + <attribute> + <id>MSS_CAL_STEP_ENABLE</id> + </attribute> + <attribute> + <id>MSS_SLEW_RATE_DATA</id> + </attribute> + <attribute> + <id>MSS_SLEW_RATE_ADR</id> + </attribute> + <attribute> + <id>SCHMOO_MULTIPLE_SETUP_CALL</id> + </attribute> + <attribute> + <id>EFF_BUFFER_LATENCY</id> + </attribute> + <attribute> + <id>EFF_LRDIMM_WORD_X</id> + </attribute> + <attribute> + <id>LRDIMM_MR12_REG</id> + </attribute> + <attribute> + <id>LRDIMM_ADDITIONAL_CNTL_WORDS</id> + </attribute> + <attribute> + <id>LRDIMM_RANK_MULT_MODE</id> + </attribute> + <attribute> + <id>MSS_EFF_VPD_VERSION</id> + </attribute> + <attribute> + <id>MSS_DATABUS_UTIL</id> + </attribute> + <attribute> + <id>EFF_DRAM_MAC</id> + </attribute> + <attribute> + <id>EFF_DRAM_MODULE_BUS_WIDTH</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC00</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC01</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC02</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC03</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC04</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC05</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC06</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC07</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC08</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC09</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC0A</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC0B</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC0C</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC0D</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC0E</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_BC0F</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F0BC1x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F30BC2x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F30BC3x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F30BC4x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F30BC5x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F0BC6x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F70BC7x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F30BC8x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F30BC9x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F30BCAx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F30BCBx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F0BCCx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F0BCDx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F0BCEx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F0BCFx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F1BCCx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F1BCDx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F1BCEx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F1BCFx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F4BC0x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F4BC1x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F4BC2x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F4BC3x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F4BC4x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F4BC5x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F4BC6x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F5BC0x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F5BC1x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F5BC2x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F5BC3x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F5BC5x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F5BC6x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F6BC0x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F6BC1x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F6BC2x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F6BC3x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F6BC4x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F6BC5x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F74BC8x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F74BC9x</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F74BCAx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F74BCBx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F74BCCx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F74BCDx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F74BCEx</id> + </attribute> + <attribute> + <id>EFF_DIMM_DDR4_F74BCFx</id> + </attribute> + <attribute> + <id>EFF_DRAM_RON</id> + </attribute> + <attribute> + <id>EFF_DRAM_RTT_NOM</id> + </attribute> + <attribute> + <id>EFF_DRAM_RTT_WR</id> + </attribute> + <attribute> + <id>EFF_DRAM_TDQS</id> + </attribute> + <attribute> + <id>EFF_DRAM_TREFI</id> + </attribute> + <attribute> + <id>EFF_DRAM_TRTP</id> + </attribute> + <attribute> + <id>EFF_DRAM_TRFC_DLR</id> + </attribute> + <attribute> + <id>EFF_DRAM_TFAW_DLR</id> + </attribute> + <attribute> + <id>EFF_DRAM_TXS</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_MC_2N_MODE_AUTOSET</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_TSYS_ADR</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_TSYS_DATA</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_DIMM_RCD_IBT_CA</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_DIMM_RCD_IBT_CKE</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_DIMM_RCD_IBT_CS</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_DIMM_RCD_IBT_ODT</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_PREAMBLE</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_MC_DRV_IMP_CSCID</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_DRAM_RTT_NOM</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_DRAM_RTT_PARK</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_DRAM_RTT_WR</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_MC_DRV_IMP_CLK</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_MC_DRV_IMP_CNTL</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_MC_DRV_IMP_DQ_DQS</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_MC_RCV_IMP_DQ_DQS</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_ODT_RD</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_ODT_WR</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_VREF_DRAM_WR</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_VREF_MC_RD</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_WINDAGE_RD_CTR</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_MC_DQ_CTLE_CAP</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_MC_DQ_CTLE_RES</id> + </attribute> + <attribute> + <id>VPD_REC_NUM</id> + </attribute> + <attribute> + <id>EFF_DRAM_GEN</id> + </attribute> + <attribute> + <id>EFF_DIMM_TYPE</id> + </attribute> + <attribute> + <id>EFF_HYBRID_MEMORY_TYPE</id> + </attribute> + <attribute> + <id>EFF_HYBRID</id> + </attribute> + <attribute> + <id>EFF_DRAM_DENSITY</id> + </attribute> + <attribute> + <id>EFF_DRAM_BANK_BITS</id> + </attribute> + <attribute> + <id>EFF_DRAM_BANK_GROUP_BITS</id> + </attribute> + <attribute> + <id>EFF_DRAM_COLUMN_BITS</id> + </attribute> + <attribute> + <id>EFF_DRAM_ROW_BITS</id> + </attribute> + <attribute> + <id>EFF_PRIM_STACK_TYPE</id> + </attribute> + <attribute> + <id>EFF_DRAM_PPR</id> + </attribute> + <attribute> + <id>EFF_DRAM_SOFT_PPR</id> + </attribute> + <attribute> + <id>EFF_DRAM_TRCD</id> + </attribute> + <attribute> + <id>EFF_DRAM_TRP</id> + </attribute> + <attribute> + <id>EFF_DRAM_TRAS</id> + </attribute> + <attribute> + <id>EFF_DRAM_TRC</id> + </attribute> + <attribute> + <id>EFF_DRAM_TRFC</id> + </attribute> + <attribute> + <id>EFF_DRAM_TFAW</id> + </attribute> + <attribute> + <id>EFF_DRAM_TRRD_S</id> + </attribute> + <attribute> + <id>EFF_DRAM_TRRD_L</id> + </attribute> + <attribute> + <id>EFF_DRAM_TCCD_L</id> + </attribute> + <attribute> + <id>EFF_DRAM_TWR</id> + </attribute> + <attribute> + <id>EFF_DRAM_TWTR_S</id> + </attribute> + <attribute> + <id>EFF_DRAM_TWTR_L</id> + </attribute> + <attribute> + <id>EFF_DRAM_TMAW</id> + </attribute> + <attribute> + <default>MEM</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>MEMVPD_POS</id> + </attribute> + <attribute> + <id>VPD_OVERRIDE_MT</id> + </attribute> + <attribute> + <id>VPD_OVERRIDE_MT_ENABLE</id> + </attribute> + <attribute> + <id>VPD_OVERRIDE_MR</id> + </attribute> + <attribute> + <id>VPD_OVERRIDE_MR_ENABLE</id> + </attribute> + <attribute> + <id>VPD_OVERRIDE_DQ</id> + </attribute> + <attribute> + <id>VPD_OVERRIDE_DQ_ENABLE</id> + </attribute> + <attribute> + <id>VPD_OVERRIDE_CK</id> + </attribute> + <attribute> + <id>VPD_OVERRIDE_CK_ENABLE</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_0_VERSION_LAYOUT</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_1_VERSION_DATA</id> + </attribute> + <attribute> + <id>MSS_VPD_MT_2_SIGNATURE_HASH</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_0_VERSION_LAYOUT</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_1_VERSION_DATA</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_2_SIGNATURE_HASH</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_DPHY_GPO</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_DPHY_RLO</id> + </attribute> + <attribute> + <id>MSS_VPD_MR_DPHY_WLO</id> + </attribute> + <attribute> + <id>MSS_VPD_CKE_MAP</id> + </attribute> + <attribute> + <id>MSS_VPD_DQ_MAP</id> + </attribute> + <attribute> + <id>EFF_DIMM_RANKS_CONFIGED</id> + </attribute> + <attribute> + <id>MSS_DIMM_MAXBANDWIDTH_MRS</id> + </attribute> + <attribute> + <id>DMI_REFCLOCK_SWIZZLE</id> + </attribute> + <attribute> + <id>MSS_IGNORE_PLUG_RULES</id> + </attribute> + <attribute> + <id>EFF_DRAM_MFG_ID</id> + </attribute> + <attribute> + <id>EFF_DRAM_TRRD_DLR</id> + </attribute> + <attribute> + <id>BAD_DQ_BITMAP</id> + </attribute> + <attribute> + <id>MSS_DIMM_THERMAL_LIMIT</id> + </attribute> + <attribute> + <id>MSS_VREF_CAL_ENABLE</id> + </attribute> + <attribute> + <id>MSS_MRW_UNSUPPORTED_RANK_CONFIG</id> + </attribute> + <attribute> + <id>MSS_RTT_NOM_OVERRIDE_DISABLE</id> + </attribute> + <attribute> + <id>EFF_DRAM_RTT_NOM</id> + </attribute> + <attribute> + <id>EFF_DRAM_RTT_WR</id> + </attribute> + <attribute> + <id>EFF_DRAM_RTT_PARK</id> + </attribute> + <attribute> + <id>EFF_RANK_GROUP_OVERRIDE</id> + </attribute> + <attribute> + <id>MSS_RDVREF_CAL_ENABLE</id> + </attribute> + <attribute> + <id>MSS_VREF_DAC_NIBBLE</id> + </attribute> + <attribute> + <id>MSS_MVPD_FWMS</id> + </attribute> +</targetType> + +<targetType> + <id>unit-mcs-nimbus</id> + <parent>unit-mcs-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- MCA @@ -1932,89 +3534,144 @@ Cumulus: No MCA Tied 1-1 to a DDR port --> <targetType> - <id>unit-mca-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>MCA</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000003</default> <!-- GARD | MEMDIAG --> - </attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - <attribute><id>CDM_DOMAIN</id><default>MEM</default></attribute> - <attribute><id>VPD_OVERRIDE_MW_ENABLE</id></attribute> - <attribute><id>VPD_OVERRIDE_MW</id></attribute> - <attribute><id>PRD_HWP_PLID</id></attribute> - <attribute><id>RCD_PARITY_RECONFIG_LOOP_COUNT</id></attribute> + <id>unit-mca-power9</id> + <parent>unit</parent> + <attribute> + <default>MCA</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000003</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>MEM</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>VPD_OVERRIDE_MW_ENABLE</id> + </attribute> + <attribute> + <id>VPD_OVERRIDE_MW</id> + </attribute> + <attribute> + <id>PRD_HWP_PLID</id> + </attribute> + <attribute><id>RCD_PARITY_RECONFIG_LOOP_COUNT</id></attribute> </targetType> <targetType> - <id>unit-mca-nimbus</id> - <parent>unit-mca-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> + <id>unit-mca-nimbus</id> + <parent>unit-mca-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- MCBIST Nimbus : 1 per MCU (total of 2 per chip) Cumulus: None --> <targetType> - <id>unit-mcbist-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>MCBIST</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000003</default> <!-- GARD | MEMDIAG --> - </attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - <attribute><id>MSS_FREQ</id></attribute> - <attribute><id>MSS_FREQ_OVERRIDE</id></attribute> - <attribute><id>MSS_VOLT_OVERRIDE</id></attribute> - <attribute><id>MSS_FREQ_BIAS_PERCENTAGE</id></attribute> - <attribute><id>MSS_NEST_CAPABLE_FREQUENCIES</id></attribute> - <attribute><id>CDM_DOMAIN</id><default>MEM</default></attribute> - -<!-- Enable memory voltage attributes --> -<!-- Static voltages --> - <attribute><id>MSS_VOLT_VPP_MILLIVOLTS</id></attribute> - <attribute><id>MSS_VOLT_VDDR_MILLIVOLTS</id></attribute> - <attribute><id>MSS_VOLT_VCS_MILLIVOLTS</id></attribute> - <attribute><id>MSS_VOLT_VDD_MILLIVOLTS</id></attribute> - <attribute><id>MSS_VOLT_AVDD_MILLIVOLTS</id></attribute> - -<!-- Dynamic voltages --> - <attribute><id>MSS_VOLT_VPP_OFFSET_MILLIVOLTS</id></attribute> - <attribute><id>MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id></attribute> - <attribute><id>MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id></attribute> - <attribute><id>MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id></attribute> - <attribute><id>MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id></attribute> - -<!-- Unique domain id --> - <attribute><id>VPP_ID</id></attribute> - <attribute><id>VDDR_ID</id></attribute> - <attribute><id>VCS_ID</id></attribute> - <attribute><id>VDD_ID</id></attribute> - <attribute><id>AVDD_ID</id></attribute> - - <attribute><id>MSS_REORDER_QUEUE_SETTING</id></attribute> -</targetType> - -<targetType> - <id>unit-mcbist-nimbus</id> - <parent>unit-mcbist-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> + <id>unit-mcbist-power9</id> + <parent>unit</parent> + <attribute> + <default>MCBIST</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000003</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>MSS_FREQ</id> + </attribute> + <attribute> + <id>MSS_FREQ_OVERRIDE</id> + </attribute> + <attribute> + <id>MSS_VOLT_OVERRIDE</id> + </attribute> + <attribute> + <id>MSS_FREQ_BIAS_PERCENTAGE</id> + </attribute> + <attribute> + <default>MEM</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>MSS_VOLT_VCS_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_VDD_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_AVDD_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_VPP_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_VDDR_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_VCS_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_VDD_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>MSS_VOLT_AVDD_OFFSET_MILLIVOLTS</id> + </attribute> + <attribute> + <id>VPP_ID</id> + </attribute> + <attribute> + <id>VDDR_ID</id> + </attribute> + <attribute> + <id>VCS_ID</id> + </attribute> + <attribute> + <id>VDD_ID</id> + </attribute> + <attribute> + <id>AVDD_ID</id> + </attribute> + <attribute> + <id>MSS_REORDER_QUEUE_SETTING</id> + </attribute> +</targetType> + +<targetType> + <id>unit-mcbist-nimbus</id> + <parent>unit-mcbist-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- MC @@ -2043,244 +3700,305 @@ Nimbus : None Cumulus: total of 4 per chip --> <targetType> - <id>unit-mi-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>MI</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> + <id>unit-mi-power9</id> + <parent>unit</parent> + <attribute> + <default>MI</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> </targetType> <targetType> - <id>unit-mi-cumulus</id> - <parent>unit-mi-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>unit-mi-cumulus</id> + <parent>unit-mi-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- DMI Nimbus : None Cumulus: 2 per MI (total of 8 per chip) --> <targetType> - <id>unit-dmi-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>DMI</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - <attribute><id>EI_BUS_TX_MSBSWAP</id></attribute> + <id>unit-dmi-power9</id> + <parent>unit</parent> + <attribute> + <default>DMI</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>EI_BUS_TX_MSBSWAP</id> + </attribute> </targetType> <targetType> - <id>unit-dmi-cumulus</id> - <parent>unit-dmi-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>unit-dmi-cumulus</id> + <parent>unit-dmi-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- PEC corresponds to IOP. Use same PEC target for Nimbus and Cumulus Nimbus : 3 per chip Cumulus: 3 per chip --> <targetType> - <id>unit-pec-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>PEC</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - - <attribute><id>PROC_PCIE_IOVALID_ENABLE</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_CDR_GAIN</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_PK_INIT</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_INIT_GAIN</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_SIGDET_LVL</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_ROT_EXTEL</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_ROT_RST_FW</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_DFE_FDDC</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_LOFF_CONTROL</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_ROT_CDR_LOOKAHEAD</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_ROT_CDR_SSC</id></attribute> - <attribute><id>PROC_PCIE_PCS_PCLCK_CNTL_PLLA</id></attribute> - <attribute><id>PROC_PCIE_PCS_PCLCK_CNTL_PLLB</id></attribute> - <attribute><id>PROC_PCIE_PCS_TX_DCLCK_ROT</id></attribute> - <attribute><id>PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET</id></attribute> - <attribute><id>PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG1</id></attribute> - <attribute><id>PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG2</id></attribute> - <attribute><id>PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_PHASE_ROTATOR_CNTL</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_VGA_CNTL_REG1</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_VGA_CNTL_REG2</id></attribute> - <attribute><id>PROC_PCIE_PCS_RX_SIGDET_CNTL</id></attribute> - <attribute><id>PROC_PCIE_PCS_SYSTEM_CNTL</id></attribute> - <attribute><id>PROC_PCIE_PCS_M_CNTL</id></attribute> - <attribute><id>PROC_PCIE_IOP_SWAP</id></attribute> - - <attribute><id>PROC_PCIE_REFCLOCK_ENABLE</id></attribute> - <attribute><id>PROC_PCIE_IOP_CONFIG</id></attribute> - - <attribute><id>CDM_DOMAIN</id><default>IO</default></attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!-- GARD --> - </attribute> - - <attribute><id>PROC_PCIE_LANE_MASK</id></attribute> - <attribute><id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id></attribute> - <attribute><id>PEC_PCIE_LANE_MASK_BIFURCATED</id></attribute> - <attribute><id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id></attribute> - <attribute><id>PEC_PCIE_IOP_SWAP_BIFURCATED</id></attribute> - <attribute><id>PEC_PCIE_IOP_REVERSAL</id></attribute> - <attribute><id>PEC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id></attribute> - <attribute><id>PEC_PCIE_IOP_REVERSAL_BIFURCATED</id></attribute> - -</targetType><!-- unit-pec-power9 --> + <id>unit-pec-power9</id> + <parent>unit</parent> + <attribute> + <default>PEC</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute><id>PROC_PCIE_PCS_RX_LOFF_CONTROL</id></attribute> + <attribute><id>PROC_PCIE_PCS_RX_PHASE_ROTATOR_CNTL</id></attribute> + <attribute><id>PROC_PCIE_PCS_RX_SIGDET_CNTL</id></attribute> + <attribute><id>PROC_PCIE_PCS_TX_FIFO_CONFIG_OFFSET</id></attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>PROC_PCIE_IOVALID_ENABLE</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_CDR_GAIN</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_PK_INIT</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_INIT_GAIN</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_SIGDET_LVL</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_ROT_EXTEL</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_ROT_RST_FW</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_DFE_FDDC</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_ROT_CDR_LOOKAHEAD</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_ROT_CDR_SSC</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_PCLCK_CNTL_PLLA</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_PCLCK_CNTL_PLLB</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_TX_DCLCK_ROT</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG1</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_TX_PCIE_RECV_DETECT_CNTL_REG2</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_VGA_CNTL_REG1</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_RX_VGA_CNTL_REG2</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_SYSTEM_CNTL</id> + </attribute> + <attribute> + <id>PROC_PCIE_PCS_M_CNTL</id> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_SWAP</id> + </attribute> + <attribute> + <id>PROC_PCIE_REFCLOCK_ENABLE</id> + </attribute> + <attribute> + <id>PROC_PCIE_IOP_CONFIG</id> + </attribute> + <attribute> + <default>IO</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000001</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PROC_PCIE_LANE_MASK</id> + </attribute> + <attribute> + <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id> + </attribute> + <attribute> + <id>PEC_PCIE_LANE_MASK_BIFURCATED</id> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_SWAP_BIFURCATED</id> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_REVERSAL</id> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id> + </attribute> + <attribute> + <id>PEC_PCIE_IOP_REVERSAL_BIFURCATED</id> + </attribute> + <attribute><id>PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3</id></attribute> +</targetType> <!-- PHB Nimbus : 6 per PEC (total of 18 per chip) Cumulus: 6 per PEC --> <targetType> - <id>unit-phb-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>PHB</default> - </attribute> - <attribute> - <id>PROC_PCIE_NUM_LANES</id> - <default>48</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!-- GARD --> - </attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - - <attribute><id>PROC_PCIE_BAR_ENABLE</id></attribute> - <attribute><id>PROC_PCIE_BAR_BASE_ADDR</id></attribute> - <attribute><id>PROC_PCIE_BAR_SIZE</id></attribute> - <attribute><id>CDM_DOMAIN</id><default>IO</default></attribute> - <attribute><id>PROC_PCIE_LANE_EQUALIZATION_GEN3</id></attribute> - <attribute><id>PROC_PCIE_LANE_EQUALIZATION_GEN4</id></attribute> - <attribute> - <id>PCIE_CAPABILITES</id> - <default></default> - </attribute> - <attribute> - <id>MGC_LOAD_SOURCE</id> - <default></default> - </attribute> - <attribute> - <id>SLOT_NAME</id> - <default></default> - </attribute> - <attribute> - <id>SLOT_INDEX</id> - <default></default> - </attribute> - <attribute> - <id>HDDW_ORDER</id> - <default></default> - </attribute> - <attribute> - <id>PCIE_32BIT_MMIO_SIZE</id> - <default></default> - </attribute> - <attribute> - <id>PCIE_64BIT_MMIO_SIZE</id> - <default></default> - </attribute> - <attribute> - <id>PCIE_32BIT_DMA_SIZE</id> - <default></default> - </attribute> - <attribute> - <id>PCIE_64BIT_DMA_SIZE</id> - <default></default> - </attribute> - <attribute> - <id>MAX_POWER</id> - <default></default> - </attribute> - <attribute> - <id>VENDOR_ID</id> - <default></default> - </attribute> - <attribute> - <id>DEVICE_ID</id> - <default></default> - </attribute> -</targetType><!-- unit-phb-power9 --> + <id>unit-phb-power9</id> + <parent>unit</parent> + <attribute> + <default>PHB</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000001</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>PROC_PCIE_BAR_ENABLE</id> + </attribute> + <attribute> + <id>PROC_PCIE_BAR_SIZE</id> + </attribute> + <attribute> + <default>IO</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <id>PROC_PCIE_LANE_EQUALIZATION_GEN3</id> + </attribute> + <attribute> + <id>PROC_PCIE_LANE_EQUALIZATION_GEN4</id> + </attribute> +</targetType> <targetType> - <id>unit-phb-nimbus</id> - <parent>unit-phb-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> + <id>unit-phb-nimbus</id> + <parent>unit-phb-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> </targetType> <targetType> - <id>unit-phb-cumulus</id> - <parent>unit-phb-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>unit-phb-cumulus</id> + <parent>unit-phb-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- OBUS Nimbus : 2 per chip (OB0 and OB3) Cumulus: 4 per chip (OB0, OB1, OB2, and OB3) --> <targetType> - <id>unit-obus-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>OBUS</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - <attribute><id>OPTICS_CONFIG_MODE</id></attribute> - <attribute><id>PEER_TARGET</id></attribute> - <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!-- GARD --> - </attribute> - <attribute><id>IO_O_MFG_CHK</id></attribute> - <attribute><id>IO_O_MFG_MIN_EYE_WIDTH</id></attribute> + <id>unit-obus-power9</id> + <parent>unit</parent> + <attribute> + <default>OBUS</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>PEER_TARGET</id> + </attribute> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>0x00000001</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> </targetType> <targetType> - <id>unit-obus-nimbus</id> - <parent>unit-obus-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> + <id>unit-obus-nimbus</id> + <parent>unit-obus-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> </targetType> <targetType> - <id>unit-obus-cumulus</id> - <parent>unit-obus-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>unit-obus-cumulus</id> + <parent>unit-obus-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- OBUS Brick @@ -2302,7 +4020,6 @@ </attribute> <attribute><id>OBUS_BRICK_LANE_MASK</id></attribute> <attribute><id>OBUS_SLOT_INDEX</id></attribute> - <attribute><id>OPTICS_CONFIG_MODE</id></attribute> <attribute><id>PARENT_PERVASIVE</id></attribute> </targetType> @@ -2326,39 +4043,50 @@ <!-- @TODO RTC:173529 - Remove NV once it is not used anywhere --> <targetType> - <id>unit-nv-power9</id> - <parent>unit-obus-power9</parent> - <attribute> - <id>TYPE</id> - <default>NV</default> - </attribute> - <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>HUID</id></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!-- GARD --> - </attribute> - <attribute><id>OPTICS_CONFIG_MODE</id><default>NVLINK</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> + <id>unit-nv-power9</id> + <parent>unit-obus-power9</parent> + <attribute> + <default>NV</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute><id>HUID</id></attribute> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>0x00000001</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> </targetType> <targetType> - <id>unit-nv-nimbus</id> - <parent>unit-nv-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> + <id>unit-nv-nimbus</id> + <parent>unit-nv-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> </targetType> <targetType> - <id>unit-nv-cumulus</id> - <parent>unit-nv-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>unit-nv-cumulus</id> + <parent>unit-nv-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- One NPU per proc --> @@ -2397,251 +4125,336 @@ 4 GPEs, 12 CMEs, and 3 IO PPEs. Cumulus: 23 (2 additional IO-PPE instances) --> <targetType> - <id>unit-ppe-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>PPE</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>0</default></attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> + <id>unit-ppe-power9</id> + <parent>unit</parent> + <attribute> + <default>PPE</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>0</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> </targetType> <targetType> - <id>unit-ppe-nimbus</id> - <parent>unit-ppe-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> + <id>unit-ppe-nimbus</id> + <parent>unit-ppe-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> </targetType> <targetType> - <id>unit-ppe-cumulus</id> - <parent>unit-ppe-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>unit-ppe-cumulus</id> + <parent>unit-ppe-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- PERV Nimbus : 43 (1 per chiplet) Cumulus: 1 per chiplet --> <targetType> - <id>unit-perv-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>PERV</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>0</default></attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>PG</id><default>5</default></attribute> - <attribute><id>TARGET_HAS_POWER</id></attribute> - <attribute><id>TARGET_HAS_CLOCK</id></attribute> - <attribute><id>TARGET_IS_SCOMMABLE</id></attribute> + <id>unit-perv-power9</id> + <parent>unit</parent> + <attribute> + <default>PERV</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>0</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <default>5</default> + <id>PG</id> + </attribute> + <attribute> + <id>TARGET_HAS_POWER</id> + </attribute> + <attribute> + <id>TARGET_HAS_CLOCK</id> + </attribute> + <attribute> + <id>TARGET_IS_SCOMMABLE</id> + </attribute> </targetType> <targetType> - <id>unit-perv-nimbus</id> - <parent>unit-perv-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> + <id>unit-perv-nimbus</id> + <parent>unit-perv-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> </targetType> <targetType> - <id>unit-perv-cumulus</id> - <parent>unit-perv-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>unit-perv-cumulus</id> + <parent>unit-perv-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- XBUS Nimbus : 1 per chip Cumulus: 7 --> <targetType> - <id>unit-xbus-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>XBUS</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!--GARD --> - </attribute> - <attribute><id>CHIP_UNIT</id></attribute> - <attribute><id>PEER_TARGET</id></attribute> - <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - <attribute><id>IO_XBUS_DCCAL_FLAGS</id></attribute> - <attribute><id>IO_X_DEBUG</id></attribute> - <attribute><id>IO_X_MFG_CHK</id></attribute> - <attribute><id>IO_X_MFG_MIN_EYE_WIDTH</id></attribute> - <attribute><id>IO_XBUS_MASTER_MODE</id></attribute> - <attribute><id>IO_XBUS_TX_MARGIN_RATIO</id></attribute> - <attribute><id>IO_XBUS_TX_FFE_PRECURSOR</id></attribute> - <attribute><id>EI_BUS_TX_MSBSWAP</id></attribute> + <id>unit-xbus-power9</id> + <parent>unit</parent> + <attribute> + <default>XBUS</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000001</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <id>PEER_TARGET</id> + </attribute> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <id>IO_XBUS_DCCAL_FLAGS</id> + </attribute> + <attribute> + <id>IO_X_DEBUG</id> + </attribute> + <attribute> + <id>IO_X_MFG_CHK</id> + </attribute> + <attribute> + <id>IO_X_MFG_MIN_EYE_WIDTH</id> + </attribute> + <attribute> + <id>IO_XBUS_MASTER_MODE</id> + </attribute> + <attribute> + <id>IO_XBUS_TX_MARGIN_RATIO</id> + </attribute> + <attribute> + <id>IO_XBUS_TX_FFE_PRECURSOR</id> + </attribute> + <attribute> + <id>EI_BUS_TX_MSBSWAP</id> + </attribute> </targetType> <targetType> - <id>unit-xbus-nimbus</id> - <parent>unit-xbus-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> + <id>unit-xbus-nimbus</id> + <parent>unit-xbus-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> </targetType> <targetType> - <id>unit-xbus-cumulus</id> - <parent>unit-xbus-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>unit-xbus-cumulus</id> + <parent>unit-xbus-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- CAPP Nimbus : 2 per chip Cumulus: 2 --> <targetType> - <id>unit-capp-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>CAPP</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!-- GARD --> - </attribute> - <attribute> - <id>PRIMARY_CAPABILITIES</id> - <default> - <field><id>supportsFsiScom</id><value>0</value></field> - <field><id>supportsXscom</id><value>0</value></field> - <field><id>supportsInbandScom</id><value>0</value></field> - <field><id>reserved</id><value>0</value></field> - </default> - </attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> - <attribute><id>PARENT_PERVASIVE</id></attribute> - <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute> + <id>unit-capp-power9</id> + <parent>unit</parent> + <attribute> + <default>CAPP</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000001</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default> + <field> + <id>supportsFsiScom</id> + <value>0</value> + </field> + <field> + <id>supportsXscom</id> + <value>0</value> + </field> + <field> + <id>supportsInbandScom</id> + <value>0</value> + </field> + <field> + <id>reserved</id> + <value>0</value> + </field> + </default> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> + <attribute> + <id>PARENT_PERVASIVE</id> + </attribute> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> </targetType> <targetType> - <id>unit-capp-nimbus</id> - <parent>unit-capp-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> + <id>unit-capp-nimbus</id> + <parent>unit-capp-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> </targetType> <targetType> - <id>unit-capp-cumulus</id> - <parent>unit-capp-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>unit-capp-cumulus</id> + <parent>unit-capp-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- SBE Nimbus : 1 per chip Cumulus: 1 --> <targetType> - <id>unit-sbe-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>SBE</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>0</default></attribute> - <attribute><id>SCRATCH_UINT8_1</id><default>5</default></attribute> + <id>unit-sbe-power9</id> + <parent>unit</parent> + <attribute> + <default>SBE</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>0</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>5</default> + <id>SCRATCH_UINT8_1</id> + </attribute> </targetType> <targetType> - <id>unit-sbe-nimbus</id> - <parent>unit-sbe-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> + <id>unit-sbe-nimbus</id> + <parent>unit-sbe-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> </targetType> <targetType> - <id>unit-sbe-cumulus</id> - <parent>unit-sbe-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>unit-sbe-cumulus</id> + <parent>unit-sbe-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> <!-- OCC Nimbus : 1 per chip Cumulus: 1 --> <targetType> - <id>unit-occ-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>OCC</default> - </attribute> - <attribute> - <id>MODEL</id> - <default>POWER9</default> - </attribute> - <attribute> - <id>OCC_MASTER_CAPABLE</id> - </attribute> + <id>unit-occ-power9</id> + <parent>unit</parent> + <attribute> + <default>OCC</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>POWER9</default> + <id>MODEL</id> + </attribute> + <attribute> + <id>OCC_MASTER_CAPABLE</id> + </attribute> </targetType> <targetType> - <id>unit-occ-nimbus</id> - <parent>unit-occ-power9</parent> - <attribute> - <id>MODEL</id> - <default>NIMBUS</default> - </attribute> + <id>unit-occ-nimbus</id> + <parent>unit-occ-power9</parent> + <attribute> + <default>NIMBUS</default> + <id>MODEL</id> + </attribute> </targetType> <targetType> - <id>unit-occ-cumulus</id> - <parent>unit-occ-power9</parent> - <attribute> - <id>MODEL</id> - <default>CUMULUS</default> - </attribute> + <id>unit-occ-cumulus</id> + <parent>unit-occ-power9</parent> + <attribute> + <default>CUMULUS</default> + <id>MODEL</id> + </attribute> </targetType> -<!-- L4 (Centaur) --> <targetType> - <id>unit-l4-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>L4</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> + <id>unit-l4-power9</id> + <parent>unit</parent> + <attribute> + <default>L4</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> </targetType> <targetType> - <id>unit-l4-centaur</id> - <parent>unit-l4-power9</parent> - <attribute> - <id>MODEL</id> - <default>CENTAUR</default> - </attribute> + <id>unit-l4-centaur</id> + <parent>unit-l4-power9</parent> + <attribute> + <default>CENTAUR</default> + <id>MODEL</id> + </attribute> </targetType> <!-- Centaur MBA --> @@ -2659,152 +4472,195 @@ </targetType> <targetType> - <id>unit-nx-power9</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>NX</default> - </attribute> - <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute> - <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> - <default>0x00000001</default> <!--GARD --> - </attribute> - <attribute> - <id>PRIMARY_CAPABILITIES</id> - <default> - <field><id>supportsFsiScom</id><value>0</value></field> - <field><id>supportsXscom</id><value>0</value></field> - <field><id>supportsInbandScom</id><value>0</value></field> - <field><id>reserved</id><value>0</value></field> - </default> - </attribute> - <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute> + <id>unit-nx-power9</id> + <parent>unit</parent> + <attribute> + <default>NX</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>1</default> + <id>DECONFIG_GARDABLE</id> + </attribute> + <attribute> + <default>0x00000001</default> + <id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id> + </attribute> + <attribute> + <default> + <field> + <id>supportsFsiScom</id> + <value>0</value> + </field> + <field> + <id>supportsXscom</id> + <value>0</value> + </field> + <field> + <id>supportsInbandScom</id> + <value>0</value> + </field> + <field> + <id>reserved</id> + <value>0</value> + </field> + </default> + <id>PRIMARY_CAPABILITIES</id> + </attribute> + <attribute> + <default>FABRIC</default> + <id>CDM_DOMAIN</id> + </attribute> </targetType> <targetType> - <id>uart</id> - <parent>unit</parent> - <attribute> - <id>CLASS</id> - <default>UNIT</default> - </attribute> - <attribute> - <id>TYPE</id> - <default>UART</default> - </attribute> + <id>uart</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>UART</default> + <id>TYPE</id> + </attribute> </targetType> <targetType> - <id>sp</id> - <parent>base</parent> - <attribute> - <id>CLASS</id> - <default>SP</default> - </attribute> - <attribute> - <id>TYPE</id> - <default>SP</default> - </attribute> + <id>sp</id> + <parent>base</parent> + <attribute> + <default>SP</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>SP</default> + <id>TYPE</id> + </attribute> </targetType> <targetType> - <id>chip-bmc-ast2500</id> - <parent>sp</parent> - <attribute> - <id>TYPE</id> - <default>BMC</default> - </attribute> - <attribute> - <id>MODEL</id> - <default>AST2500</default> - </attribute> - <attribute> - <id>HWAS_STATE</id> - <default> - <field><id>deconfiguredByEid</id><value>0</value></field> - <field><id>poweredOn</id><value>1</value></field> - <field><id>present</id><value>1</value></field> - <field><id>functional</id><value>1</value></field> - <field><id>dumpfunctional</id><value>0</value></field> - <field><id>specdeconfig</id><value>0</value></field> - </default> - </attribute> + <id>chip-bmc-ast2500</id> + <parent>sp</parent> + <attribute> + <default>BMC</default> + <id>TYPE</id> + </attribute> + <attribute> + <default>AST2500</default> + <id>MODEL</id> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>affinity:sys-0/node-0/bmc-0</default> + </attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/bmc-0</default> + </attribute> + <attribute> + <default> + <field> + <id>deconfiguredByEid</id> + <value>0</value> + </field> + <field> + <id>poweredOn</id> + <value>1</value> + </field> + <field> + <id>present</id> + <value>1</value> + </field> + <field> + <id>functional</id> + <value>1</value> + </field> + <field> + <id>dumpfunctional</id> + <value>0</value> + </field> + <field> + <id>specdeconfig</id> + <value>0</value> + </field> + </default> + <id>HWAS_STATE</id> + </attribute> </targetType> <targetType> - <id>power-supply</id> - <parent>unit</parent> - <attribute> - <id>CLASS</id> - <default>UNIT</default> - </attribute> - <attribute> - <id>TYPE</id> - <default>PS</default> - </attribute> + <id>power-supply</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>PS</default> + <id>TYPE</id> + </attribute> </targetType> <targetType> - <id>fan</id> - <parent>unit</parent> - <attribute> - <id>CLASS</id> - <default>UNIT</default> - </attribute> - <attribute> - <id>TYPE</id> - <default>FAN</default> - </attribute> + <id>fan</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>FAN</default> + <id>TYPE</id> + </attribute> </targetType> <targetType> - <id>vrm</id> - <parent>unit</parent> - <attribute> - <id>CLASS</id> - <default>UNIT</default> - </attribute> - <attribute> - <id>TYPE</id> - <default>VRM</default> - </attribute> + <id>vrm</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>VRM</default> + <id>TYPE</id> + </attribute> </targetType> <targetType> - <id>usb</id> - <parent>unit</parent> - <attribute> - <id>CLASS</id> - <default>UNIT</default> - </attribute> - <attribute> - <id>TYPE</id> - <default>USB</default> - </attribute> + <id>usb</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>USB</default> + <id>TYPE</id> + </attribute> </targetType> <targetType> - <id>eth</id> - <parent>unit</parent> - <attribute> - <id>CLASS</id> - <default>UNIT</default> - </attribute> - <attribute> - <id>TYPE</id> - <default>ETH</default> - </attribute> + <id>eth</id> + <parent>unit</parent> + <attribute> + <default>UNIT</default> + <id>CLASS</id> + </attribute> + <attribute> + <default>ETH</default> + <id>TYPE</id> + </attribute> </targetType> <targetType> - <id>panel</id> - <parent>unit</parent> - <attribute> - <id>TYPE</id> - <default>PANEL</default> - </attribute> + <id>panel</id> + <parent>unit</parent> + <attribute> + <default>PANEL</default> + <id>TYPE</id> + </attribute> </targetType> -<!-- End p9 sub-units --> - </attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types_empty.xml b/src/usr/targeting/common/xmltohb/target_types_empty.xml new file mode 100644 index 000000000..57a4986b1 --- /dev/null +++ b/src/usr/targeting/common/xmltohb/target_types_empty.xml @@ -0,0 +1,26 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/targeting/common/xmltohb/target_types_empty.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2017 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> +</attributes> diff --git a/src/usr/targeting/common/xmltohb/target_types_hb.xml b/src/usr/targeting/common/xmltohb/target_types_hb.xml index 6aef9602b..962acbf7b 100644 --- a/src/usr/targeting/common/xmltohb/target_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/target_types_hb.xml @@ -47,6 +47,7 @@ <attribute><id>HB_RSV_MEM_NEXT_SECTION</id></attribute> <attribute><id>HB_SECURITY_MODE</id></attribute> <attribute><id>ALLOW_ATTR_OVERRIDES_IN_SECURE_MODE</id></attribute> + <attribute><id>HIDDEN_ERRLOGS_ENABLE</id></attribute> </targetTypeExtension> <targetTypeExtension> diff --git a/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml b/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml index 20df55cd1..2bc2b8084 100644 --- a/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml +++ b/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml @@ -5488,9 +5488,6 @@ <attribute><id>VAS_USER_WINDOW_CONTEXT_ADDR</id> <default>0x0006053100000000</default> </attribute> - <attribute><id>LPC_BUS_ADDR</id> - <default>0x0006070000000000</default> - </attribute> <attribute><id>NVIDIA_NPU_PRIVILEGED_ADDR</id> <default>0x0006070200000000</default> </attribute> diff --git a/src/usr/targeting/common/xmltohb/xmltohb.pl b/src/usr/targeting/common/xmltohb/xmltohb.pl index 75d5f69a1..1d1370ecb 100755 --- a/src/usr/targeting/common/xmltohb/xmltohb.pl +++ b/src/usr/targeting/common/xmltohb/xmltohb.pl @@ -189,6 +189,7 @@ my $allAttributes = $xml->XMLin($cfgHbXmlFile, forcearray => ['enumerationType','enumerator','attribute','hwpfToHbAttrMap', 'compileAttribute','range']); + my $fapiAttributes = {}; if ($cfgFapiAttributesXmlFile ne "") { @@ -1003,6 +1004,7 @@ sub validateAttributes { $elements{"serverwizShow"} = { required => 0, isscalar => 1}; $elements{"global"} = { required => 0, isscalar => 0}; $elements{"range"} = { required => 0, isscalar => 0}; + $elements{"ignoreEkb"} = { required => 0, isscalar => 0}; # do NOT export attribute & its associated enum to serverwiz $elements{"no_export"} = { required => 0, isscalar => 0}; @@ -2092,7 +2094,7 @@ sub writeEnumFileAttrEnums { # Format below intentionally > 80 chars for clarity format ENUMFORMAT = - @<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< = @<<<<<<<<<< + @<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< = @<<<<<<<<<<<<<<<<<< $enumName, $enumHex ."," . select($outFile); @@ -5214,8 +5216,9 @@ sub packSingleSimpleTypeAttribute { { my $enumeration = getEnumerationType($$attributesRef,$simpleType-> {enumeration}->{id}); - #print STDOUT "id=$simpleType->{enumeration}->{id}\n"; - #print STDOUT "value=$value\n"; + +# print STDOUT "id=$simpleType->{enumeration}->{id}\n"; +# print STDOUT "value=$value\n"; #my %dummy1 = %{$enumeration}; #foreach (sort keys %dummy1) { # print STDOUT "---$_ : $dummy1{$_}\n"; @@ -5270,6 +5273,7 @@ sub packSingleSimpleTypeAttribute { if( ($simpleTypeProperties->{$typeName}{complexTypeSupport}) && ($value =~ m/[^0-9]/) && ($valueIsNegative eq 'false')) { + # This is a type that supports complex types - i.e. an integer and # the value is a string. Look for an enumeration named after the # attribute id, if one is not found then one of the function calls @@ -5922,6 +5926,7 @@ sub generateTargetingImage { # Use all attributes including virtual for association processing getTargetAttributes($targetInstance->{type}, $allAttributes,\%attrhash); + #Check for Targets with ZERO attributes before writing to PNOR. my $tempNumAttributes = keys %attrhash; if($tempNumAttributes == 0) @@ -5929,6 +5934,7 @@ sub generateTargetingImage { #skip the present target next; } +# print Dumper($allAttributes); # Update hash with any per-instance overrides, but only if that # attribute has already been defined @@ -5940,7 +5946,7 @@ sub generateTargetingImage { } else { - croak("Target instance \"$targetInstance->{id}\" cannot " + croak("Target instance \"$targetInstance->{id}\" of type \" $targetInstance->{type} \" cannot " . "override attribute \"$attr->{id}\" unless " . "the attribute has already been defined in the target " . "type inheritance chain."); diff --git a/src/usr/targeting/xmltohb/fapi_utils.pl b/src/usr/targeting/xmltohb/fapi_utils.pl new file mode 100755 index 000000000..7ba1c1fb1 --- /dev/null +++ b/src/usr/targeting/xmltohb/fapi_utils.pl @@ -0,0 +1,426 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/targeting/xmltohb/fapi_utils.pl $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2017 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# A collection of utility functions to convert fapi attributes to targeting attributes + +$XML::Simple::PREFERRED_PARSER = 'XML::Parser'; +my $xml = new XML::Simple (KeyAttr=>[]); +use Digest::MD5 qw(md5_hex); +use strict; + +# Convert a FAPI2 target type to the equivalent TARGETING type +# Input: fapi2 type +# Output: targeting type +sub convertTargetFapi2Targ +{ + my $fapitype = shift; + my $targtype; + + $targtype =~ s/\s//g; + $targtype =~ s/TARGET_TYPE_//; + $targtype =~ s/_ENDPOINT//; + $targtype =~ s/_CHIPLET//; + $targtype =~ s/_CHIP//; + $targtype =~ s/^SYSTEM$/SYS/; + + #todo - check result against list of types from target_types? + + return $targtype; +} + + +# Convert a FAPI2 value type to the equivalent TARGETING type +# Input: fapi2 type +# Output: targeting type +sub convertValueFapi2Targ +{ + my $fapitype = shift; + my $targtype = $fapitype; + + $targtype =~ s/(uint\d+)/$1_t/ if($fapitype =~ /^uint\d+$/); + $targtype =~ s/(int\d+)/$1_t/ if($fapitype =~ /^int\d+$/); + + #todo - check result against list of types from target_types? + + return $targtype; +} + +# Create a TARGETING style enumeration based on the enum tag from +# a FAPI2 attribute definition +# Input: fapi2 attribute +# Output: targeting enumeration +sub createEnumFromAttr(\%) +{ + my($fapiattr) = @_; + my @enums; + + if (exists $fapiattr->{enum}) + { + # description: passed as-is + my $fapiattr_id = $fapiattr->{id}; + my $id = $fapiattr_id; + $id =~ s/ATTR_//; + my $description = $fapiattr->{description}; + $description =~ s/^\s+|\s+$//g; + + + my $enum = $fapiattr->{enum}; + my @enumerators = split( /,/, $enum); + my @enumeratorHashArray; + + foreach my $enumerator (@enumerators) { + my %enumeratorHash; + chomp($enumerator); + $enumerator =~ s/^\s+|\s+$//g; + + my @nameVal = split( /=/, $enumerator); + + my $name = $nameVal[0]; + $name =~ s/^\s+|\s+$//g; + my $value = $nameVal[1]; + $value =~ s/^\s+|\s+$//g; + + my %enumeratorHash = ( + name => $name, + value => $value + ); + + push @enumeratorHashArray, \%enumeratorHash; + } + + my %enumToAdd = ( + id => $id, + description => $description, + ); + $enumToAdd{'enumerator'} = [@enumeratorHashArray]; + return \%enumToAdd + } +} + +# Create full attribute definition from a fapi2 attribute definition +# Input: hashmap of a single fapi attribute +# Output: hashmap of a single targeting attribute +sub createAttrFromFapi(\%) +{ + my($fapiattr) = @_; + my $targattr = {}; + + # id: passed as-is + my $fapiattr_id = $fapiattr->{id}; + my $id = $fapiattr_id; + $id =~ s/ATTR_//; + $targattr->{id} = $id; + + # description: passed as-is + my $description = $fapiattr->{description}; + $targattr->{description} = $description; + + # valueType: convert + my $valueType = convertValueFapi2Targ($fapiattr->{valueType}); + $targattr->{simpleType}->{$valueType} = {}; + + # writeable: passed as-is + if( exists $fapiattr->{writeable} ) + { + $targattr->{writeable} = {}; + } + + #default: modifies simpleType + if( exists $fapiattr->{default} ) + { + $targattr->{simpleType}->{$valueType}->{default} = + $fapiattr->{default}; + } + + #array: modifies simpleType + if( exists $fapiattr->{array} ) + { + my @dimensions = split(' ',$fapiattr->{array}); + my $dimensions_cs = @dimensions[0]; + for my $i ( 1 .. $#dimensions ) + { + $dimensions_cs .= ",$dimensions[$i]"; + } + $dimensions_cs =~ s/,,/,/g; + $targattr->{simpleType}->{array} = $dimensions_cs; + } + + #platInit: influences persistency + #initToZero: influences persistency + #overrideOnly: influences persistency + if( exists $fapiattr->{platInit} ) + { + if( exists $fapiattr->{overrideOnly} ) + { + $targattr->{persistency} = "volatile"; + } + else + { + $targattr->{persistency} = "non-volatile"; + } + } + elsif( exists $fapiattr->{initToZero} ) + { + if( exists $fapiattr->{default} ) + { + print "INVALID - $fapiattr_id has initToZero and a default\n"; + } + $targattr->{persistency} = "volatile-zeroed"; + } + elsif( exists $fapiattr->{default} ) + { + $targattr->{persistency} = "volatile"; + } + else + { + $targattr->{persistency} = "volatile-zeroed"; + } + + #mssUnits: ignore + #mssAccessorName: ignore + #odmVisible: ignore + #odmChangeable: ignore + #persistent: ignore + #persistRuntime: ignore + + #enum: ignored here + #targetType: ignored here + + #always add these + $targattr->{readable} = {}; + $targattr->{hwpfToHbAttrMap}->{id} = $fapiattr_id; + $targattr->{hwpfToHbAttrMap}->{macro} = "DIRECT"; + +# print Dumper($targattr); + +# printTargAttr($targattr); + + return $targattr; +} + +# Create targetTypeExtensions from a fapi2 attribute definition +# Input: hashmap of a single fapi attribute +# array of all targetTypeExtensions +sub createTargetExtensionFromFapi(\%,\%) +{ + my($fapiattr,$alltargext) = @_; + #print "createTargetExtensionFromFapi---\n"; + open my $FHSTDOUT, ">&STDOUT"; + + # Conversions from FAPI2 to TARGETING types + my $fapi2targ = { + TARGET_TYPE_SYSTEM => "sys-sys-power9", + TARGET_TYPE_DIMM => "lcard-dimm", + TARGET_TYPE_PROC_CHIP => "chip-processor", + TARGET_TYPE_MEMBUF_CHIP => "chip-membuf", + TARGET_TYPE_EX => "unit-ex-power9", + TARGET_TYPE_MBA => "unit-mba", + TARGET_TYPE_MCS => "unit-mcs-power9", + TARGET_TYPE_XBUS => "unit-xbus-power9", + TARGET_TYPE_ABUS => "unit-abus-power9", + TARGET_TYPE_L4 => "unit-l4-power9", + TARGET_TYPE_CORE => "unit-core-power9", + TARGET_TYPE_EQ => "unit-eq-power9", + TARGET_TYPE_MCA => "unit-mca-power9", + TARGET_TYPE_MCBIST => "unit-mcbist-power9", + TARGET_TYPE_MI => "unit-mi-power9", + TARGET_TYPE_CAPP => "unit-capp-power9", + TARGET_TYPE_DMI => "unit-dmi-power9", + TARGET_TYPE_OBUS => "unit-obus-power9", + TARGET_TYPE_NV => "unit-nv-power9", + TARGET_TYPE_SBE => "unit-sbe-power9", + TARGET_TYPE_PPE => "unit-ppe-power9", + TARGET_TYPE_PERV => "unit-perv-power9", + TARGET_TYPE_PEC => "unit-pec-power9", + TARGET_TYPE_PHB => "unit-phb-power9", + TARGET_TYPE_MC => "unit-mc-power9", + }; + + # Loop through all of the targets that this attribute + # is needed on (per fapi xml) + my @types = split(',',$fapiattr->{targetType}); + foreach my $type(@types) + { + my $foundmatch = 0; + $type =~ s/\s//g; + my $targtype = $fapi2targ->{$type}; + #print "type = $type -> $targtype\n"; + my $attrid = $fapiattr->{id}; + $attrid =~ s/ATTR_//; + + # create new attribute element + my $newattr = {}; + $newattr->{id} = $attrid; + + # look for an existing targetTypeExtension entry + # to modify with new attribute + foreach my $targ (@{$alltargext->{targetTypeExtension}}) + { + if( $targ->{id} =~ $targtype ) + { + #print "-Found it\n"; + $foundmatch = 1; + #printTargExt($FHSTDOUT,$targ); + my $attrlist = $targ->{attribute}; + push @$attrlist, $newattr; + #printTargExt($FHSTDOUT,$targ); + last; + } + } + + # no existing entry for this kind of target, make a new one + if( $foundmatch == 0 ) + { + #print "-No entry found for $targtype, creating new entry\n"; + my $newext = {}; + $newext->{id} = $targtype; + my $newarray = []; + push @$newarray, $newattr; + $newext->{attribute} = $newarray; + my $allext = $alltargext->{targetTypeExtension}; + push @$allext, $newext; + #printTargExt($FHSTDOUT,$newext); + } + } + + + #print Dumper($alltargets); + + +# print "---\n"; +# printTargTarg($targtarg); +# print "---done\n"; +} + + + +# Print string representation of a targeting attribute +# Input: hashmap of a single targeting attribute +# Output: string of xml tags +sub printTargAttr +{ + my($FH1,$targattr) = @_; + print $FH1 $xml->XMLout( $targattr, RootName => 'attribute', NoAttr => 1 ); +} + +# Print string representation of a targeting enumeration +# Input: hashmap of a single targeting enumeration +# Output: string of xml tags +sub printTargEnum +{ + my($FH1,$targattr) = @_; + print $FH1 $xml->XMLout( $targattr, RootName => 'enumerationType', NoAttr => 1 ); +} + +# Print string representation of a targeting target +# Input: hashmap of a single targeting target +# Output: string of xml tags +sub printTargTarg +{ + my($FH1,$targtarg) = @_; + print $FH1 $xml->XMLout( $targtarg, RootName => 'targetType', NoAttr => 1 ); +} + +# Print string representation of a targeting targetExtension +# Input: hashmap of a single targeting target +# Output: string of xml tags +sub printTargExt +{ + my($FH1,$targtarg) = @_; + print $FH1 $xml->XMLout( $targtarg, RootName => 'targetTypeExtension', NoAttr => 1 ); +} + +# getArrayDimmensions +# Description: for a given attribute hashMap , return the array dimmensions +# if the attribute type is an array +# input : hashMap of attribute xml +# return : String of CSV list that lists the array dimmensions +sub getArrayDimmensions{ + my (%attrHash) = @_; + my $retValue = ""; + + my $simpleType = %attrHash->{simpleType}; + + my @keys = keys (%$simpleType); + + for my $key (@keys) + { + if( $key eq "array") + { + $retValue .= %attrHash->{simpleType}->{$key}; + } + } + #eat whitespace + $retValue =~ s/\s+//g; + return $retValue; +} + +# getFuncionBackedAttrs +# Description: Lookup all of the attributes that HB is backing with functions +# input : full path to attribute_service.H +# return : array of attribute IDs that are function backed +sub getFuncionBackedAttrs { + my ($headerFile) = @_; + my @attrIdArray; + open(my $attr_service_fh, '<', $headerFile) || die "unable to open $headerFile"; + + foreach my $row (<$attr_service_fh>) + { + my $attrIndex = index($row, "ATTR_"); + my $getMacroIndex = index($row, "_GETMACRO(ID"); + if($getMacroIndex != -1) + { + my $attrToAdd = substr $row, $attrIndex, $getMacroIndex - $attrIndex; + push @attrIdArray, $attrToAdd; + print " $0> FOUND $attrToAdd GETMACRO\n"; + } + } + return @attrIdArray; +} + +# getAttrType +# Description: for a given attribute hashMap , return the attribute type +# input : hashMap of attribute xml +# return : string represention attribute type +sub getAttrType { + my (%attrHash) = @_; + my $retValue = ""; + + my $simpleType = %attrHash->{simpleType}; + + my @keys = keys (%$simpleType); + + for my $key (@keys) + { + if( $key ne "array") + { + $retValue .= $key; + } + } + return $retValue; +} + + +# need to return 1 for other modules to include this +1; diff --git a/src/usr/targeting/xmltohb/makefile b/src/usr/targeting/xmltohb/makefile index 2e34e4941..35fa36761 100755 --- a/src/usr/targeting/xmltohb/makefile +++ b/src/usr/targeting/xmltohb/makefile @@ -46,8 +46,6 @@ include ${COMMON_TARGETING_MAKEFILE} VPATH = ${COMMON_TARGETING_REL_PATH} FAPI_ATTR_SOURCE_DIR = ${ROOTPATH}/src/usr/hwpf/hwp -XMLTOHB_FAPIATTR_SOURCES = \ - ${addprefix ${FAPI_ATTR_SOURCE_DIR}/, ${FAPI_ATTR_SOURCES}} FAPI2_ATTR_XML_DIR = ${ROOTPATH}/src/import/hwpf/fapi2/xml/attribute_info HB_TEMP_DFLT_SOURCES = $(wildcard \ @@ -59,6 +57,7 @@ FAPIATTRSRVC_SOURCE = \ ${FAPI2_INCLUDE_PATH}/${ATTRIBUTE_SERVICE_H} + # Attribute XML files. FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/chips/p9/procedures/xml/attribute_info/*) FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/hwpf/fapi2/xml/attribute_info/*) @@ -66,45 +65,112 @@ FAPI2_ATTR_XML += $(wildcard $(ROOTPATH)/src/import/hwpf/fapi2/xml/attribute_inf # NOTE: The hb_temp_defaults.xml file is not a normal attribute file with the # normal structures that define the attribute itself. It temporarily # provides default values for new attributes defined in other files. -FAPI2_ATTR_XML := $(filter-out ${HB_TEMP_DFLT_SOURCES},$(FAPI2_ATTR_XML)) + +FAPI2_ATTR_XML := $(filter-out $(ROOTPATH)/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml,$(FAPI2_ATTR_XML)) +FAPI2_ATTR_XML := $(filter-out $(wildcard $(ROOTPATH)/src/import/hwpf/fapi2/xml/attribute_info/*~) ,$(FAPI2_ATTR_XML)) +FAPI2_ATTR_XML := $(filter-out $(wildcard $(ROOTPATH)/src/import/chips/p9/procedures/xml/attribute_info/*~),$(FAPI2_ATTR_XML)) XMLTOHB_FAPIATTR_SOURCES += ${FAPI2_ATTR_XML} -XMLTOHB_COMMON_ATTRIBUTE_SOURCES = attribute_types.xml -XMLTOHB_COMMON_TARGET_SOURCES = target_types.xml -XMLTOHB_HB_ATTRIBUTE_SOURCES = attribute_types_hb.xml -XMLTOHB_HB_TARGET_SOURCES = target_types_hb.xml +# Manually generated sources + +# Common +XMLTOHB_COMMON_ATTRIBUTE_TYPES = attribute_types.xml +XMLTOHB_COMMON_TARGET_TYPES = target_types.xml + +# HB only +XMLTOHB_HB_ATTRIBUTE_TYPES = attribute_types_hb.xml +XMLTOHB_HB_TARGET_TYPES = target_types_hb.xml + +# OP PowerVM only +XMLTOHB_OPPOWERVM_ATTRIBUTE_TYPES = attribute_types_oppowervm.xml +XMLTOHB_OPPOWERVM_TARGET_TYPES = target_types_oppowervm.xml + +# Empty Targeting XML - Needed to generate XMLTOHB_CONFIG_ATTRIBUTE_SOURCES +XMLTOHB_EMPTY_TARGET_TYPES = target_types_empty.xml + +# OP only +XMLTOHB_OPENPOWER_ATTRIBUTE_TYPES = attribute_types_openpower.xml +XMLTOHB_OPENPOWER_TARGET_TYPES = target_types_openpower.xml + +# Auto generated sources + +# EKB +# Common generated from EKB xml +XMLTOHB_EKB_ATTRIBUTE_TYPES = attribute_types_ekb.xml +XMLTOHB_EKB_TARGET_TYPES = target_types_ekb.xml + +# Config Sources +# Contains all sources in configuration +XMLTOHB_CONFIG_ATTRIBUTE_TYPES = attribute_types_config.xml +XMLTOHB_CONFIG_TARGET_TYPES = target_types_config.xml + +# SP Sources +# Contains xml that will be exported to SP +XMLTOHB_SP_ATTRIBUTE_TYPES = attribute_types_sp.xml +XMLTOHB_SP_TARGET_TYPES = target_types_sp.xml + +# SRC +# a_src = a + a_hb + a_xxx +# t_src = t + merge_extension(t_hb + t_xxx) +XMLTOHB_SRC_ATTRIBUTE_TYPES = attribute_types_src.xml +XMLTOHB_SRC_TARGET_TYPES = target_types_src.xml + + +# HBX +# a_hbx = a_ekb + a_xxx +# t_hbx = merge_extension(t_ekb + t_xxx) +#XMLTOHB_HBX_ATTRIBUTE_TYPES = attribute_types_hbx.xml +#XMLTOHB_HBX_TARGET_TYPES = target_types_hbx.xml + +# FULL +# a_full = a_src + a_ekb +# t_full = t_src + t_ekb +XMLTOHB_FULL_ATTRIBUTE_TYPES = attribute_types_full.xml +XMLTOHB_FULL_TARGET_TYPES = target_types_full.xml + +# attribute_customization +# hb_temp_defaults.xml + hb_customized_attrs.xml +XMLTOHB_ATTRIBUTE_CUSTOMIZATION = attribute_customization.xml + +#Note that order matters here , we want hb_customized_attrs to be first so it's defaults get picked up first +#if there are duplicates +XMLTOHB_ATTRIBUTE_CUSTOMIZATION_SOURCES += ${COMMON_TARGETING_REL_PATH}/${HB_CUSTOMIZED_ATTRS_XML} +XMLTOHB_ATTRIBUTE_CUSTOMIZATION_SOURCES += ${ROOTPATH}/src/import/hwpf/fapi2/xml/attribute_info/hb_temp_defaults.xml -# attribute files that are only included in power vm build. -XMLTOHB_OPPOWERVM_ATTRIBUTE_SOURCES = attribute_types_oppowervm.xml -XMLTOHB_OPPOWERVM_TARGET_SOURCES = target_types_oppowervm.xml +# SRC attribute sources +XMLTOHB_SRC_ATTRIBUTE_SOURCES += ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_COMMON_ATTRIBUTE_TYPES} +XMLTOHB_SRC_ATTRIBUTE_SOURCES += ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_HB_ATTRIBUTE_TYPES} +XMLTOHB_SRC_ATTRIBUTE_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPPOWERVM),${XMLTOHB_OPPOWERVM_ATTRIBUTE_TYPES}) +XMLTOHB_SRC_ATTRIBUTE_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPENPOWER),${XMLTOHB_OPENPOWER_ATTRIBUTE_TYPES}) -# attribute files that are only included in openpower build. -XMLTOHB_OPENPOWER_ATTRIBUTE_SOURCES = attribute_types_openpower.xml -XMLTOHB_OPENPOWER_TARGET_SOURCES = target_types_openpower.xml +# Config Sources +XMLTOHB_CONFIG_ATTRIBUTE_SOURCES += ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_COMMON_ATTRIBUTE_TYPES} +XMLTOHB_CONFIG_ATTRIBUTE_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPPOWERVM),${XMLTOHB_OPPOWERVM_ATTRIBUTE_TYPES}) +XMLTOHB_CONFIG_ATTRIBUTE_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPENPOWER),${XMLTOHB_OPENPOWER_ATTRIBUTE_TYPES}) -XMLTOHB_MERGED_COMMON_TARGET_SOURCES = target_types_merged.xml # The customize target file combines all targetTypeExtension files before # combining them with the common target_types.xml file. To include a new file, -# just add it to the XMLTOHB_TARGET_SOURCES. -XMLTOHB_CUSTOMIZE_TARGET_SOURCES = target_types_customize.xml +# just add it to the XMLTOHB_*_EXT_TARGET_SOURCES. +XMLTOHB_SRC_CUSTOMIZE_TARGET_SOURCES = target_types_customize_src.xml +XMLTOHB_CONFIG_CUSTOMIZE_TARGET_SOURCES = target_types.customize_config.xml + + +XMLTOHB_SRC_EXT_TARGET_SOURCES += ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_HB_TARGET_TYPES} +XMLTOHB_SRC_EXT_TARGET_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPPOWERVM),${XMLTOHB_OPPOWERVM_TARGET_TYPES}) +XMLTOHB_SRC_EXT_TARGET_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPENPOWER),${XMLTOHB_OPENPOWER_TARGET_TYPES}) + +XMLTOHB_CONFIG_EXT_TARGET_SOURCES += ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_EMPTY_TARGET_TYPES} +XMLTOHB_CONFIG_EXT_TARGET_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPPOWERVM),${XMLTOHB_OPPOWERVM_TARGET_TYPES}) +XMLTOHB_CONFIG_EXT_TARGET_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPENPOWER),${XMLTOHB_OPENPOWER_TARGET_TYPES}) -XMLTOHB_TARGET_SOURCES += ${XMLTOHB_HB_TARGET_SOURCES} -XMLTOHB_TARGET_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPPOWERVM),${XMLTOHB_OPPOWERVM_TARGET_SOURCES}) -XMLTOHB_TARGET_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPENPOWER),${XMLTOHB_OPENPOWER_TARGET_SOURCES}) #Define XMLTOHB_GENERIC_SOURCES -XMLTOHB_GENERIC_SOURCES += ${XMLTOHB_COMMON_ATTRIBUTE_SOURCES} -XMLTOHB_GENERIC_SOURCES += ${XMLTOHB_HB_ATTRIBUTE_SOURCES} -XMLTOHB_GENERIC_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPPOWERVM),${XMLTOHB_OPPOWERVM_ATTRIBUTE_SOURCES}) -XMLTOHB_GENERIC_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPENPOWER),${XMLTOHB_OPENPOWER_ATTRIBUTE_SOURCES}) -XMLTOHB_GENERIC_SOURCES += ${GENDIR}/${XMLTOHB_MERGED_COMMON_TARGET_SOURCES} -XMLTOHB_GENERIC_SOURCES += ${XMLTOHB_HB_TARGET_SOURCES} -XMLTOHB_GENERIC_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPPOWERVM),${XMLTOHB_OPPOWERVM_TARGET_SOURCES}) -XMLTOHB_GENERIC_SOURCES += $(if $(CONFIG_INCLUDE_XML_OPENPOWER),${XMLTOHB_OPENPOWER_TARGET_SOURCES}) +XMLTOHB_GENERIC_SOURCES += ${GENDIR}/${XMLTOHB_FULL_ATTRIBUTE_TYPES} +XMLTOHB_GENERIC_SOURCES += ${GENDIR}/${XMLTOHB_FULL_TARGET_TYPES} TEMP_DEFAULT_SOURCES = tempdefaults.xml @@ -123,7 +189,7 @@ XMLTOHB_SYSTEM_BINARIES += \ $(if $(CONFIG_SECUREBOOT),simics_NIMBUS_targeting.bin.protected) XMLTOHB_SYSTEM_BINARIES += \ $(if $(CONFIG_SECUREBOOT),simics_NIMBUS_targeting.bin.unprotected) - + XMLTOHB_SYSTEM_BINARIES += \ $(if $(CONFIG_SECUREBOOT),simics_CUMULUS_targeting.bin.protected) XMLTOHB_SYSTEM_BINARIES += \ @@ -142,12 +208,12 @@ XMLTOHB_SYSTEM_BINARIES += \ # @echo FAPI_ATTR_SOURCES = ${FAPI_ATTR_SOURCES} # @echo XMLTOHB_FAPIATTR_SOURCES = ${XMLTOHB_FAPIATTR_SOURCES} # @echo HB_TEMP_DFLT_SOURCES = ${HB_TEMP_DFLT_SOURCES} -# @echo XMLTOHB_COMMON_ATTRIBUTE_SOURCES = ${XMLTOHB_COMMON_ATTRIBUTE_SOURCES} -# @echo XMLTOHB_COMMON_TARGET_SOURCES = ${XMLTOHB_COMMON_TARGET_SOURCES} +# @echo XMLTOHB_COMMON_ATTRIBUTE_TYPES = ${XMLTOHB_COMMON_ATTRIBUTE_TYPES} +# @echo XMLTOHB_COMMON_TARGET_TYPES = ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_COMMON_TARGET_TYPES} # @echo TEMP_DEFAULT_SOURCES = ${TEMP_DEFAULT_SOURCES} -# @echo XMLTOHB_HB_ATTRIBUTE_SOURCES = ${XMLTOHB_HB_ATTRIBUTE_SOURCES} -# @echo XMLTOHB_HB_TARGET_SOURCES = ${XMLTOHB_HB_TARGET_SOURCES} -# @echo XMLTOHB_MERGED_COMMON_TARGET_SOURCES = ${XMLTOHB_MERGED_COMMON_TARGET_SOURCES} +# @echo XMLTOHB_HB_ATTRIBUTE_TYPES = ${XMLTOHB_HB_ATTRIBUTE_TYPES} +# @echo XMLTOHB_HB_TARGET_TYPES = ${XMLTOHB_HB_TARGET_TYPES} +# @echo XMLTOHB_SRC_TARGET_TYPES = ${XMLTOHB_SRC_TARGET_TYPES} # @echo TEMP_GENERIC_XML = ${TEMP_GENERIC_XML} # @echo VPATH = ${VPATH} @@ -156,14 +222,25 @@ EXTRA_PARTS = $(addprefix $(IMGDIR)/, $(XMLTOHB_SYSTEM_BINARIES)) CLEAN_TARGETS += $(addprefix $(GENDIR)/, ${XMLTOHB_SYSTEM_BINARIES}) CLEAN_TARGETS += $(addprefix $(GENDIR)/, ${XMLTOHB_SYSTEM_BINARIES:.bin=.xml}) CLEAN_TARGETS += ${GENDIR}/${HB_PLAT_ATTR_SRVC_H} -CLEAN_TARGETS += ${GENDIR}/${TEMP_GENERIC_XML} CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_GENERIC_XML} CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_FAPI_XML} -CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_MERGED_COMMON_TARGET_SOURCES} CLEAN_TARGETS += ${GENDIR}/errl/errludattribute.H CLEAN_TARGETS += ${GENDIR}/errl/errludtarget.H CLEAN_TARGETS += ${GENDIR}/targAttrInfo.csv CLEAN_TARGETS += ${GENDIR}/targAttrOverrideData.H +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_SRC_TARGET_TYPES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_SRC_ATTRIBUTE_TYPES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_CONFIG_ATTRIBUTE_TYPES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_CONFIG_TARGET_TYPES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_SRC_CUSTOMIZE_TARGET_SOURCES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_CONFIG_CUSTOMIZE_TARGET_SOURCES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_SP_ATTRIBUTE_TYPES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_SP_TARGET_TYPES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_EKB_ATTRIBUTE_TYPES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_EKB_TARGET_TYPES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_FULL_ATTRIBUTE_TYPES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_FULL_TARGET_TYPES} +CLEAN_TARGETS += ${GENDIR}/${XMLTOHB_ATTRIBUTE_CUSTOMIZATION} GENDIR_ERRL = $(ROOTPATH)/obj/genfiles/errl @@ -173,24 +250,93 @@ CLEAN_TARGETS += $(XMLTOHB_RAN_INDICATION) COPYHDR_RAN_INDICATION = $(GENDIR)/.called_copy_attrsrvhdr CLEAN_TARGETS += $(COPYHDR_RAN_INDICATION) +GEN_PASS_BODY += ${GENDIR}/${XMLTOHB_CONFIG_ATTRIBUTE_TYPES} +GEN_PASS_BODY += ${GENDIR}/${XMLTOHB_CONFIG_TARGET_TYPES} +GEN_PASS_BODY += ${GENDIR}/${XMLTOHB_SP_ATTRIBUTE_TYPES} +GEN_PASS_BODY += ${GENDIR}/${XMLTOHB_SP_TARGET_TYPES} + include ${ROOTPATH}/config.mk # Delete any generated file on error -.DELETE_ON_ERROR: +# # .DELETE_ON_ERROR: ${EXTRA_PARTS}: ${IMGDIR}/% : ${GENDIR}/% cp -f $^ $@ +# create merged config attribute xml +${GENDIR}/${XMLTOHB_CONFIG_ATTRIBUTE_TYPES}: \ + ${XMLTOHB_MERGE_SCRIPT} ${XMLTOHB_CONFIG_ATTRIBUTE_SOURCES} + $< $(wordlist 2,$(words $^),$^) > $@ + +# create merged src attribute xml +${GENDIR}/${XMLTOHB_SRC_ATTRIBUTE_TYPES}: \ + ${XMLTOHB_MERGE_SCRIPT} ${XMLTOHB_SRC_ATTRIBUTE_SOURCES} + $< $(wordlist 2,$(words $^),$^) > $@ + +# create merged src target xml +${GENDIR}/${XMLTOHB_SRC_CUSTOMIZE_TARGET_SOURCES}: \ + ${XMLTOHB_MERGE_SCRIPT} ${XMLTOHB_SRC_EXT_TARGET_SOURCES} + $< $(wordlist 2,$(words $^),$^) > $@ + +# TODO RTC: 178228 Review usage of XMLTOHB_TARGET_MERGE_SCRIPT in this makefile +${GENDIR}/${XMLTOHB_SRC_TARGET_TYPES}: \ + ${XMLTOHB_TARGET_MERGE_SCRIPT} ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_COMMON_TARGET_TYPES} \ + ${GENDIR}/${XMLTOHB_SRC_CUSTOMIZE_TARGET_SOURCES} + ./${XMLTOHB_TARGET_MERGE_SCRIPT} $(addprefix --hb=,${GENDIR}/${XMLTOHB_SRC_CUSTOMIZE_TARGET_SOURCES}) \ + $(addprefix --common=,${COMMON_TARGETING_REL_PATH}/${XMLTOHB_COMMON_TARGET_TYPES}) > $@ -# create merged target xml -${GENDIR}/${XMLTOHB_CUSTOMIZE_TARGET_SOURCES}: \ - ${XMLTOHB_MERGE_SCRIPT} ${XMLTOHB_TARGET_SOURCES} +# create merged config target xml +${GENDIR}/${XMLTOHB_CONFIG_CUSTOMIZE_TARGET_SOURCES}: \ + ${XMLTOHB_MERGE_SCRIPT} ${XMLTOHB_CONFIG_EXT_TARGET_SOURCES} $< $(wordlist 2,$(words $^),$^) > $@ -${GENDIR}/${XMLTOHB_MERGED_COMMON_TARGET_SOURCES}: \ - ${XMLTOHB_TARGET_MERGE_SCRIPT} ${XMLTOHB_COMMON_TARGET_SOURCES} ${GENDIR}/${XMLTOHB_CUSTOMIZE_TARGET_SOURCES} - ./${XMLTOHB_TARGET_MERGE_SCRIPT} $(addprefix --hb=,${GENDIR}/${XMLTOHB_CUSTOMIZE_TARGET_SOURCES}) \ - $(addprefix --common=,${COMMON_TARGETING_REL_PATH}/${XMLTOHB_COMMON_TARGET_SOURCES}) > $@ +# TODO RTC: 178228 Review usage of XMLTOHB_TARGET_MERGE_SCRIPT in this makefile +${GENDIR}/${XMLTOHB_CONFIG_TARGET_TYPES}: \ + ${XMLTOHB_TARGET_MERGE_SCRIPT} ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_COMMON_TARGET_TYPES} \ + ${GENDIR}/${XMLTOHB_CONFIG_CUSTOMIZE_TARGET_SOURCES} + ./${XMLTOHB_TARGET_MERGE_SCRIPT} $(addprefix --hb=,${GENDIR}/${XMLTOHB_CONFIG_CUSTOMIZE_TARGET_SOURCES}) \ + $(addprefix --common=,${COMMON_TARGETING_REL_PATH}/${XMLTOHB_COMMON_TARGET_TYPES}) > $@ + + +# TODO RTC: 178228 Review usage of XMLTOHB_TARGET_MERGE_SCRIPT in this makefile +# create merged full target xml +${GENDIR}/${XMLTOHB_FULL_TARGET_TYPES}: \ + ${XMLTOHB_TARGET_MERGE_SCRIPT} ${GENDIR}/${XMLTOHB_EKB_TARGET_TYPES} \ + ${GENDIR}/${XMLTOHB_SRC_TARGET_TYPES} ${GENDIR}/${XMLTOHB_SRC_ATTRIBUTE_TYPES} \ + ${GENDIR}/${XMLTOHB_EKB_TARGET_TYPES} ${GENDIR}/${XMLTOHB_FULL_ATTRIBUTE_TYPES} + ./${XMLTOHB_TARGET_MERGE_SCRIPT} $(addprefix --hb=,${GENDIR}/${XMLTOHB_EKB_TARGET_TYPES}) \ + $(addprefix --common=,${GENDIR}/${XMLTOHB_SRC_TARGET_TYPES}) > $@ + ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_SWAP_MAPPED_ATTR_SCRIPT} \ + $(addprefix --srcTargetXml=,${GENDIR}/${XMLTOHB_SRC_TARGET_TYPES}) \ + $(addprefix --ekbTargetXml=,${GENDIR}/${XMLTOHB_EKB_TARGET_TYPES}) \ + $(addprefix --fullAttrXml=,${GENDIR}/${XMLTOHB_FULL_ATTRIBUTE_TYPES}) \ + $(addprefix --fullTargetXml=,${GENDIR}/${XMLTOHB_FULL_TARGET_TYPES}) \ + $(addprefix --fapi2Header=,${ROOTPATH}/src/include/usr/fapi2/attribute_service.H) + echo '<attributes>' | cat - ${GENDIR}/${XMLTOHB_FULL_TARGET_TYPES} > tempFull && mv tempFull ${GENDIR}/${XMLTOHB_FULL_TARGET_TYPES} + echo '</attributes>' | cat ${GENDIR}/${XMLTOHB_FULL_TARGET_TYPES} - > tempFull && mv tempFull ${GENDIR}/${XMLTOHB_FULL_TARGET_TYPES} + +# TODO RTC: 178228 Review usage of XMLTOHB_TARGET_MERGE_SCRIPT in this makefile +# create merged sp target xml +${GENDIR}/${XMLTOHB_SP_TARGET_TYPES}: \ + ${XMLTOHB_TARGET_MERGE_SCRIPT} ${GENDIR}/${XMLTOHB_EKB_TARGET_TYPES} \ + ${GENDIR}/${XMLTOHB_CONFIG_TARGET_TYPES} ${GENDIR}/${XMLTOHB_CONFIG_ATTRIBUTE_TYPES} \ + ${GENDIR}/${XMLTOHB_EKB_TARGET_TYPES} ${GENDIR}/${XMLTOHB_SP_ATTRIBUTE_TYPES} + ./${XMLTOHB_TARGET_MERGE_SCRIPT} $(addprefix --hb=,${GENDIR}/${XMLTOHB_EKB_TARGET_TYPES}) \ + $(addprefix --common=,${GENDIR}/${XMLTOHB_CONFIG_TARGET_TYPES}) > $@ + ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_SWAP_MAPPED_ATTR_SCRIPT} \ + $(addprefix --srcTargetXml=,${GENDIR}/${XMLTOHB_CONFIG_TARGET_TYPES}) \ + $(addprefix --ekbTargetXml=,${GENDIR}/${XMLTOHB_EKB_TARGET_TYPES}) \ + $(addprefix --fullAttrXml=,${GENDIR}/${XMLTOHB_SP_ATTRIBUTE_TYPES}) \ + $(addprefix --fullTargetXml=,${GENDIR}/${XMLTOHB_SP_TARGET_TYPES}) \ + $(addprefix --fapi2Header=,${ROOTPATH}/src/include/usr/fapi2/attribute_service.H) + echo '<attributes>' | cat - ${GENDIR}/${XMLTOHB_SP_TARGET_TYPES} > tempSp && mv tempSp ${GENDIR}/${XMLTOHB_SP_TARGET_TYPES} + echo '</attributes>' | cat ${GENDIR}/${XMLTOHB_SP_TARGET_TYPES} - > tempSp && mv tempSp ${GENDIR}/${XMLTOHB_SP_TARGET_TYPES} + ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_REMOVE_HB_MAPPED_ATTR_SCRIPT} \ + $(addprefix --spAttrXml=,${GENDIR}/${XMLTOHB_SP_ATTRIBUTE_TYPES}) \ + $(addprefix --spTargXml=,${GENDIR}/${XMLTOHB_SP_TARGET_TYPES}) \ + $(addprefix --hbAttrXml=,${COMMON_TARGETING_REL_PATH}/${XMLTOHB_HB_ATTRIBUTE_TYPES}) \ + + # merge all FAPI attribute files into one ${GENDIR}/${XMLTOHB_FAPI_XML}: ${XMLTOHB_MERGE_SCRIPT} \ @@ -203,23 +349,51 @@ $(COPYHDR_RAN_INDICATION): ${FAPIATTRSRVC_SOURCE} cp ${FAPIATTRSRVC_SOURCE} ${GENDIR}/${HB_PLAT_ATTR_SRVC_H} touch $(COPYHDR_RAN_INDICATION) -# temp generic XML is created from the generic sources only -${GENDIR}/${TEMP_GENERIC_XML}: \ - ${XMLTOHB_MERGE_SCRIPT} ${XMLTOHB_GENERIC_SOURCES} +# merge all attribute customization srcs together +${GENDIR}/${XMLTOHB_ATTRIBUTE_CUSTOMIZATION}: ${XMLTOHB_MERGE_SCRIPT} \ + ${XMLTOHB_ATTRIBUTE_CUSTOMIZATION_SOURCES} $< $(wordlist 2,$(words $^),$^) > $@ -# generic XML is created from temp generic XML, temporary defaults, merged FAPI -# attributes, and HB temp defaults +# convert FAPI attrs to HB attrs +${GENDIR}/${XMLTOHB_EKB_ATTRIBUTE_TYPES} \ +${GENDIR}/${XMLTOHB_EKB_TARGET_TYPES}: \ + ${XMLTOHB_EKB_TARGATTR_SCRIPT} ${GENDIR}/${XMLTOHB_FAPI_XML} \ + fapi_utils.pl ${GENDIR}/${XMLTOHB_ATTRIBUTE_CUSTOMIZATION} + ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_EKB_TARGATTR_SCRIPT} \ + $(addprefix --fapi=,${GENDIR}/${XMLTOHB_FAPI_XML}) \ + $(addprefix --attr=,${GENDIR}/${XMLTOHB_EKB_ATTRIBUTE_TYPES}) \ + $(addprefix --targ=,${GENDIR}/${XMLTOHB_EKB_TARGET_TYPES}) \ + $(addprefix --default=,${GENDIR}/${XMLTOHB_ATTRIBUTE_CUSTOMIZATION})\ + + +# Add EKB attribute xml to src xml to produce the final output. +# Skip adding any attributes that already exists in the src xml +${GENDIR}/${XMLTOHB_FULL_ATTRIBUTE_TYPES}: \ + ${XMLTOHB_DUPLICATE_SCRIPT} ${GENDIR}/${XMLTOHB_EKB_ATTRIBUTE_TYPES} \ + ${GENDIR}/${XMLTOHB_SRC_ATTRIBUTE_TYPES} + ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_DUPLICATE_SCRIPT} \ + $(addprefix --ekbXmlFile=,${GENDIR}/${XMLTOHB_EKB_ATTRIBUTE_TYPES}) \ + $(addprefix --hbXmlFile=,${GENDIR}/${XMLTOHB_SRC_ATTRIBUTE_TYPES}) \ + $(addprefix --fapi2Header=,${ROOTPATH}/src/include/usr/fapi2/attribute_service.H) \ + $(addprefix --outFile=,${GENDIR}/${XMLTOHB_FULL_ATTRIBUTE_TYPES}) \ + --verbose + +# Add EKB attribute xml to config xml to produce the final output. +# Skip adding any attributes that already exists in the src xml +${GENDIR}/${XMLTOHB_SP_ATTRIBUTE_TYPES}: \ + ${XMLTOHB_DUPLICATE_SCRIPT} ${GENDIR}/${XMLTOHB_EKB_ATTRIBUTE_TYPES} \ + ${GENDIR}/${XMLTOHB_CONFIG_ATTRIBUTE_TYPES} + ${COMMON_TARGETING_REL_PATH}/${XMLTOHB_DUPLICATE_SCRIPT} \ + $(addprefix --ekbXmlFile=,${GENDIR}/${XMLTOHB_EKB_ATTRIBUTE_TYPES}) \ + $(addprefix --hbXmlFile=,${GENDIR}/${XMLTOHB_CONFIG_ATTRIBUTE_TYPES}) \ + $(addprefix --fapi2Header=,${ROOTPATH}/src/include/usr/fapi2/attribute_service.H) \ + $(addprefix --outFile=,${GENDIR}/${XMLTOHB_SP_ATTRIBUTE_TYPES}) \ + --verbose + +# generic XML is created from the generic sources only ${GENDIR}/${XMLTOHB_GENERIC_XML}: \ - ${XMLTOHB_TEMPS_MERGE_SCRIPT} ${GENDIR}/${TEMP_GENERIC_XML} \ - ${GENDIR}/${XMLTOHB_FAPI_XML} \ - ${HB_TEMP_DFLT_SOURCES} ${TEMP_DEFAULT_SOURCES} - ./${XMLTOHB_TEMPS_MERGE_SCRIPT} \ - --generic=${GENDIR}/${TEMP_GENERIC_XML} \ - --fapi=${GENDIR}/${XMLTOHB_FAPI_XML} \ - --fapi_inc=${ROOTPATH}/src/include/usr/fapi2/attribute_service.H \ - --fw_dflts=${HB_TEMP_DFLT_SOURCES} \ - --defaults=${COMMON_TARGETING_REL_PATH}/${TEMP_DEFAULT_SOURCES} > $@ + ${XMLTOHB_MERGE_SCRIPT} ${XMLTOHB_GENERIC_SOURCES} + $< $(wordlist 2,$(words $^),$^) > $@ # create the header files, only needs generic xml $(call GENTARGET,$(XMLTOHB_TARGETS)) : $(XMLTOHB_RAN_INDICATION) @@ -233,6 +407,7 @@ $(XMLTOHB_RAN_INDICATION): ${XMLTOHB_COMPILER_SCRIPT} \ cp ${GENDIR_ERRL}/errludtarget.H ${GENDIR_PLUGINS} touch $(XMLTOHB_RAN_INDICATION) +# .PRECIOUS: ${GENDIR}/%.hb.xml # system-specific XML needs the generic xml plus the xxx.system.xml file + the # MRW file ${GENDIR}/%.hb.xml: %.system.xml ${GENDIR}/${XMLTOHB_GENERIC_XML} %.mrw.xml diff --git a/src/usr/targeting/xmltohb/updatetargetxml.pl b/src/usr/targeting/xmltohb/updatetargetxml.pl index 8d86159df..11b38c3ba 100755 --- a/src/usr/targeting/xmltohb/updatetargetxml.pl +++ b/src/usr/targeting/xmltohb/updatetargetxml.pl @@ -6,7 +6,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2012,2014 +# Contributors Listed Below - COPYRIGHT 2012,2017 # [+] International Business Machines Corp. # # @@ -83,7 +83,7 @@ foreach my $Extension ( @{$generic->{targetTypeExtension}} ) { $default = $attr->{default}->[0]; } - #print "$id, $attribute_id $default\n"; + if (! exists $generic1->{targetType}->{$id}->{attribute}->{$attribute_id}) { push @NewAttr, [ $id, $attribute_id, $default ]; @@ -91,6 +91,11 @@ foreach my $Extension ( @{$generic->{targetTypeExtension}} ) } } +#for my $i ( 0 .. $#NewAttr ) +#{ + # print STDERR "$NewAttr[$i][0], $NewAttr[$i][1], $NewAttr[$i][2]\n"; +#} + open (FH, "<$common"); my $check = 0; |
