INITPROC: Hostboot - Updated HWPs from defect SW218634

SW218634

Change-Id: Ie328e419de7cf6228ac3068775a2ddc068972678
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5874
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

8 files changed, 388 insertions, 77 deletions

diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C
index bcdacc19e..2b3a0a3cf 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_image_help_base.C,v 1.13 2013/06/10 22:09:49 jeshua Exp $
+// $Id: p8_image_help_base.C,v 1.14 2013-08-01 13:34:16 dcrowell Exp $
 /*------------------------------------------------------------------------------*/
 /* *! TITLE : p8_image_help_base.c                                              */
 /* *! DESCRIPTION : Basic helper functions for building and extracting          */
@@ -486,7 +486,8 @@ int over_write_ring_data_in_image(  void            *io_image,
   hostVectorThis = (void*) ( (uint64_t)hostVectorBase + 
                              i_idxVector*8*(1+i_overridable) +
                              8*i_override*i_overridable );
-  hostRingBlock = (DeltaRingLayout*)(*(uintptr_t*)hostVectorThis);
+  uint64_t tmp1 = (*(uintptr_t*)hostVectorThis);
+  sbe_xip_pore2host( io_image, tmp1, (void**)&hostRingBlock);
   hostRingData = (void*)( (uint64_t)hostRingBlock + hostRingBlock->entryOffset );
 
   // Over write ringData onto existing ring data content in image.
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C
index 07cb97413..2f7d44778 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pore_table_gen_api_fixed.C,v 1.7 2013/05/08 20:16:18 cmolsen Exp $
+// $Id: p8_pore_table_gen_api_fixed.C,v 1.9 2013/05/29 18:58:28 cmolsen Exp $
 //
 /*------------------------------------------------------------------------------*/
 /* *! (C) Copyright International Business Machines Corp. 2012                  */
@@ -41,7 +41,6 @@
 /*------------------------------------------------------------------------------*/
 
 #define __P8_PORE_TABLE_GEN_API_C
-#include <HvPlicModule.H>
 #include <p8_pore_api_custom.h>
 #include <p8_pore_table_gen_api.H>
 #include <p8_delta_scan_rw.h>
@@ -566,14 +565,14 @@ uint32_t p8_pore_gen_scom_fixed(  void       *io_image,
   //   SCOM is replacing that NNNN sequence.
   hostScomEntryNext = hostScomTableThis;
   MY_DBG("hostScomEntryNext (addr): 0x%016llx\n ",(uint64_t)hostScomEntryNext);
-  while (memcmp(hostScomEntryNext, bufRET, sizeof(uint32_t))) {
+  while (memcmp(hostScomEntryNext, bufRET, sizeof(uint32_t)))  {
     entriesCount++;
     MY_DBG("Number of SCOM entries: %i\n ",entriesCount);
     if (*((uint32_t*)bufIIS+1)==*((uint32_t*)hostScomEntryNext+1) && entriesMatch==0)  {// +1 skips 1st word in Scom entry (which loads the PC in an LS operation.)
       hostScomEntryMatch = hostScomEntryNext;
       entriesMatch++;
     }
-    if ((0 == memcmp(hostScomEntryNext, bufNOP, sizeof(uint32_t))) && entriesNOP==0)  {
+    if (memcmp(hostScomEntryNext, bufNOP, sizeof(uint32_t))==0 && entriesNOP==0)  {
       hostScomEntryNOP = hostScomEntryNext;
       entriesNOP++;
     }
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
index 951a42ef9..85c64f1e0 100755
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit.C,v 1.50 2013/07/17 15:50:58 mwuu Exp $
+// $Id: mss_draminit.C,v 1.51 2013/08/01 18:36:52 jdsloat Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -28,6 +28,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.51   | jdsloat  | 08/01/13| Fixed dimm/rank conversion in address mirroring phy setting for a 4 rank dimm scenario
 //  1.50   | mwuu     | 07/17/13| Fixed CS when accessing RCD words on 1 rank RDIMMs
 //         |          |         | Added checks for invalid RTT_NOM, RTT_WR
 //  1.49   | jdsloat  | 06/11/13| Added several rc checks
@@ -300,13 +301,13 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 	    {
 
 	        // dimm 0, dimm_rank 0-3 = ranks 0-3; dimm 1, dimm_rank 0-3 = ranks 4-7
-	        pri_dimm = (primary_ranks_array[rank_pair_group][port_number] + 1) / 4;
+	        pri_dimm = (primary_ranks_array[rank_pair_group][port_number]) / 4;
 	        pri_dimm_rank = primary_ranks_array[rank_pair_group][port_number] - 4*pri_dimm;
-	        sec_dimm = (secondary_ranks_array[rank_pair_group][port_number] + 1) / 4;
+	        sec_dimm = (secondary_ranks_array[rank_pair_group][port_number]) / 4;
 	        sec_dimm_rank = secondary_ranks_array[rank_pair_group][port_number] - 4*sec_dimm;
-	        ter_dimm = (tertiary_ranks_array[rank_pair_group][port_number] + 1) / 4;
+	        ter_dimm = (tertiary_ranks_array[rank_pair_group][port_number]) / 4;
 	        ter_dimm_rank = tertiary_ranks_array[rank_pair_group][port_number] - 4*ter_dimm;
-	        qua_dimm = (quaternary_ranks_array[rank_pair_group][port_number] + 1) / 4;
+	        qua_dimm = (quaternary_ranks_array[rank_pair_group][port_number]) / 4;
 	        qua_dimm_rank = quaternary_ranks_array[rank_pair_group][port_number] - 4*qua_dimm;
 
 		// Set the rank pairs that will be affected.
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
index dfb063a1a..06f984ab9 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_training.C,v 1.62 2013/07/17 16:20:12 mwuu Exp $
+// $Id: mss_draminit_training.C,v 1.64 2013/08/01 18:32:48 jdsloat Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -28,7 +28,9 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|------------------------------------------------
-//  1.62   | mwuu     |17-JUL-13| Fixed set_bbm function to disable0,disable1,wr_clk registers
+//  1.64   | jdsloat  |01-AUG-13| Fixed dimm/rank conversion in address mirroring mode for a 4 rank dimm scenario
+//  1.63   | jdsloat  |29-JUN-13| Added JTAG mode and CONTROL SWITCH attribute checks to bad bit mask function calls.
+//  1.62   | mwuu     |17-JUN-13| Fixed set_bbm function to disable0,disable1,wr_clk registers
 //         |          |         | In x4 single bit fails disables entire nibble in set/get_bbm FN
 //  1.61   | jdsloat  |13-JUN-13| Added a single RC check
 //  1.60   | jdsloat  |11-JUN-13| Added a single RC check
@@ -300,6 +302,14 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
     rc = fapiGetParentChip(i_target, l_target_centaur);
     if(rc) return rc;
 
+    uint8_t control_switch = 0;
+    rc = FAPI_ATTR_GET(ATTR_MSS_CONTROL_SWITCH, NULL, control_switch);
+    if(rc) return rc;
+
+    uint8_t jtag_mode = 0;
+    rc = FAPI_ATTR_GET(ATTR_LAB_USE_JTAG_MODE, NULL, jtag_mode);
+    if(rc) return rc;
+
     uint8_t dram_gen = 0;
     rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen);
     if(rc) return rc;
@@ -368,12 +378,14 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
     rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64);
     if(rc) return rc;
 
-
-    rc = mss_set_bbm_regs (i_target);
-    if(rc)
+    if ( ( control_switch && 0x01 ) && (jtag_mode == 0) )
     {
-	FAPI_ERR( "Error Moving bad bit information to the Phy regs. Exiting.");
-	return rc;
+        rc = mss_set_bbm_regs (i_target);
+        if(rc)
+        {
+	   FAPI_ERR( "Error Moving bad bit information to the Phy regs. Exiting.");
+	   return rc;
+        }
     }
 
     if ( ( cal_steps_8.isBitSet(0) ) ||
@@ -713,12 +725,15 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 		if(rc) return rc;
     }
 
-    rc = mss_get_bbm_regs(i_target);
-    if(rc)
+    if ( ( control_switch && 0x01 ) && (jtag_mode == 0) )
+    {
+    	rc = mss_get_bbm_regs(i_target);
+    	if(rc)
 	{
-	FAPI_ERR( "Error Moving bad bit information from the Phy regs. Exiting.");
-	return rc;
+		FAPI_ERR( "Error Moving bad bit information from the Phy regs. Exiting.");
+		return rc;
 	}
+    }
 
     if (complete_status == MSS_INIT_CAL_STALL)
     {
@@ -2527,7 +2542,7 @@ ReturnCode mss_rtt_nom_rtt_wr_swap(
     uint8_t dimm_rank = 0;
 
     // dimm 0, dimm_rank 0-3 = ranks 0-3; dimm 1, dimm_rank 0-3 = ranks 4-7
-    dimm = (i_rank + 1) / 4;
+    dimm = (i_rank) / 4;
     dimm_rank = i_rank - 4*dimm;
 
 
diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
index 96b7ce8c2..7985a31fb 100644
--- a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: cen.dmi.scom.initfile,v 1.12 2013/04/18 19:20:14 jgrell Exp $ 
+#-- $Id: cen.dmi.scom.initfile,v 1.16 2013/07/30 20:47:07 jgrell Exp $ 
 
 
 ####################################################################
@@ -7,14 +7,18 @@
 ##      Based on SETUP_ID_MODE DMI_BUS_TR_HW
 ##      from ../../logic/mesa_sim/fusion/run/IODNC_MB_TOP.IODNC_MB_TOP.figdb
 ##
-##   Created on Mon Apr 15 15:04:16 CDT 2013, by jgrell
+##   Created on Tue Jul 30 10:22:33 CDT 2013, by jgrell
 ####################################################################
 
 ## -- CHANGE HISTORY:
  ## --------------------------------------------------------------------------------
  ## -- VersionID: |Author:  | Date:  | Comment:
  ## -- -----------|---------|--------|-------------------------------------------------
+ ## -- jfg13072400| jfg     |07-24-13| HW253558: change pgooddly to MAX from lab feedback
+ ## -- mbs13071200| mbs     |07-12-13| Disable recal adjustment for allv1 (DFE bug)     
+ ## -- mbs13071100| mbs     |07-11-13| Updates for HW239870 and HW258990                
  ## -- jgr13041800| jgr     |04-18-13| Added rx_max_ber_check_count setting to 0x03
+ ## -- smr13032500| SMR     |03-25-13| Changed rx_dyn_recal_overall_timeout_sel init to 0b100 & rx_sls_timeout_sel init to 0b110
  ## -- jgr13031300| jgr     |03-13-13| Added missing entries from rel 0128
  ## -- mbs13011802| mbs     |01-18-13| Added rx_fence to run_mode dial (HW236326)
  ## -- mbs13011000| mbs     |01-10-13| Added rx_prot_speed_slct and rx_c4_sel
@@ -91,7 +95,7 @@ scom 0x800B80000201043F {
 	bits, scom_data, expr;
      rx_ber_cfg,  0b100   , def_IS_HW;
      rx_ber_cfg,  0b000  , def_IS_VBU;
-     rx_dac_bo_cfg,  0b100   , def_IS_HW;
+     rx_dac_bo_cfg,  0b101   , def_IS_HW;
      rx_dac_bo_cfg,  0b000  , def_IS_VBU;
      rx_ddc_cfg,  0b10   , def_IS_HW;
      rx_ddc_cfg,  0b00  , def_IS_VBU;
@@ -104,7 +108,13 @@ scom 0x800B80000201043F {
 #RX.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG
 scom 0x800A18000201043F { 
 	bits, scom_data, expr;
-	rx_dyn_recal_overall_timeout_sel, 0b001, any;
+	rx_dyn_recal_overall_timeout_sel, 0b100, any;
+}
+
+#RX.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_TIMEOUTS_PP
+scom 0x800B40000201043F { 
+	bits, scom_data, expr;
+	rx_dyn_recal_interval_timeout_sel, 0b101, any;
 }
 
 #RX.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
@@ -198,13 +208,6 @@ scom 0x8009C0000201043F {
      rx_prot_speed_slct,  0b0  , def_IS_VBU;
 }
 
-#RX.RXCTL.RX_CTL_REGS.RX_MODE1_PP
-scom 0x800B08000201043F { 
-	bits, scom_data, expr;
-     rx_bit_lock_timeout_sel,  0b110   , def_IS_HW;
-     rx_bit_lock_timeout_sel,  0b101  , def_IS_VBU;
-}
-
 #RX.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
 scom 0x800AB8000201043F { 
 	bits, scom_data, expr;
@@ -214,10 +217,8 @@ scom 0x800AB8000201043F {
      rx_rc_enable_ctle_cal,  0b0  , def_IS_VBU;
      rx_rc_enable_ddc,  0b1   , def_IS_HW;
      rx_rc_enable_ddc,  0b0  , def_IS_VBU;
-     rx_rc_enable_dfe_h1_cal,  0b1   , def_IS_HW;
-     rx_rc_enable_dfe_h1_cal,  0b0  , def_IS_VBU;
-     rx_rc_enable_h1ap_tweak,  0b1   , def_IS_HW;
-     rx_rc_enable_h1ap_tweak,  0b0  , def_IS_VBU;
+	rx_rc_enable_dfe_h1_cal, 0b0, any;
+	rx_rc_enable_h1ap_tweak, 0b0, any;
      rx_rc_enable_latch_offset_cal,  0b1   , def_IS_HW;
      rx_rc_enable_latch_offset_cal,  0b0  , def_IS_VBU;
      rx_rc_enable_result_check,  0b1   , def_IS_HW;
@@ -229,13 +230,15 @@ scom 0x800AB8000201043F {
 #RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP
 scom 0x800B90000201043F { 
 	bits, scom_data, expr;
-     rx_recal_timeout_sel_b,  0b0100   , def_IS_HW;
+     rx_recal_timeout_sel_b,  0b0110   , def_IS_HW;
      rx_recal_timeout_sel_b,  0b1000  , def_IS_VBU;
 }
 
 #RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP
 scom 0x800B98000201043F { 
 	bits, scom_data, expr;
+     rx_recal_timeout_sel_g,  0b0111   , def_IS_HW;
+     rx_recal_timeout_sel_g,  0b0100  , def_IS_VBU;
      rx_recal_timeout_sel_h,  0b1011   , def_IS_HW;
      rx_recal_timeout_sel_h,  0b1000  , def_IS_VBU;
 }
@@ -251,26 +254,21 @@ scom 0x800BA0000201043F {
      rx_recal_timeout_sel_k,  0b1000  , def_IS_VBU;
 }
 
-#RX.RXCTL.RX_CTL_REGS.RX_SCOPE_CNTL_PP
-scom 0x800BC0000201043F { 
-	bits, scom_data, expr;
-     rx_scope_control,  0b01   , def_IS_HW;
-     rx_scope_control,  0b00  , def_IS_VBU;
-}
-
 #RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
 scom 0x800B60000201043F { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_b,  0b1000   , def_IS_HW;
-     rx_servo_timeout_sel_b,  0b1010  , def_IS_VBU;
-     rx_servo_timeout_sel_d,  0b1001   , def_IS_HW;
+     rx_servo_timeout_sel_b,  0b1010   , def_IS_HW;
+     rx_servo_timeout_sel_b,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_d,  0b1010   , def_IS_HW;
      rx_servo_timeout_sel_d,  0b1000  , def_IS_VBU;
 }
 
 #RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
 scom 0x800B68000201043F { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_h,  0b1110   , def_IS_HW;
+     rx_servo_timeout_sel_g,  0b0111   , def_IS_HW;
+     rx_servo_timeout_sel_g,  0b0100  , def_IS_VBU;
+     rx_servo_timeout_sel_h,  0b1011   , def_IS_HW;
      rx_servo_timeout_sel_h,  0b1000  , def_IS_VBU;
 }
 
@@ -279,7 +277,7 @@ scom 0x800B70000201043F {
 	bits, scom_data, expr;
      rx_servo_timeout_sel_i,  0b1011   , def_IS_HW;
      rx_servo_timeout_sel_i,  0b1000  , def_IS_VBU;
-     rx_servo_timeout_sel_j,  0b1100   , def_IS_HW;
+     rx_servo_timeout_sel_j,  0b1101   , def_IS_HW;
      rx_servo_timeout_sel_j,  0b1000  , def_IS_VBU;
      rx_servo_timeout_sel_k,  0b1101   , def_IS_HW;
      rx_servo_timeout_sel_k,  0b1000  , def_IS_VBU;
@@ -307,7 +305,7 @@ scom 0x800898000201043F {
      rx_ds_bl_timeout_sel,  0b001  , def_IS_VBU;
      rx_ds_timeout_sel,  0b110   , def_IS_HW;
      rx_ds_timeout_sel,  0b010  , def_IS_VBU;
-	rx_sls_timeout_sel, 0b001, any;
+	rx_sls_timeout_sel, 0b110, any;
      rx_wt_timeout_sel,  0b111   , def_IS_HW;
      rx_wt_timeout_sel,  0b011  , def_IS_VBU;
 }
@@ -328,7 +326,7 @@ scom 0x800958000201043F {
 #RX.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG
 scom 0x800A30000201043F { 
 	bits, scom_data, expr;
-     rx_wt_cu_pll_pgooddly,  0b001   , def_IS_HW;
+     rx_wt_cu_pll_pgooddly,  0b110   , def_IS_HW;
      rx_wt_cu_pll_pgooddly,  0b000  , def_IS_VBU;
      rx_wt_cu_pll_reset,  0b0   , def_IS_HW;
      rx_wt_cu_pll_reset,  0b1  , def_IS_VBU;
@@ -448,6 +446,12 @@ scom 0x800CC4000201043F {
 	tx_drv_clk_pattern_gcrmsg, 0b00, any;
 }
 
+#TX.TXCTL.TX_CTL_REGS.TX_DYN_RECAL_TIMEOUTS_PP
+scom 0x800EAC000201043F { 
+	bits, scom_data, expr;
+	tx_dyn_recal_interval_timeout_sel, 0b101, any;
+}
+
 #TX.TXCTL.TX_CTL_REGS.TX_ID1_PG
 scom 0x800C94000201043F { 
 	bits, scom_data, expr;
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml
index a4c172c6e..9d07533f3 100644
--- a/src/usr/hwpf/hwp/memory_attributes.xml
+++ b/src/usr/hwpf/hwp/memory_attributes.xml
@@ -21,7 +21,7 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <attributes>
-<!-- $Id: memory_attributes.xml,v 1.76 2013/07/17 13:47:15 bellows Exp $ -->
+<!-- $Id: memory_attributes.xml,v 1.82 2013/08/05 21:40:04 bellows Exp $ -->
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
 <!-- *********************************************************************** -->
@@ -455,7 +455,7 @@ firmware notes: none</description>
 <attribute>
     <id>ATTR_EFF_CKE_MAP</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none</description>
+    <description>Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none - NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
     <valueType>uint8</valueType>
     <writeable/>
     <odmVisable/>
@@ -466,7 +466,7 @@ firmware notes: none</description>
 <attribute>
     <id>ATTR_EFF_SPCKE_MAP</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Rank to Spare CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none</description>
+    <description>Rank to Spare CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
     <valueType>uint8</valueType>
     <writeable/>
     <odmVisable/>
@@ -3162,19 +3162,6 @@ Firmware shares some code with the processor, so the attribute is named so they
 </attribute>
 
 <attribute>
-    <id>ATTR_MEMB_NEST_FREQ</id>
-    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
-    <description>Frequency of the Centaur NEST PLL in MHz.
-consumer:  cen_mem_pll_initf
-firmware notes:  Platforms should initialize the attribute to the correct value for the system.</description>
-    <valueType>uint32</valueType>
-    <platInit/>
-    <writeable/>
-    <odmVisable/>
-    <odmChangeable/>
-</attribute>
-
-<attribute>
     <id>ATTR_CDIMM_SENSOR_MAP_PRIMARY</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Custom DIMM Sensor Map for Primary I2C Port (1 byte of data):
@@ -3347,7 +3334,7 @@ Comes from the VPD MW Keyword</description>
 <attribute>
     <id>ATTR_EFF_RLO</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Gives the RLO value to use for this port.  This comes from the MR Keyword of the VPD gives and indication of the value.  It will be writable until it comes from VPD. The value is a positive integer number.</description>
+    <description>This value comes from looking at the ATTR_VPD_RLO attribute associated with the DIMMs off the port.  Computed in eff_config. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
     <valueType>uint8</valueType>
     <platInit/>
     <writeable/>
@@ -3359,7 +3346,7 @@ Comes from the VPD MW Keyword</description>
 <attribute>
     <id>ATTR_EFF_CKE_PRI_MAP</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Contains the CKE MAP for the DIMM being plugged in.  It comes from the MT keyword but is not on a port basis --- meaning this Attribute may be split: with 16 bits associated with port A data and 16 bits with B. This value goes directly into the MBA01 Rank-to-primary-CKE mapping table register bits 0:31 (MBA01_MBAREF1Q) register. This attribute is writeable until it comes from the VPD</description>
+    <description>Contains the CKE MAP for the DIMM being plugged in.  The source of the data comes from the the ATTR_CKE_PRI_MAP attributes where 16 bits associated with port A data and 16 bits with B. This value goes directly into the MBA01 Rank-to-primary-CKE mapping table register bits 0:31 (MBA01_MBAREF1Q) register. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
     <valueType>uint32</valueType>
     <platInit/>
     <writeable/>
@@ -3370,7 +3357,7 @@ Comes from the VPD MW Keyword</description>
 <attribute>
     <id>ATTR_EFF_CKE_PWR_MAP</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Contains the CKE Power Domain mapping tables for the DIMM being plugged in.  It comes from the MT keyword but is not on a port basis --- meaning this Attribute may be split: with 32 bits associated with port A data and 32 bits with B. This value goes directly into the MBA01 Rank-to-CKE power domain mapping table bits 0:33 (MBA01_MBARPC1Q) register. This attribute is writeable until it comes from the VPD</description>
+    <description>Contains the CKE Power Domain mapping tables for the DIMM being plugged in.  The source of the data are the ATTR_VPD_CKE_PWR_MAP with 32 bits coming from the attribute  associated  with port A data and 32 bits with B. This value goes directly into the MBA01 Rank-to-CKE power domain mapping table bits 0:33 (MBA01_MBARPC1Q) register. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
     <valueType>uint64</valueType>
     <platInit/>
     <writeable/>
@@ -3381,7 +3368,7 @@ Comes from the VPD MW Keyword</description>
 <attribute>
     <id>ATTR_EFF_GPO</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Global Phy Offset value that is used in setting up the phy.  This value comes from the MR keyword of the VPD</description>
+    <description>Global Phy Offset value that is used in setting up the phy.  This value is dervived from the VPD_GPO attribute. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
     <valueType>uint8</valueType>
     <platInit/>
     <writeable/>
@@ -3393,7 +3380,7 @@ Comes from the VPD MW Keyword</description>
 <attribute>
     <id>ATTR_EFF_RDTAG</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Read Tag value that is used in setting up the phy.  It is expected that this value will come from the VPD</description>
+    <description>Read Tag value that is used in setting up the phy.  It is expected that this value will come from the VPD. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
     <valueType>uint8</valueType>
     <platInit/>
     <writeable/>
@@ -3404,7 +3391,7 @@ Comes from the VPD MW Keyword</description>
 <attribute>
     <id>ATTR_EFF_WLO</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Read Latency Offset value that is used in the phy.  This value  comes from the MR keyword of the VPD</description>
+    <description>This value comes from looking at the ATTR_VPD_WLO attribute associated with the DIMMs off the port.  Computed in eff_config. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
     <valueType>uint8</valueType>
     <platInit/>
     <writeable/>
@@ -3416,7 +3403,7 @@ Comes from the VPD MW Keyword</description>
 <attribute>
     <id>ATTR_EFF_TSYS_ADR</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>TSYS for all address blocks in the MBA pair. This value comes from the MR keyword of the VPD</description>
+    <description>TSYS for all address blocks in the MBA pair. This value comes from ATTR_VPD_TSYS_ADR of the assoicated DIMMs. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
     <valueType>uint8</valueType>
     <platInit/>
     <writeable/>
@@ -3427,7 +3414,7 @@ Comes from the VPD MW Keyword</description>
 <attribute>
     <id>ATTR_EFF_TSYS_DP18</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>TSYS for all DP18 blocks in the MBA pair.  This value comes from the MR keyword of the VPD</description>
+    <description>TSYS for all DP18 blocks in the MBA pair.  This value comes from ATTR_VPD_TSYS_DP18 from the associated DIMMs. NOTE THIS VALUE OF THIS ATTRIBUTE WILL COME FROM THE VPD SO THIS ATTRIBUTE WILL BECOME OBSOLETE AT SOME TIME</description>
     <valueType>uint8</valueType>
     <platInit/>
     <writeable/>
@@ -3464,7 +3451,9 @@ Comes from the VPD MW Keyword</description>
     <description>LRDIMM MR1,2 register.
 DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks.  Eff config should set this up.</description>
     <valueType>uint8</valueType>
+    <writeable/>
     <odmVisable/>
+    <odmChangeable/>
     <array> 2 2</array>
 </attribute>
 
@@ -3476,7 +3465,9 @@ F[3,4]RC10, F[3,4]RC11, F[5,6]RC10, F[5,6]RC11, F[7,8]RC10, F[7,8]RC11, F[9,10]R
 F[1]RC8, F[3]RC9, F[3]RC8, F[1]RC11, F[1]RC12, F[1]RC13, F[1]RC14, F[1]RC15.
 Eff config should set this up</description>
     <valueType>uint64</valueType>
+    <writeable/>
     <odmVisable/>
+    <odmChangeable/>
     <array> 2 2</array>
 </attribute>
 
@@ -3492,6 +3483,164 @@ Will be set at an MBA level with one policy to be used</description>
     <odmChangeable/>
 </attribute>
 
+<attribute>
+    <id>ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>runtime memory throttle values adjusted by the dimm power test
+DIMM power test memory throttles for cfg_nm_n_per_mba</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistent/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>runtime memory throttle values adjusted by the dimm power test
+DIMM power test memory throttles for cfg_nm_n_per_chip</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistent/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_DENOMINATOR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>runtime memory throttle values adjusted by the dimm power test
+DIMM power test memory throttles for cfg_nm_m</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistent/>
+</attribute>
+
+<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP
+<attribute>
+    <id>ATTR_MSS_DRAM_ACTIVATE_POWER_PERCENT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DRAM Activation power percentage to determine the ras and cas weights for throttle controls
+will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on the left(big endian))
+</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+-->
+
+<attribute>
+    <id>ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>RAS weight to use for memory throttle control</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>CAS weight to use for memory throttle control</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<!-- TODO: RTC 82331 - Add this attribute to the Accessor HWP
+<attribute>
+    <id>ATTR_VPD_MT_CKE_PRI_MAP</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD keyword MT bytes 54 and 55 MT(54:55) for the Logical DIMM associated with port A.  Bytes 118:119 for port B, 182:183 for port C and 246:247 for port D.  The AB and CD portions form a 32 bit word for each mba</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_MT_CKE_PWR_MAP</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD keyword MT bytes 56 to 59 MT(56:59) for the Logical DIMM associated with port A.  Bytes 120:123 for port B, 184:187 for port C and 248:251 for port D</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_MR_GPO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD keyword MR bytes 50 MR(50) for the Logical DIMM associated with port A.  Bytes 114 for port B, 178 for port C and 242 for port D</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_MR_RLO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD keyword MR byte 49 bits 4:7 for the Logical DIMM associated with port A.  Byte 113 bits 4:7 for port B, 177 bits 4:7 for port C and 241 bits 4:7 for port D</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_MR_WLO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD keyword MR byte 49 bits 0:3 for the Logical DIMM associated with port A.  Byte 113 bits 0:3 for port B, 177 bits 0:3 for port C and 241 bits 0:3 for port D</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_MR_TSYS_ADR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD MR keyword byte 51 for ports A and B and byte 179 for port C and D.    This means that all ADR blocks use this value on an mba level</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_VPD_MR_TSYS_DP18</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>This value comes from the VPD MR keyword byte 115 for ports A and B and byte 243 for port C and D.  This means all DP18 blocks use this value on a mba level</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+-->
+
+<attribute>
+    <id>ATTR_LAB_USE_JTAG_MODE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>This attribute controls how the procedures operate in JTAG mode under an environment called cronus flex.  For normal operation, this attribute should be set to FALSE. Platforms should initialize this attribute to FALSE.</description>
+    <valueType>uint8</valueType>
+    <enum>FALSE =0, TRUE = 1</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_CONTROL_SWITCH</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>This attribute enables control switches in the memory code.  This is a one hot vector:  Bit 7 controls the Bad Bit Mask function in draminit_training. The platform should initialize this to BBM_ON except if ATTR_LAB_USE_JTAG_MODE == TRUE, then the platform should set this attribute to BBM_ OFF.</description>
+    <valueType>uint8</valueType>
+    <enum>BBM_ON = 0x01, BBM_OFF = 0x00 </enum>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 9c6a7eb75..cc2ff0815 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -13022,4 +13022,139 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </hwpfToHbAttrMap>
 </attribute>
 
+<attribute>
+    <id>LAB_USE_JTAG_MODE</id>
+    <description>This attribute controls how the procedures operate in JTAG mode under an environment called cronus flex.  For normal operation, this attribute should be set to FALSE. Platforms should initialize this attribute to FALSE.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_LAB_USE_JTAG_MODE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_CONTROL_SWITCH</id>
+    <description>This attribute enables control switches in the memory code.  This is a one hot vector:  Bit 7 controls the Bad Bit Mask function in draminit_training. The platform should initialize this to BBM_ON except if ATTR_LAB_USE_JTAG_MODE == TRUE, then the platform should set this attribute to BBM_ OFF.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_CONTROL_SWITCH</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
+    <description>runtime memory throttle values adjusted by the dimm power test
+        DIMM power test memory throttles for cfg_nm_n_per_mba</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+    <description>runtime memory throttle values adjusted by the dimm power test
+        DIMM power test memory throttles for cfg_nm_n_per_chip</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_DIMM_POWER_TEST_MEM_THROTTLE_DENOMINATOR</id>
+    <description>runtime memory throttle values adjusted by the dimm power test
+        DIMM power test memory throttles for cfg_nm_m</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_DIMM_POWER_TEST_MEM_THROTTLE_DENOMINATOR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<!--
+<attribute>
+    <id>MSS_DRAM_ACTIVATE_POWER_PERCENT</id>
+    <description>DRAM Activation power percentage to determine the ras and cas weights for throttle controls
+        will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on the left(big endian))
+    </description>
+    <simpleType>
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_DRAM_ACTIVATE_POWER_PERCENT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+-->
+
+<attribute>
+    <id>MSS_THROTTLE_CONTROL_RAS_WEIGHT</id>
+    <description>RAS weight to use for memory throttle control</description>
+    <simpleType>
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_THROTTLE_CONTROL_CAS_WEIGHT</id>
+    <description>CAS weight to use for memory throttle control</description>
+    <simpleType>
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 6d8d78e9c..911de4dbb 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -187,6 +187,8 @@
     <attribute><id>CDM_POLICIES</id></attribute>
     <attribute><id>HOSTSVC_PLID</id></attribute>
     <attribute><id>RUN_MAX_MEM_PATTERNS</id></attribute>
+    <attribute><id>LAB_USE_JTAG_MODE</id></attribute>
+    <attribute><id>MSS_CONTROL_SWITCH</id></attribute>
 </targetType>
 
 <targetType>
@@ -1015,6 +1017,11 @@
     <attribute><id>LRDIMM_ADDITIONAL_CNTL_WORDS</id></attribute>
     <attribute><id>LRDIMM_RANK_MULT_MODE</id></attribute>
     <attribute><id>EFF_CRC_WR_LATENCY</id></attribute>
+    <attribute><id>MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_MBA</id></attribute>
+    <attribute><id>MSS_DIMM_POWER_TEST_MEM_THROTTLE_NUMERATOR_PER_CHIP</id></attribute>
+    <attribute><id>MSS_DIMM_POWER_TEST_MEM_THROTTLE_DENOMINATOR</id></attribute>
+    <attribute><id>MSS_THROTTLE_CONTROL_RAS_WEIGHT</id></attribute>
+    <attribute><id>MSS_THROTTLE_CONTROL_CAS_WEIGHT</id></attribute>
 </targetType>
 
 <targetType>