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| author | Stephen Glancy <sglancy@us.ibm.com> | 2019-04-24 15:26:23 -0400 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-04-30 11:54:00 -0500 |
| commit | 114d10d29c181671b0ec51c1bef37652a2df9b83 (patch) | |
| tree | c3af0f9b70638d0b6f0c6f85f8b0609bd4605438 | |
| parent | 4ce53f71e9fcf0c22fdb83af31b450db975df233 (diff) | |
| download | talos-hostboot-114d10d29c181671b0ec51c1bef37652a2df9b83.tar.gz talos-hostboot-114d10d29c181671b0ec51c1bef37652a2df9b83.zip | |
Fixes LRDIMM command to command timing
Change-Id: Ia423a01f01a96e7c79bfb704b3c66fd4a7ceeec9
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76467
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Mark Pizzutillo <mark.pizzutillo@ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76521
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
3 files changed, 16 insertions, 16 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C index 266e7ce56..f43e8ff19 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C @@ -69,8 +69,6 @@ namespace mss fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) { - constexpr uint64_t SAFE_DELAY = 2000; // Waiting a safe amount of time as the LRDIMM spec - // doesn't give us an explicit value for this delay FAPI_INF("bcw_load_ddr4 %s", mss::c_str(i_target) ); uint8_t l_sim = 0; @@ -104,21 +102,21 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target { FUNC_SPACE_0, DQ_DRIVER_CW, eff_dimm_ddr4_bc03, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, MDQ_RTT_CW, eff_dimm_ddr4_bc04, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, MDQ_DRIVER_CW, eff_dimm_ddr4_bc05, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, CMD_SPACE_CW, eff_dimm_ddr4_bc06, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, RANK_PRESENCE_CW, eff_dimm_ddr4_bc07, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, CMD_SPACE_CW, eff_dimm_ddr4_bc06, BCW_SAFE_DELAY , CW4_DATA_LEN, cw_info::BCW}, // using tmrd_l2 causes an error - safe delay works + { FUNC_SPACE_0, RANK_PRESENCE_CW, eff_dimm_ddr4_bc07, BCW_SAFE_DELAY , CW4_DATA_LEN, cw_info::BCW}, // using tmrd_l2 causes an error - safe delay works { FUNC_SPACE_0, RANK_SELECTION_CW, eff_dimm_ddr4_bc08, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, POWER_SAVING_CW, eff_dimm_ddr4_bc09, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, OPERATING_SPEED, eff_dimm_ddr4_bc0a, l_tDLLK , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, VOLT_AND_SLEW_RATE_CW, eff_dimm_ddr4_bc0b, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, eff_dimm_ddr4_bc0c, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, eff_dimm_ddr4_bc0c, mss::tmrd_l2() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, LDQ_OPERATION_CW, eff_dimm_ddr4_bc0d, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, PARITY_CW, eff_dimm_ddr4_bc0e, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, ERROR_STATUS_CW, eff_dimm_ddr4_bc0f, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, // 8-bit BCW's now // Function space 0 - we're already there, so that's nice - { FUNC_SPACE_0, BUFF_CONFIG_CW, eff_dimm_ddr4_f0bc1x, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, LRDIMM_OPERATING_SPEED, eff_dimm_ddr4_f0bc6x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, BUFF_CONFIG_CW, eff_dimm_ddr4_f0bc1x, mss::tmrd_l2() , CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, LRDIMM_OPERATING_SPEED, eff_dimm_ddr4_f0bc6x, BCW_SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, // Function space 2 { FUNC_SPACE_2, FUNC_SPACE_SELECT_CW, FUNC_SPACE_2, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, @@ -126,8 +124,8 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target // Function space 5 { FUNC_SPACE_5, FUNC_SPACE_SELECT_CW, FUNC_SPACE_5, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_5, HOST_VREF_CW, eff_dimm_ddr4_f5bc5x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_5, DRAM_VREF_CW, eff_dimm_ddr4_f5bc6x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_5, HOST_VREF_CW, eff_dimm_ddr4_f5bc5x, BCW_SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_5, DRAM_VREF_CW, eff_dimm_ddr4_f5bc6x, BCW_SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, // Function space 6 { FUNC_SPACE_6, FUNC_SPACE_SELECT_CW, FUNC_SPACE_6, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H index d2bffc509..0cd1fad32 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H @@ -96,6 +96,9 @@ enum db02_def : size_t HOST_VREF_CW = 0x5, // Func space 5 DRAM_VREF_CW = 0x6, // Func space 5 BUFF_TRAIN_CONFIG_CW = 0x4, // Func space 6 + + // Safe delays for BCW's + BCW_SAFE_DELAY = 2000, }; namespace ddr4 @@ -302,7 +305,7 @@ inline fapi2::ReturnCode set_buffer_training( const fapi2::Target<fapi2::TARGET_ uint64_t l_encoding = 0; fapi2::Assert(find_value_from_key(BUFF_TRAINING, i_mode, l_encoding)); - cw_data l_data(FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, l_encoding, mss::tmrc()); + cw_data l_data(FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, l_encoding, mss::tmrd_l2()); FAPI_TRY( settings_boilerplate<BCW_4BIT>(i_target, l_data, io_inst) ); fapi_try_exit: @@ -453,9 +456,8 @@ inline fapi2::ReturnCode set_command_space( const fapi2::Target<fapi2::TARGET_TY } // From the DDR4DB02 Spec: BC06 - Command Space Control Word - // After issuing a data buffer command via writes to BC06 waiting for tMRC(16 tCK) - // is required before the next DRAM command or BCW write can be issued. - cw_data l_data(FUNC_SPACE_0, CMD_SPACE_CW, i_command, mss::tmrc()); + // Waiting safe delay here as we've seen issues in the lab where the required tMRD_l2 isn't sufficient + cw_data l_data(FUNC_SPACE_0, CMD_SPACE_CW, i_command, BCW_SAFE_DELAY); FAPI_TRY( settings_boilerplate<BCW_4BIT>(i_target, l_data, io_inst) ); fapi_try_exit: @@ -495,7 +497,7 @@ inline fapi2::ReturnCode set_pba_mode( const fapi2::Target<fapi2::TARGET_TYPE_DI FAPI_TRY(mss::eff_dimm_ddr4_f0bc1x(i_target, l_nominal_bc_value)); { - cw_data l_data(FUNC_SPACE_0, BUFF_CONFIG_CW, l_nominal_bc_value, mss::tmrc()); + cw_data l_data(FUNC_SPACE_0, BUFF_CONFIG_CW, l_nominal_bc_value, mss::tmrd_l2()); l_data.iv_data.writeBit<PBA_POSITION>(i_state); FAPI_INF("%s data 0x%02x", mss::c_str(i_target), l_data.iv_data); FAPI_TRY( settings_boilerplate<BCW_8BIT>(i_target, l_data, io_inst) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C index 036f87871..31c0cd6e3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C @@ -445,8 +445,8 @@ fapi2::ReturnCode mrep::set_delay(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& std::vector<cw_info> l_bcws = { - {i_rank, NIBBLE0_BCW_NUMBER, i_delay, mss::tmrc(), mss::CW8_DATA_LEN, cw_info::BCW}, - {i_rank, NIBBLE1_BCW_NUMBER, i_delay, mss::tmrc(), mss::CW8_DATA_LEN, cw_info::BCW}, + {i_rank, NIBBLE0_BCW_NUMBER, i_delay, mss::tmrd_l2(), mss::CW8_DATA_LEN, cw_info::BCW}, + {i_rank, NIBBLE1_BCW_NUMBER, i_delay, mss::tmrd_l2(), mss::CW8_DATA_LEN, cw_info::BCW}, }; uint8_t l_sim = 0; |
