diff options
author | Thi Tran <thi@us.ibm.com> | 2014-06-18 09:30:14 -0500 |
---|---|---|
committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-06-23 15:15:47 -0500 |
commit | 0ea3be7d289e8e19aae6a426b65ec91a925ea11a (patch) | |
tree | 7b48822a1f19d5865af83729660ecd4af65ccccf | |
parent | 12b9ad95d9d199e7295cb94ee2855bb53a27ebbf (diff) | |
download | talos-hostboot-0ea3be7d289e8e19aae6a426b65ec91a925ea11a.tar.gz talos-hostboot-0ea3be7d289e8e19aae6a426b65ec91a925ea11a.zip |
FW624379: P8:Brazos: MCS Speculation Filter Enabled
Change-Id: Ie1ee3bf3fa0e325af3134a1b56929a8f94eb894f
CQ:FW624379
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/#/c/11652/
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11653
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
-rwxr-xr-x | src/usr/hwpf/hwp/include/p8_scom_addresses.H | 6 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/initfiles/mbs_def.initfile | 34 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile | 10 |
3 files changed, 39 insertions, 11 deletions
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H index 658f6cfd6..00cf5c838 100755 --- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H @@ -20,7 +20,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_scom_addresses.H,v 1.182 2014/04/24 23:14:55 cmolsen Exp $ +// $Id: p8_scom_addresses.H,v 1.183 2014/06/08 19:49:24 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -1211,6 +1211,7 @@ CONST_UINT64_T( X_GP0_0x04000000 , ULL(0x04000000) ); CONST_UINT64_T( X_GP1_0x04000001 , ULL(0x04000001) ); CONST_UINT64_T( X_GP2_0x04000002 , ULL(0x04000002) ); +CONST_UINT64_T( X_CLK_ADJ_DAT_REG_0x040F0015 , ULL(0x040F0015) ); CONST_UINT64_T( X_CLK_ADJ_SET_0x040F0016 , ULL(0x040F0016) ); //------------------------------------------------------------------------------ @@ -2120,6 +2121,9 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: p8_scom_addresses.H,v $ +Revision 1.183 2014/06/08 19:49:24 jmcgill +add XBUS skew adjust data register definition + Revision 1.182 2014/04/24 23:14:55 cmolsen Added four PIRR reg defs. diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile index f5dd0ac88..d58633cb5 100644 --- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile @@ -1,8 +1,9 @@ -#-- $Id: mbs_def.initfile,v 1.47 2014/03/19 19:38:44 yctschan Exp $ +#-- $Id: mbs_def.initfile,v 1.48 2014/05/20 20:37:38 baysah Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.48 |baysah |04/21/14| Added L4 Cleaner settings per rank group to improve memory performance #-- 1.47 |tschang | 3/19/14| SW252733 - L4 Cache UE Handling #-- 1.46 |tschang | 3/19/14| SW252733 - L4 Cache UE Handling typo #-- 1.45 |tschang | 2/24/14| fixed MBA1 only cfg @@ -405,6 +406,16 @@ define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mb ## Temp defines until the code adds these attributes + + +# Define the number of ranks per MBS (2 MBAs) for L4 Cleaner setup +#define def_mba01_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1]); +#define def_mba23_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); +define def_num_mbs_ranks = (MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] + MBA1.ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + MBA1.ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); + + + + #--****************************************************************************** #-- MBS FIR MASK Register #--****************************************************************************** @@ -562,12 +573,21 @@ scom 0x0201140F { 11 , 0b1 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 0); # MBCCFGQ_srw_prefetch_dis 12 , 0b0 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 1); # MBCCFGQ_prq_prefetch_dis 12 , 0b1 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 0); # MBCCFGQ_prq_prefetch_dis - 13:16 , 0xE , any ; # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 - 17:22 , 0x1F , any ; # MBCCFGQ_cln_wrq_tgt_alloc_0_5 - 23:28 , 0x7 , any ; # MBCCFGQ_cln_wr_priority_wrq_hwmark_0_5 - 29:34 , 0x6 , any ; # MBCCFGQ_cln_wr_priority_wrq_lwmark_0_5 - 35:48 , 0x1000 , any ; # MBCCFGQ_cln_wr_priority_dv_hwmark_0_13 - 49:62 , 0x0FC0 , any ; # MBCCFGQ_cln_wr_priority_dv_lwmark_0_13 + #13:16 , 0xE , any ; # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 + #17:22 , 0x1F , any ; # MBCCFGQ_cln_wrq_tgt_alloc_0_5 + #23:28 , 0x7 , any ; # MBCCFGQ_cln_wr_priority_wrq_hwmark_0_5 + #29:34 , 0x6 , any ; # MBCCFGQ_cln_wr_priority_wrq_lwmark_0_5 + #35:48 , 0x1000 , any ; # MBCCFGQ_cln_wr_priority_dv_hwmark_0_13 + #49:62 , 0x0FC0 , any ; # MBCCFGQ_cln_wr_priority_dv_lwmark_0_13 + 13:16 , 0b1111 , ( (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((def_num_mbs_ranks == 2 ) || (def_num_mbs_ranks == 4)) ); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 15 for 2 and 4 rnkgrp + 13:16 , 0b0111 , ( (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 8 ) ); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 7 for 8 rnkgrp + 17:22 , 0b100000 , ( (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 2 ) ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp + 17:22 , 0b010000 , ( (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 4 ) ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 16 for 4 rnkgrp + 17:22 , 0b001000 , ( (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 8 ) ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 8 for 8 rnkgrp + 23:28 , 0b000111 , any ; # MBCCFGQ_cln_wr_priority_wrq_hwmark_0_5 is 7 for all rank groups + 29:34 , 0b000110 , any ; # MBCCFGQ_cln_wr_priority_wrq_lwmark_0_5 is 6 for all rank groups + 35:48 , 0b00001000000000 , any ; # MBCCFGQ_cln_wr_priority_dv_hwmark_0_13 is 512 for all rank groups + 49:62 , 0b00000111110000 , any ; # MBCCFGQ_cln_wr_priority_dv_lwmark_0_13 is 512-16 for all rank groups } diff --git a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile index 97a97e4ce..35565b0c1 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile @@ -1,9 +1,11 @@ -#-- $Id: p8.mcs.scom.initfile,v 1.12 2014/01/08 18:22:31 baysah Exp $ +#-- $Id: p8.mcs.scom.initfile,v 1.13 2014/05/21 19:17:17 baysah Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- #-- | | | +#-- 1.13|baysah |05/20/14|- Added Best MCS Spec filter setting to MODE2 reg (2011809 16 20 9007F) for power and perf improvement +#-- | | | #-- 1.12|baysah |01/08/14|- Moved ECC bypass qualifier from MCMODE1(63) TO MCMODE1(62), bit 63 is perfmon. #-- | | | #-- 1.10|jmcgill |05/07/13|- Qualify ECC bypass disable by risk level @@ -114,10 +116,12 @@ define ecc_bypass_disable = ((TGT1.ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE ! 1:13 , 0b0000000000000 ; # MCMODE2Q_DISABLE_WRITE_MDI_TO_ZERO 14 , 0b0 ; # MCMODE2Q_DISABLE_SFU_OPERATIONS 15 , 0b0 ; # MCMODE2Q_DISABLE_FASTPATH_QOS - 16 , 0b0 ; # MCMODE2Q_ENABLE_2K_SPEC_READ_DISABLE_COUNTERS + # 16 , 0b0 ; # MCMODE2Q_ENABLE_2K_SPEC_READ_DISABLE_COUNTERS + 16 , 0b1 ; # MCMODE2Q_ENABLE_2K_SPEC_READ_DISABLE_COUNTERS 17 , 0b0 ; # MCMODE2Q_ENABLE_ZERO_SPEC_HASH_ADDR_48_TO_50 18 , 0b0 ; # MCMODE2Q_DISABLE_SPEC_DISABLE_HINT_BIT - 19 , 0b0 ; # MCMODE2Q_ENABLE_RESET_2K_COUNT_IF_HINT_BIT_SET + # 19 , 0b0 ; # MCMODE2Q_ENABLE_RESET_2K_COUNT_IF_HINT_BIT_SET + 19 , 0b1 ; # MCMODE2Q_ENABLE_RESET_2K_COUNT_IF_HINT_BIT_SET 20:23, 0x0 ; # MCMODE2Q_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT 24:27, 0x0 ; # MCMODE2Q_D2K_SPEC_FILTER_COUNTER_LFSR_DEC__SELECT 28 , 0b0 ; # MCMODE2Q_SPEC_READ_FILTER_NO_HASH_MODE |