PRD: removed NPUFIR workaround for DD1.0 to enable default capture

Change-Id: Iba8ab16900f75545757901c8c6ad781791b8d75c
CQ: SW418409
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54615
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54782
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>

3 files changed, 26 insertions, 665 deletions

diff --git a/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule b/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule
index 9a9845cdb..691e7026e 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule
@@ -754,78 +754,6 @@ chip p9_nimbus
     };
 
     ############################################################################
-    # P9 chip NPU0FIR for Nimbus DD1.0 only
-    ############################################################################
-
-    register NPU0FIR_NDD10
-    {
-        name        "P9 chip NPU0FIR for Nimbus DD1.0";
-        scomaddr    0x05011400;
-        reset       (&, 0x05011401);
-        mask        (|, 0x05011405);
-        capture     group cNPU0FIR_NDD10;
-    };
-
-    register NPU0FIR_MASK_NDD10
-    {
-        name        "P9 chip NPU0FIR MASK for Nimbus DD1.0";
-        scomaddr    0x05011403;
-        capture     group cNPU0FIR_NDD10;
-    };
-
-    register NPU0FIR_ACT0_NDD10
-    {
-        name        "P9 chip NPU0FIR ACT0 for Nimbus DD1.0";
-        scomaddr    0x05011406;
-        capture     group cNPU0FIR_NDD10;
-        capture     req nonzero("NPU0FIR_NDD10");
-    };
-
-    register NPU0FIR_ACT1_NDD10
-    {
-        name        "P9 chip NPU0FIR ACT1 for Nimbus DD1.0";
-        scomaddr    0x05011407;
-        capture     group cNPU0FIR_NDD10;
-        capture     req nonzero("NPU0FIR_NDD10");
-    };
-
-    ############################################################################
-    # P9 chip NPU1FIR for Nimbus DD1.0 only
-    ############################################################################
-
-    register NPU1FIR_NDD10
-    {
-        name        "P9 chip NPU1FIR for Nimbus DD1.0";
-        scomaddr    0x05011440;
-        reset       (&, 0x05011441);
-        mask        (|, 0x05011445);
-        capture     group cNPU1FIR_NDD10;
-    };
-
-    register NPU1FIR_MASK_NDD10
-    {
-        name        "P9 chip NPU1FIR MASK for Nimbus DD1.0";
-        scomaddr    0x05011443;
-        capture     group cNPU1FIR_NDD10;
-    };
-
-    register NPU1FIR_ACT0_NDD10
-    {
-        name        "P9 chip NPU1FIR ACT0 for Nimbus DD1.0";
-        scomaddr    0x05011446;
-        capture     group cNPU1FIR_NDD10;
-        capture     req nonzero("NPU1FIR_NDD10");
-    };
-
-    register NPU1FIR_ACT1_NDD10
-    {
-        name        "P9 chip NPU1FIR ACT1 for Nimbus DD1.0";
-        scomaddr    0x05011447;
-        capture     group cNPU1FIR_NDD10;
-        capture     req nonzero("NPU1FIR_NDD10");
-    };
-
-    ############################################################################
     # P9 chip PBWESTFIR
     ############################################################################
 
@@ -1078,13 +1006,6 @@ chip p9_nimbus
     };
 
     ############################################################################
-    # P9 chip EHHCAFIR
-    ############################################################################
-
-    # Only existed on DD1.0 and was completely masked. So this FIR has been
-    # completely removed for all DD levels.
-
-    ############################################################################
     # P9 chip PBAMFIR
     ############################################################################
 
@@ -1310,21 +1231,21 @@ chip p9_nimbus
         scomaddr    0x05013C00;
         reset       (&, 0x05013C01);
         mask        (|, 0x05013C05);
-        capture     group cNPU0FIR;
+        capture     group default;
     };
 
     register NPU0FIR_MASK
     {
         name        "P9 chip NPU0FIR MASK";
         scomaddr    0x05013C03;
-        capture     group cNPU0FIR;
+        capture     group default;
     };
 
     register NPU0FIR_ACT0
     {
         name        "P9 chip NPU0FIR ACT0";
         scomaddr    0x05013C06;
-        capture     group cNPU0FIR;
+        capture     group default;
         capture     req nonzero("NPU0FIR");
     };
 
@@ -1332,7 +1253,7 @@ chip p9_nimbus
     {
         name        "P9 chip NPU0FIR ACT1";
         scomaddr    0x05013C07;
-        capture     group cNPU0FIR;
+        capture     group default;
         capture     req nonzero("NPU0FIR");
     };
 
@@ -1346,21 +1267,21 @@ chip p9_nimbus
         scomaddr    0x05013C40;
         reset       (&, 0x05013C41);
         mask        (|, 0x05013C45);
-        capture     group cNPU1FIR;
+        capture     group default;
     };
 
     register NPU1FIR_MASK
     {
         name        "P9 chip NPU1FIR MASK";
         scomaddr    0x05013C43;
-        capture     group cNPU1FIR;
+        capture     group default;
     };
 
     register NPU1FIR_ACT0
     {
         name        "P9 chip NPU1FIR ACT0";
         scomaddr    0x05013C46;
-        capture     group cNPU1FIR;
+        capture     group default;
         capture     req nonzero("NPU1FIR");
     };
 
@@ -1368,7 +1289,7 @@ chip p9_nimbus
     {
         name        "P9 chip NPU1FIR ACT1";
         scomaddr    0x05013C47;
-        capture     group cNPU1FIR;
+        capture     group default;
         capture     req nonzero("NPU1FIR");
     };
 
@@ -1382,21 +1303,21 @@ chip p9_nimbus
         scomaddr    0x05013C80;
         reset       (&, 0x05013C81);
         mask        (|, 0x05013C85);
-        capture     group cNPU2FIR;
+        capture     group default;
     };
 
     register NPU2FIR_MASK
     {
         name        "P9 chip NPU2FIR MASK";
         scomaddr    0x05013C83;
-        capture     group cNPU2FIR;
+        capture     group default;
     };
 
     register NPU2FIR_ACT0
     {
         name        "P9 chip NPU2FIR ACT0";
         scomaddr    0x05013C86;
-        capture     group cNPU2FIR;
+        capture     group default;
         capture     req nonzero("NPU2FIR");
     };
 
@@ -1404,7 +1325,7 @@ chip p9_nimbus
     {
         name        "P9 chip NPU2FIR ACT1";
         scomaddr    0x05013C87;
-        capture     group cNPU2FIR;
+        capture     group default;
         capture     req nonzero("NPU2FIR");
     };
 
@@ -4194,20 +4115,15 @@ group gN3_CHIPLET_FIR filter singlebit
      */
     (rN3_CHIPLET_FIR, bit(8)) ? analyze(gPBEASTFIR);
 
-    /** N3_CHIPLET_FIR[9]
-     *  Attention from ENHCAFIR
-     */
-    (rN3_CHIPLET_FIR, bit(9)) ? analyze(gENHCAFIR); # DD1.0 only
-
     /** N3_CHIPLET_FIR[10]
      *  Attention from NPU0FIR
      */
-    (rN3_CHIPLET_FIR, bit(10)) ? analyzeNPU0FIR;
+    (rN3_CHIPLET_FIR, bit(10)) ? analyze(gNPU0FIR);
 
     /** N3_CHIPLET_FIR[11]
      *  Attention from NPU1FIR
      */
-    (rN3_CHIPLET_FIR, bit(11)) ? analyzeNPU1FIR;
+    (rN3_CHIPLET_FIR, bit(11)) ? analyze(gNPU1FIR);
 
     /** N3_CHIPLET_FIR[12]
      *  Attention from NMMUCQFIR
@@ -4257,12 +4173,12 @@ group gN3_CHIPLET_FIR filter singlebit
     /** N3_CHIPLET_FIR[22]
      *  Attention from ENHCAFIR
      */
-    (rN3_CHIPLET_FIR, bit(22)) ? analyze(gENHCAFIR); # DD2.0+
+    (rN3_CHIPLET_FIR, bit(22)) ? analyze(gENHCAFIR);
 
     /** N3_CHIPLET_FIR[23]
      *  Attention from NPU2FIR
      */
-    (rN3_CHIPLET_FIR, bit(23)) ? analyzeNPU2FIR;
+    (rN3_CHIPLET_FIR, bit(23)) ? analyze(gNPU2FIR);
 
 };
 
@@ -4291,17 +4207,17 @@ group gN3_CHIPLET_UCS_FIR filter singlebit
     /** N3_CHIPLET_UCS_FIR[6]
      *  Attention from NPU2FIR
      */
-    (rN3_CHIPLET_UCS_FIR, bit(6)) ? analyzeNPU2FIR;
+    (rN3_CHIPLET_UCS_FIR, bit(6)) ? analyze(gNPU2FIR);
 
     /** N3_CHIPLET_UCS_FIR[7]
      *  Attention from NPU0FIR
      */
-    (rN3_CHIPLET_UCS_FIR, bit(7)) ? analyzeNPU0FIR;
+    (rN3_CHIPLET_UCS_FIR, bit(7)) ? analyze(gNPU0FIR);
 
     /** N3_CHIPLET_UCS_FIR[8]
      *  Attention from NPU1FIR
      */
-    (rN3_CHIPLET_UCS_FIR, bit(8)) ? analyzeNPU1FIR;
+    (rN3_CHIPLET_UCS_FIR, bit(8)) ? analyze(gNPU1FIR);
 
     /** N3_CHIPLET_UCS_FIR[9]
      *  Attention from NMMUCQFIR
@@ -4481,492 +4397,6 @@ group gN3_LFIR filter singlebit, cs_root_cause
 };
 
 ################################################################################
-# P9 chip NPU0FIR
-################################################################################
-
-rule rNPU0FIR_NDD10
-{
-  CHECK_STOP:
-    NPU0FIR_NDD10 & ~NPU0FIR_MASK_NDD10 & ~NPU0FIR_ACT0_NDD10 & ~NPU0FIR_ACT1_NDD10;
-  RECOVERABLE:
-    NPU0FIR_NDD10 & ~NPU0FIR_MASK_NDD10 & ~NPU0FIR_ACT0_NDD10 &  NPU0FIR_ACT1_NDD10;
-  UNIT_CS:
-    NPU0FIR_NDD10 & ~NPU0FIR_MASK_NDD10 &  NPU0FIR_ACT0_NDD10 &  NPU0FIR_ACT1_NDD10;
-};
-
-group gNPU0FIR_NDD10 filter singlebit, cs_root_cause
-{
-    /** NPU0FIR[0]
-     *  NTL array CE
-     */
-    (rNPU0FIR_NDD10, bit(0)) ? self_th_32perDay;
-
-    /** NPU0FIR[1]
-     *  NTL header array UE
-     */
-    (rNPU0FIR_NDD10, bit(1)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[2]
-     *  NTL Data Array UE
-     */
-    (rNPU0FIR_NDD10, bit(2)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[3]
-     *  NTL NVLInk Control/Header/AE PE
-     */
-    (rNPU0FIR_NDD10, bit(3)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[4]
-     *  NTL NVLink Data Parity error
-     */
-    (rNPU0FIR_NDD10, bit(4)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[5]
-     *  NTL NVLink Malformed Packet
-     */
-    (rNPU0FIR_NDD10, bit(5)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[6]
-     *  NTL NVLink Unsupported Packet
-     */
-    (rNPU0FIR_NDD10, bit(6)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[7]
-     *  NTL NVLink Config errors
-     */
-    (rNPU0FIR_NDD10, bit(7)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[8]
-     *  NTL NVLink CRC errors or LMD=Stomp
-     */
-    (rNPU0FIR_NDD10, bit(8)) ? defaultMaskedError;
-
-    /** NPU0FIR[9]
-     *  NTL PRI errors
-     */
-    (rNPU0FIR_NDD10, bit(9)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[10]
-     *  NTL logic error
-     */
-    (rNPU0FIR_NDD10, bit(10)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[11]
-     *  NTL LMD=Data Posion
-     */
-    (rNPU0FIR_NDD10, bit(11)) ? defaultMaskedError;
-
-    /** NPU0FIR[12]
-     *  NTL data array SUE
-     */
-    (rNPU0FIR_NDD10, bit(12)) ? defaultMaskedError;
-
-    /** NPU0FIR[13]
-     *  CQ CTL/SM ASBE Array single-bit CE
-     */
-    (rNPU0FIR_NDD10, bit(13)) ? self_th_32perDay;
-
-    /** NPU0FIR[14]
-     *  CQ CTL/SM PBR PowerBus Recoverable err
-     */
-    (rNPU0FIR_NDD10, bit(14)) ? defaultMaskedError;
-
-    /** NPU0FIR[15]
-     *  CQ CTL/SM REG Register ring error
-     */
-    (rNPU0FIR_NDD10, bit(15)) ? self_th_32perDay;
-
-    /** NPU0FIR[16]
-     *  Data UE for MMIO store data
-     */
-    (rNPU0FIR_NDD10, bit(16)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[17]
-     *  spare
-     */
-    (rNPU0FIR_NDD10, bit(17)) ? defaultMaskedError;
-
-    /** NPU0FIR[18]
-     *  CQ CTL/SM NCF NVLink config error
-     */
-    (rNPU0FIR_NDD10, bit(18)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[19]
-     *  CQ CTL/SM NVF NVLink fatal error
-     */
-    (rNPU0FIR_NDD10, bit(19)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[20]
-     *  spare
-     */
-    (rNPU0FIR_NDD10, bit(20)) ? defaultMaskedError;
-
-    /** NPU0FIR[21]
-     *  CQ CTL/SM AUE Array UE
-     */
-    (rNPU0FIR_NDD10, bit(21)) ? self_th_1;
-
-    /** NPU0FIR[22]
-     *  CQ CTL/SM PBP PowerBus parity error
-     */
-    (rNPU0FIR_NDD10, bit(22)) ? self_th_1;
-
-    /** NPU0FIR[23]
-     *  CQ CTL/SM PBF PowerBus Fatal Error
-     */
-    (rNPU0FIR_NDD10, bit(23)) ? level2_M_self_L_th_1;
-
-    /** NPU0FIR[24]
-     *  PowerBus configuration error
-     */
-    (rNPU0FIR_NDD10, bit(24)) ? level2_M_self_L_th_1;
-
-    /** NPU0FIR[25]
-     *  CQ CTL/SM FWD Forward-Progress error
-     */
-    (rNPU0FIR_NDD10, bit(25)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[26]
-     *  CQ CTL/SM NLG NPU Logic error
-     */
-    (rNPU0FIR_NDD10, bit(26)) ? self_th_1;
-
-    /** NPU0FIR[27]
-     *  CQ CTL/SM  UT=1 to frozen PE error
-     */
-    (rNPU0FIR_NDD10, bit(27)) ? defaultMaskedError;
-
-    /** NPU0FIR[28]
-     *  spare
-     */
-    (rNPU0FIR_NDD10, bit(28)) ? defaultMaskedError;
-
-    /** NPU0FIR[29]
-     *  CQ DAT ECC UE/SUE on data/BE arrays
-     */
-    (rNPU0FIR_NDD10, bit(29)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[30]
-     *  CQ DAT ECC CE on data/BE arrays
-     */
-    (rNPU0FIR_NDD10, bit(30)) ? self_M_level2_L_th_32perDay;
-
-    /** NPU0FIR[31]
-     *  CQ DAT parity error on data/BE latches
-     */
-    (rNPU0FIR_NDD10, bit(31)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[32]
-     *  CQ DAT parity errs on config regs
-     */
-    (rNPU0FIR_NDD10, bit(32)) ? self_th_1;
-
-    /** NPU0FIR[33]
-     *  CQ DAT parity errs/PowerBus rtag
-     */
-    (rNPU0FIR_NDD10, bit(33)) ? self_th_1;
-
-    /** NPU0FIR[34]
-     *  CQ DAT parity errs nternal state latches
-     */
-    (rNPU0FIR_NDD10, bit(34)) ? self_th_1;
-
-    /** NPU0FIR[35]
-     *  CQ DAT logic error
-     */
-    (rNPU0FIR_NDD10, bit(35)) ? self_th_1;
-
-    /** NPU0FIR[36]
-     *  Future SUE
-     */
-    (rNPU0FIR_NDD10, bit(36)) ? defaultMaskedError;
-
-    /** NPU0FIR[37]
-     *  ECC SUE on PB received data
-     */
-    (rNPU0FIR_NDD10, bit(37)) ? defaultMaskedError;
-
-    /** NPU0FIR[38:39]
-     *  spare
-     */
-    (rNPU0FIR_NDD10, bit(38|39)) ? defaultMaskedError;
-
-    /** NPU0FIR[40]
-     *  XTS internal logic error
-     */
-    (rNPU0FIR_NDD10, bit(40)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[41]
-     *  XTS correctable errs in XTS SRAM
-     */
-    (rNPU0FIR_NDD10, bit(41)) ? self_M_level2_L_th_32perDay;
-
-    /** NPU0FIR[42]
-     *  XTS Ues in XTS internal SRAM
-     */
-    (rNPU0FIR_NDD10, bit(42)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[43]
-     *  XTS CE on incoming stack transactions
-     */
-    (rNPU0FIR_NDD10, bit(43)) ? self_M_level2_L_th_32perDay;
-
-    /** NPU0FIR[44]
-     *  XTS  errs incoming stack transaction
-     */
-    (rNPU0FIR_NDD10, bit(44)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[45]
-     *  XTS errs on incoming PBUS transaction
-     */
-    (rNPU0FIR_NDD10, bit(45)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[46]
-     *  XTS Translate Request Fail
-     */
-    (rNPU0FIR_NDD10, bit(46)) ? self_th_1; # NIMBUS_10
-
-    /** NPU0FIR[47:59]
-     *  spare
-     */
-    (rNPU0FIR_NDD10, bit(47|48|49|50|51|52|53|54|55|56|57|58|59)) ? defaultMaskedError;
-
-    /** NPU0FIR[60]
-     *  MISC Pervasive SCOM satellite err
-     */
-    (rNPU0FIR_NDD10, bit(60)) ? defaultMaskedError;
-
-    /** NPU0FIR[61]
-     *  MISC Pervasive SCOM satellite err
-     */
-    (rNPU0FIR_NDD10, bit(61)) ? defaultMaskedError;
-
-    /** NPU0FIR[62]
-     *  Local FIR Parity Error RAS duplicate
-     */
-    (rNPU0FIR_NDD10, bit(62)) ? defaultMaskedError;
-
-    /** NPU0FIR[63]
-     *  Local FIR Parity Err
-     */
-    (rNPU0FIR_NDD10, bit(63)) ? defaultMaskedError;
-
-};
-
-################################################################################
-# P9 chip NPU1FIR
-################################################################################
-
-rule rNPU1FIR_NDD10
-{
-  CHECK_STOP:
-    NPU1FIR_NDD10 & ~NPU1FIR_MASK_NDD10 & ~NPU1FIR_ACT0_NDD10 & ~NPU1FIR_ACT1_NDD10;
-  RECOVERABLE:
-    NPU1FIR_NDD10 & ~NPU1FIR_MASK_NDD10 & ~NPU1FIR_ACT0_NDD10 &  NPU1FIR_ACT1_NDD10;
-  UNIT_CS:
-    NPU1FIR_NDD10 & ~NPU1FIR_MASK_NDD10 &  NPU1FIR_ACT0_NDD10 &  NPU1FIR_ACT1_NDD10;
-};
-
-group gNPU1FIR_NDD10 filter singlebit, cs_root_cause
-{
-    /** NPU1FIR[0]
-     *  NDL Brick0 stall
-     */
-    (rNPU1FIR_NDD10, bit(0)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[1]
-     *  NDL Brick0 nostall
-     */
-    (rNPU1FIR_NDD10, bit(1)) ? defaultMaskedError;
-
-    /** NPU1FIR[2]
-     *  NDL Brick1 stall
-     */
-    (rNPU1FIR_NDD10, bit(2)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[3]
-     *  NDL Brick1 nostall
-     */
-    (rNPU1FIR_NDD10, bit(3)) ? defaultMaskedError;
-
-    /** NPU1FIR[4]
-     *  NDL Brick2 stall
-     */
-    (rNPU1FIR_NDD10, bit(4)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[5]
-     *  NDL Brick2 nostall
-     */
-    (rNPU1FIR_NDD10, bit(5)) ? defaultMaskedError;
-
-    /** NPU1FIR[6]
-     *  NDL Brick3 stall
-     */
-    (rNPU1FIR_NDD10, bit(6)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[7]
-     *  NDL Brick3 nostall
-     */
-    (rNPU1FIR_NDD10, bit(7)) ? defaultMaskedError;
-
-    /** NPU1FIR[8]
-     *  NDL Brick4 stall
-     */
-    (rNPU1FIR_NDD10, bit(8)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[9]
-     *  NDL Brick4 nostall
-     */
-    (rNPU1FIR_NDD10, bit(9)) ? defaultMaskedError;
-
-    /** NPU1FIR[10]
-     *  NDL Brick5 stall
-     */
-    (rNPU1FIR_NDD10, bit(10)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[11]
-     *  NDL Brick5 nostall
-     */
-    (rNPU1FIR_NDD10, bit(11)) ? defaultMaskedError;
-
-    /** NPU1FIR[12]
-     *  MISC Register ring error (ie noack)
-     */
-    (rNPU1FIR_NDD10, bit(12)) ? self_th_32perDay;
-
-    /** NPU1FIR[13]
-     *  MISC Parity error from ibr addr regi
-     */
-    (rNPU1FIR_NDD10, bit(13)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[14]
-     *  MISC Parity error on SCOM D/A addr reg
-     */
-    (rNPU1FIR_NDD10, bit(14)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[15]
-     *  MISC Parity error on MISC Cntrl reg
-     */
-    (rNPU1FIR_NDD10, bit(15)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[16]
-     *  MISC NMMU signaled Local Checkstop
-     */
-    (rNPU1FIR_NDD10, bit(16)) ? defaultMaskedError;
-
-    /** NPU1FIR[17]
-     *  ATS Invalid TVT entry
-     */
-    (rNPU1FIR_NDD10, bit(17)) ? defaultMaskedError;
-
-    /** NPU1FIR[18]
-     *  ATS TVT Address range error
-     */
-    (rNPU1FIR_NDD10, bit(18)) ? defaultMaskedError;
-
-    /** NPU1FIR[19]
-     *  ATS TCE Page access error
-     */
-    (rNPU1FIR_NDD10, bit(19)) ? defaultMaskedError;
-
-    /** NPU1FIR[20]
-     *  ATS Effective Address hit multiple TCE
-     */
-    (rNPU1FIR_NDD10, bit(20)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[21]
-     *  ATS TCE Page access error
-     */
-    (rNPU1FIR_NDD10, bit(21)) ? defaultMaskedError;
-
-    /** NPU1FIR[22]
-     *  ATS Timeout on TCE tree walk
-     */
-    (rNPU1FIR_NDD10, bit(22)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[23]
-     *  ATS Parity error on TCE cache dir array
-     */
-    (rNPU1FIR_NDD10, bit(23)) ? self_th_32perDay;
-
-    /** NPU1FIR[24]
-     *  ATS Parity error on TCE cache data array
-     */
-    (rNPU1FIR_NDD10, bit(24)) ? self_th_32perDay;
-
-    /** NPU1FIR[25]
-     *  ATS ECC UE on Effective Address array
-     */
-    (rNPU1FIR_NDD10, bit(25)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[26]
-     *  ATS ECC CE on Effective Address array
-     */
-    (rNPU1FIR_NDD10, bit(26)) ? self_th_32perDay;
-
-    /** NPU1FIR[27]
-     *  ATS ECC UE on TDRmem array
-     */
-    (rNPU1FIR_NDD10, bit(27)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[28]
-     *  ATS ECC CE on TDRmem array
-     */
-    (rNPU1FIR_NDD10, bit(28)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[29]
-     *  ATS ECC UE on CQ CTL DMA Read
-     */
-    (rNPU1FIR_NDD10, bit(29)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[30]
-     *  ATS ECC CE on CQ CTL DMA Read
-     */
-    (rNPU1FIR_NDD10, bit(30)) ? self_th_32perDay;
-
-    /** NPU1FIR[31]
-     *  ATS Parity error on TVT entry
-     */
-    (rNPU1FIR_NDD10, bit(31)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[32]
-     *  ATS Parity err on IODA Address Reg
-     */
-    (rNPU1FIR_NDD10, bit(32)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[33]
-     *  ATS Parity error on ATS Control Register
-     */
-    (rNPU1FIR_NDD10, bit(33)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[34]
-     *  ATS Parity error on ATS reg
-     */
-    (rNPU1FIR_NDD10, bit(34)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[35]
-     *  ATS Invalid IODA Table Select entry
-     */
-    (rNPU1FIR_NDD10, bit(35)) ? self_th_1; # NIMBUS_10
-
-    /** NPU1FIR[36:61]
-     *  Reserved
-     */
-    (rNPU1FIR_NDD10, bit(36|37|38|39|40|41|42|43|44|45|46|47|48|49|50|51|52|53|54|55|56|57|58|59|60|61)) ? defaultMaskedError;
-
-    /** NPU1FIR[62]
-     *  scom error
-     */
-    (rNPU1FIR_NDD10, bit(62)) ? defaultMaskedError;
-
-    /** NPU1FIR[63]
-     *  scom error
-     */
-    (rNPU1FIR_NDD10, bit(63)) ? defaultMaskedError;
-
-};
-
-################################################################################
 # P9 chip PBWESTFIR
 ################################################################################
 
@@ -8429,7 +7859,6 @@ group gPCI2_CHIPLET_FIR filter singlebit
 .include "p9_common_actions.rule";
 # Include the chip-specific action set.
 .include "p9_proc_common_actions.rule";
-.include "p9_nimbus_actions.rule";
 
 actionclass analyzeConnectedEQ0     { analyze(connected(TYPE_EQ,      0)); };
 actionclass analyzeConnectedEQ1     { analyze(connected(TYPE_EQ,      1)); };
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_nimbus_actions.rule b/src/usr/diag/prdf/common/plat/p9/p9_nimbus_actions.rule
deleted file mode 100644
index 17d8a2223..000000000
--- a/src/usr/diag/prdf/common/plat/p9/p9_nimbus_actions.rule
+++ /dev/null
@@ -1,43 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/diag/prdf/common/plat/p9/p9_nimbus_actions.rule $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2016,2017
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-actionclass aNPU0FIR_NDD10 {capture(cNPU0FIR_NDD10); analyze(gNPU0FIR_NDD10);};
-actionclass aNPU1FIR_NDD10 {capture(cNPU1FIR_NDD10); analyze(gNPU1FIR_NDD10);};
-actionclass aNPU0FIR       {capture(cNPU0FIR);       analyze(gNPU0FIR);      };
-actionclass aNPU1FIR       {capture(cNPU1FIR);       analyze(gNPU1FIR);      };
-actionclass analyzeNPU2FIR {capture(cNPU2FIR);       analyze(gNPU2FIR);      };
-
-actionclass analyzeNPU0FIR
-{
-    try( funccall("checkNimbusDD10"   ), aNPU0FIR_NDD10 );
-    try( funccall("checkNotNimbusDD10"), aNPU0FIR       );
-};
-
-actionclass analyzeNPU1FIR
-{
-    try( funccall("checkNimbusDD10"   ), aNPU1FIR_NDD10 );
-    try( funccall("checkNotNimbusDD10"), aNPU1FIR       );
-};
-
diff --git a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C
index 8ed2944ee..7e53dc4c5 100644
--- a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C
+++ b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C
@@ -273,6 +273,9 @@ void getAddresses( TrgtMap_t & io_targMap )
         0x05013030, // INTCQFIR
         0x05013400, // PBIOEFIR
         0x05013800, // PBIOOFIR
+        0x05013C00, // NPU0FIR
+        0x05013C40, // NPU1FIR
+        0x05013C80, // NPU2FIR
 
         0x0604000a, // XBUS_LFIR
         0x06010840, // XBPPEFIR
@@ -1007,38 +1010,10 @@ errlHndl_t getHwConfig( std::vector<HOMER_ChipInfo_t> & o_chipInfVector,
 /***************************************************/
 static HOMER_ChipSpecAddr_t  s_ecDepProcRegisters[]
 {
-    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x10,
-      0, 0x0000000005011400ll }, // NPU0FIR DD1
-
-    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x10,
-      0, 0x0000000005011440ll }, // NPU1FIR DD1
-
-    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x20,
-      0, 0x0000000005013C00ll }, // NPU0FIR DD2
-
-    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x20,
-      0, 0x0000000005013C40ll }, // NPU1FIR DD2
-
-    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x20,
-      0, 0x000000005013C80ll },  // NPU2FIR DD2
-
-    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x21,
-      0, 0x0000000005013C00ll }, // NPU0FIR DD2.1
-
-    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x21,
-      0, 0x0000000005013C40ll }, // NPU1FIR DD2.1
-
-    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x21,
-      0, 0x000000005013C80ll },  // NPU2FIR DD2.1
-
-    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x22,
-      0, 0x0000000005013C00ll }, // NPU0FIR DD2.2
-
-    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x22,
-      0, 0x0000000005013C40ll }, // NPU1FIR DD2.2
-
-    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x22,
-      0, 0x000000005013C80ll }   // NPU2FIR DD2.2
+    /* EXAMPLE:
+    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x10, 0, 0x05011400ll }, // DD1
+    { HOMER_CHIP_NIMBUS, TRGT_PROC, REG_FIR, 0x20, 0, 0x05013C00ll }, // DD2
+    */
 };
 
 //------------------------------------------------------------------------------