SW252411: RAS Review: mss_draminit, mss_draminit_training, mss_funcs

Change-Id: Ic15d47f3cab295c132efb959506ac368174d9a08
CQ:SW252411
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10107
Reviewed-by: Priti Bavaria <pbavari@us.ibm.com>
Tested-by: Priti Bavaria <pbavari@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10353
Tested-by: Jenkins Server
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

7 files changed, 398 insertions, 51 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/memory_mss_funcs.xml b/src/usr/hwpf/hwp/dram_training/memory_mss_funcs.xml
index 7eb182b48..8a33cabd1 100644
--- a/src/usr/hwpf/hwp/dram_training/memory_mss_funcs.xml
+++ b/src/usr/hwpf/hwp/dram_training/memory_mss_funcs.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- IBM CONFIDENTIAL                                                       -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!-- COPYRIGHT International Business Machines Corp. 2013,2014              -->
 <!--                                                                        -->
 <!-- p1                                                                     -->
 <!--                                                                        -->
@@ -21,51 +21,145 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <hwpErrors>
-<!-- $Id: memory_mss_funcs.xml,v 1.1 2013/06/19 18:28:11 bellows Exp $ -->
+<!-- $Id: memory_mss_funcs.xml,v 1.3 2014/03/31 15:54:05 jdsloat Exp $ -->
 <!-- For file ../../ipl/fapi/mss_funcs.C -->
 <!-- // *! OWNER NAME : jdsloat@us.ibm.com -->
 <!-- // *! BACKUP NAME : -->
 
+
+
+<registerFfdc>
+  <id>REG_FFDC_MSS_CCS_FAILURE</id>
+  <scomRegister>MEM_MBA01_CCS_MODEQ_0x030106A7</scomRegister>
+  <scomRegister>MEM_MBA01_STATQ_0x030106A6</scomRegister>
+  <scomRegister>MEM_MBA01_CCS_CNTLQ_0x030106A5</scomRegister>
+</registerFfdc>
+
+<registerFfdc>
+  <id>REG_FFDC_MSS_RCD_PARITY_FAILURE</id>
+  <scomRegister>MEM_MBA01_CALFIR_0x03010402</scomRegister>
+</registerFfdc>
+
 <!-- Original Source for RC_MSS_CCS_READ_MISCOMPARE memory_errors.xml -->
   <hwpError>
     <rc>RC_MSS_CCS_READ_MISCOMPARE</rc>
     <description>The ccs errors at runtime and registers a read miscompare.</description>
+  <ffdc>REG_CONTENTS</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_CCS_FAILURE</id>
+    <target>TARGET_MBA_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
 </hwpError>
 
 <!-- Original Source for RC_MSS_CCS_UE_SUE memory_errors.xml -->
   <hwpError>
     <rc>RC_MSS_CCS_UE_SUE</rc>
     <description>The ccs errors at runtime and registers a UE or SUE</description>
+  <ffdc>REG_CONTENTS</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_CCS_FAILURE</id>
+    <target>TARGET_MBA_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
 </hwpError>
 
 <!-- Original Source for RC_MSS_CCS_CAL_TIMEOUT memory_errors.xml -->
   <hwpError>
     <rc>RC_MSS_CCS_CAL_TIMEOUT</rc>
     <description>The ccs errors at runtime and registers a calibration operation timeout</description>
+  <ffdc>REG_CONTENTS</ffdc>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_CCS_FAILURE</id>
+    <target>TARGET_MBA_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
 </hwpError>
 
 <!-- Original Source for RC_MSS_CCS_HUNG memory_errors.xml -->
   <hwpError>
     <rc>RC_MSS_CCS_HUNG</rc>
     <description>The ccs failed to return from in_progress status and failed to describe an error further.</description>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_CCS_FAILURE</id>
+    <target>TARGET_MBA_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
 </hwpError>
 
 <!-- Original Source for RC_MSS_RCD_PARITY_ERROR_LIMIT memory_errors.xml -->
   <hwpError>
     <rc>RC_MSS_RCD_PARITY_ERROR_LIMIT</rc>
     <description>The number of rcd parity errors have exceeded the maximum allowable number</description>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_RCD_PARITY_FAILURE</id>
+    <target>TARGET_MBA_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
 </hwpError>
 
 <!-- Original Source for RC_MSS_RCD_PARITY_ERROR_PORT0 memory_errors.xml -->
   <hwpError>
     <rc>RC_MSS_RCD_PARITY_ERROR_PORT0</rc>
     <description>An rcd parity error has been registered on port_0</description>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_RCD_PARITY_FAILURE</id>
+    <target>TARGET_MBA_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
 </hwpError>
 
 <!-- Original Source for RC_MSS_RCD_PARITY_ERROR_PORT1 memory_errors.xml -->
   <hwpError>
     <rc>RC_MSS_RCD_PARITY_ERROR_PORT1</rc>
     <description>An rcd parity error has been registered on port_1</description>
+  <collectRegisterFfdc>
+    <id>REG_FFDC_MSS_RCD_PARITY_FAILURE</id>
+    <target>TARGET_MBA_ERROR</target>
+  </collectRegisterFfdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
 </hwpError>
 
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/memory_mss_draminit.xml b/src/usr/hwpf/hwp/dram_training/mss_draminit/memory_mss_draminit.xml
index 0a9689da7..6eff9194e 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/memory_mss_draminit.xml
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/memory_mss_draminit.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- IBM CONFIDENTIAL                                                       -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!-- COPYRIGHT International Business Machines Corp. 2013,2014              -->
 <!--                                                                        -->
 <!-- p1                                                                     -->
 <!--                                                                        -->
@@ -21,7 +21,45 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <hwpErrors>
-<!-- $Id: memory_mss_draminit.xml,v 1.1 2013/06/19 18:27:45 bellows Exp $ -->
+<!-- $Id: memory_mss_draminit.xml,v 1.2 2014/03/28 21:04:03 jdsloat Exp $ -->
 <!-- For file ../../ipl/fapi/mss_draminit.C -->
 
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_RTT_NOM_IMP_INPUT_ERROR</rc>
+  <description>Unknown Value for RTT_NOM within the VPD</description>
+  <ffdc>IMP</ffdc>
+  <ffdc>PORT</ffdc>
+  <ffdc>DIMM</ffdc>
+  <ffdc>RANK</ffdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
+  <gard>
+    <target>TARGET_MBA_ERROR</target>
+  </gard>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_RTT_WR_IMP_INPUT_ERROR</rc>
+  <description>Unknown Value for RTT_WR within the VPD</description>
+  <ffdc>IMP</ffdc>
+  <ffdc>PORT</ffdc>
+  <ffdc>DIMM</ffdc>
+  <ffdc>RANK</ffdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
+  <gard>
+    <target>TARGET_MBA_ERROR</target>
+  </gard>
+</hwpError>
+
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
index 3d3ae22d1..08ae5dd40 100755
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2013              */
+/* COPYRIGHT International Business Machines Corp. 2012,2014              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit.C,v 1.59 2013/11/11 20:50:06 jdsloat Exp $
+// $Id: mss_draminit.C,v 1.65 2014/04/09 22:47:08 jdsloat Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -28,6 +28,12 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.65   | jdsloat  |09-APL-14| Fixed ifdef around #include mss_lrdimm_ddr4_funcs.H
+//  1.64   | jdsloat  |01-APL-14| RAS review edits/changes
+//  1.63   | jdsloat  |01-APL-14| RAS review edits/changes
+//  1.62   | jdsloat  |28-MAR-14| RAS review edits/changes
+//  1.61   | kcook    | 03/18/13| Added include mss_lrdimm_ddr4_funcs.H
+//  1.60   | kcook    | 03/14/13| Added calls to DDR4 ISDIMM functions.
 //  1.59   | jdsloat  | 11/11/13| Changed EFF attributes to VPD named attributes
 //  1.58   | jdsloat  | 10/15/13| Added rc checks in ddr4 shadow regs check per review request
 //  1.57   | jdsloat  | 10/09/13| Added mrs_load_ddr4 with defines for ddr4 usage, added shadow regs, removed complicated flow
@@ -114,7 +120,9 @@
 #include <mss_lrdimm_funcs.H>
 #include <mss_ddr4_funcs.H>
 
-
+#ifdef FAPI_LRDIMM
+#include <mss_lrdimm_ddr4_funcs.H>
+#endif
 
 #ifndef FAPI_LRDIMM
 using namespace fapi;
@@ -122,7 +130,7 @@ fapi::ReturnCode mss_lrdimm_rcd_load(Target& i_target, uint32_t port_number, uin
 {
    ReturnCode rc;
 
-   FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString());
+   FAPI_ERR("Invalid exec of mss_lrdimm_rcd_load on %s!", i_target.toEcmdString());
    FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
    return rc;
 
@@ -131,14 +139,14 @@ ReturnCode mss_lrdimm_mrs_load(Target& i_target, uint32_t i_port_number, uint32_
 {
    ReturnCode rc;
 
-   FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString());
+   FAPI_ERR("Invalid exec of mss_lrdimm_mrs_load function on %s!", i_target.toEcmdString());
    FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
    return rc;
 
 }
 #endif
 
- #ifndef FAPI_DDR4
+#ifndef FAPI_DDR4
 using namespace fapi;
 fapi::ReturnCode mss_mrs_load_ddr4(Target& i_target, uint32_t port_number, uint32_t& ccs_inst_cnt)
 {
@@ -149,6 +157,33 @@ fapi::ReturnCode mss_mrs_load_ddr4(Target& i_target, uint32_t port_number, uint3
    return rc;
 
 }
+fapi::ReturnCode mss_rcd_load_ddr4(Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt)
+{
+   ReturnCode rc;
+
+   FAPI_ERR("Invalid exec of rcd_load_ddr4  %s!", i_target.toEcmdString());
+   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
+   return rc;
+
+}
+fapi::ReturnCode mss_lrdimm_ddr4_db_load(Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt)
+{
+   ReturnCode rc;
+
+   FAPI_ERR("Invalid exec of lrdimm_ddr4_db_load  %s!", i_target.toEcmdString());
+   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
+   return rc;
+
+}
+fapi::ReturnCode mss_ddr4_invert_mpr_write(Target& i_target)
+{
+   ReturnCode rc;
+
+   FAPI_ERR("Invalid exec of ddr4_invert_mpr_write  %s!", i_target.toEcmdString());
+   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
+   return rc;
+
+}
 
 #endif
 
@@ -339,7 +374,7 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 		rc_num = rc_num | data_buffer_64.setBit(61);
 		rc_num = rc_num | data_buffer_64.setBit(62);
 		rc_num = rc_num | data_buffer_64.setBit(63);
-		rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
+                rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
 		if(rc) return rc;
 
 		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
@@ -489,7 +524,9 @@ ReturnCode mss_draminit_cloned(Target& i_target)
             FAPI_ERR(" assert_resetn Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
             return rc;
         }
+
         rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode)
+	if(rc) return rc;
 
         rc = mss_assert_resetn(i_target, 1 ); // de-assert a reset
         if(rc)
@@ -504,24 +541,46 @@ ReturnCode mss_draminit_cloned(Target& i_target)
             if (!((dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_UDIMM)||(dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)))
             {
                 // Step three: Load RCD Control Words
-                rc = mss_rcd_load(i_target, port_number, ccs_inst_cnt);
-                if(rc)
+                if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) 
                 {
-                    FAPI_ERR(" rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                    return rc;
-                }
+                   rc = mss_rcd_load_ddr4(i_target, port_number, ccs_inst_cnt);
+                   if(rc)
+                   {
+                       FAPI_ERR(" rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+                       return rc;
+                   }
+                   if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM )
+                   {
+                      // Set Data Buffer Function  words
+                      rc = mss_lrdimm_ddr4_db_load(i_target, port_number, ccs_inst_cnt);
+                      if(rc)
+                      {
+                          FAPI_ERR(" LRDIMM rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+                          return rc;
+                      }
+                   }
 
-                if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM )
+                }
+                else 
                 {
-                   // Set Function 1-13 rcd words
-                   rc = mss_lrdimm_rcd_load(i_target, port_number, ccs_inst_cnt);
+                   rc = mss_rcd_load(i_target, port_number, ccs_inst_cnt);
                    if(rc)
                    {
-                       FAPI_ERR(" LRDIMM rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+                       FAPI_ERR(" rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
                        return rc;
                    }
-                }
-     
+
+                   if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM )
+                   {
+                      // Set Function 1-13 rcd words
+                      rc = mss_lrdimm_rcd_load(i_target, port_number, ccs_inst_cnt);
+                      if(rc)
+                      {
+                          FAPI_ERR(" LRDIMM rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+                          return rc;
+                      }
+                   }
+                } 
             }
         }
 
@@ -1041,6 +1100,14 @@ ReturnCode mss_draminit_cloned(Target& i_target)
 	    }
 	}
 
+        if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) && (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM || dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) 
+        {
+           FAPI_INF("Performing B-side address inversion MPR write pattern");
+
+           rc = mss_ddr4_invert_mpr_write(i_target);
+           if (rc) return rc;
+        }
+
 	if (rc_num)
 	{
 	    FAPI_ERR( "mss_draminit: Error setting up buffers");
@@ -1144,7 +1211,7 @@ ReturnCode mss_rcd_load(
     ecmdDataBufferBase csn_8(8);
     rc_num = rc_num | csn_8.setBit(0,8);
     ecmdDataBufferBase odt_4(4);
-    rc_num = rc_num | odt_4.setBit(0,4);
+    rc_num = rc_num | odt_4.clearBit(0,4);
     ecmdDataBufferBase ddr_cal_type_4(4);
 
     ecmdDataBufferBase num_idles_16(16);
@@ -1343,7 +1410,7 @@ ReturnCode mss_mrs_load(
     ecmdDataBufferBase csn_8(8);
     rc_num = rc_num | csn_8.setBit(0,8);
     ecmdDataBufferBase odt_4(4);
-    rc_num = rc_num | odt_4.setBit(0,4);
+    rc_num = rc_num | odt_4.clearBit(0,4);
     ecmdDataBufferBase ddr_cal_type_4(4);
 
     ecmdDataBufferBase csn_setup_8(8);
@@ -1777,8 +1844,15 @@ ReturnCode mss_mrs_load(
                     }
                     else
                     {
+			//DECONFIG and FFDC INFO
+			const fapi::Target & TARGET_MBA_ERROR = i_target;
+                        const uint8_t & IMP = dram_rtt_nom[i_port_number][dimm_number][rank_number];
+                        const uint32_t & PORT = i_port_number;
+                        const uint32_t & DIMM = dimm_number;
+                        const uint32_t & RANK = rank_number;
+
                         FAPI_ERR( "mss_mrs_load: Error determining ATTR_VPD_DRAM_RTT_NOM value: %d from attribute", dram_rtt_nom[i_port_number][dimm_number][rank_number]);
-                        FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR);
+                        FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_RTT_NOM_IMP_INPUT_ERROR);
                         return rc;
                     }
 
@@ -1826,8 +1900,16 @@ ReturnCode mss_mrs_load(
                     }
 		    else
 		    {
+
+			//DECONFIG and FFDC INFO
+			const fapi::Target & TARGET_MBA_ERROR = i_target;
+                        const uint8_t & IMP = dram_rtt_nom[i_port_number][dimm_number][rank_number];
+                        const uint32_t & PORT = i_port_number;
+                        const uint32_t & DIMM = dimm_number;
+                        const uint32_t & RANK = rank_number;
+
                         FAPI_ERR( "mss_mrs_load: Error determining ATTR_VPD_DRAM_RTT_WR value: %d from attribute", dram_rtt_wr[i_port_number][dimm_number][rank_number]);
-                        FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR);
+                        FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_RTT_WR_IMP_INPUT_ERROR);
                         return rc;
                     }
 
@@ -1976,7 +2058,8 @@ ReturnCode mss_mrs_load(
             // For LRDIMM  Set Rtt_nom, rtt_wr, driver impedance for R0 and R1
             if ( (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) && lrdimm_rank_mult_mode != 0 )
             {
-                 mss_lrdimm_mrs_load(i_target, i_port_number, dimm_number, io_ccs_inst_cnt);
+                 rc = mss_lrdimm_mrs_load(i_target, i_port_number, dimm_number, io_ccs_inst_cnt);
+                 if(rc) return rc;
             } // end LRDIMM 8R dir MRS 1
 
         } // end if has ranks
@@ -2007,7 +2090,7 @@ ReturnCode mss_assert_resetn (
 
     if (rc_num)
     {
-        FAPI_ERR( "mss_ccs_mode: Error setting up buffers");
+        FAPI_ERR( "mss_assert_resetn: Error setting up buffers");
         rc_buff.setEcmdError(rc_num);
         return rc_buff;
     }
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/memory_mss_draminit_training.xml b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/memory_mss_draminit_training.xml
index 5b9bf15da..087754f0f 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/memory_mss_draminit_training.xml
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/memory_mss_draminit_training.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- IBM CONFIDENTIAL                                                       -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!-- COPYRIGHT International Business Machines Corp. 2013,2014              -->
 <!--                                                                        -->
 <!-- p1                                                                     -->
 <!--                                                                        -->
@@ -21,20 +21,77 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <hwpErrors>
-<!-- $Id: memory_mss_draminit_training.xml,v 1.1 2013/06/19 18:27:49 bellows Exp $ -->
+<!-- $Id: memory_mss_draminit_training.xml,v 1.3 2014/03/29 19:48:36 jdsloat Exp $ -->
 <!-- For file ../../ipl/fapi/mss_draminit_training.C -->
 
-<!-- Original Source for RC_MSS_DRAMINIT_TRAINING_INIT_CAL_STALLED memory_errors.xml -->
-  <hwpError>
-    <rc>RC_MSS_DRAMINIT_TRAINING_INIT_CAL_STALLED</rc>
-    <description>One or more Rank Pairs Stalled Init Cal within Draminit_training</description>
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_SETBBM</rc>
+  <description>Unknown Value for DRAM_WIDTH being used.</description>
+  <ffdc>WIDTH</ffdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>LOW</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
 </hwpError>
 
-<!-- Original Source for RC_MSS_DRAMINIT_TRAINING_INIT_CAL_FAILED memory_errors.xml -->
-  <hwpError>
-    <rc>RC_MSS_DRAMINIT_TRAINING_INIT_CAL_FAILED</rc>
-    <description>One or more Rank Pairs Failed Init Cal within Draminit_training</description>
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_GETBBM</rc>
+  <description>Unknown Value for DRAM_WIDTH being used.</description>
+  <ffdc>WIDTH</ffdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>LOW</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
 </hwpError>
 
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_DIMM_SPARE_INPUT_ERROR</rc>
+  <description>Unknown Value for DIMM_SPARE being used.</description>
+  <ffdc>PORT</ffdc>
+  <ffdc>DIMM</ffdc>
+  <ffdc>RANK</ffdc>
+  <ffdc>SPARE</ffdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <callout>
+    <procedure>CODE</procedure>
+    <priority>LOW</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
+</hwpError>
+
+<hwpError>
+  <rc>RC_MSS_DRAMINIT_TRAINING_C4_PHY_TRANSLATION_ERROR</rc>
+  <description>Incorrect translation of bad bit mask between C4 and PHY</description>
+  <ffdc>PORT</ffdc>
+  <ffdc>BLOCK</ffdc>
+  <ffdc>QUAD</ffdc>
+  <ffdc>PHYLANE</ffdc>
+  <callout>
+    <target>TARGET_MBA_ERROR</target>
+    <priority>HIGH</priority>
+  </callout>
+  <deconfigure>
+    <target>TARGET_MBA_ERROR</target>
+  </deconfigure>
+</hwpError>
 
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
index bddb1c01f..2ab388499 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_training.C,v 1.77 2014/03/28 19:48:10 jdsloat Exp $
+// $Id: mss_draminit_training.C,v 1.80 2014/04/01 16:34:50 jdsloat Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -28,6 +28,9 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|------------------------------------------------
+//  1.80   | jdsloat  |01-APL-14| RAS review edits/changes
+//  1.79   | jdsloat  |01-APL-14| RAS review edits/changes
+//  1.78   | jdsloat  |28-MAR-14| RAS review edits/changes
 //  1.77   | jdsloat  |28-MAR-14| Added ifdef around #include for mss_lrdimm_ddr4_funcs.H
 //  1.76   | mwuu     |14-MAR-14| Fixed CDIMM full spare case in getC4dq2reg (bbm)
 //  1.75   | kcook    |14-MAR-14| Fixed mss_mxd_training stub function definition
@@ -470,7 +473,9 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
                  (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) )
             {
                  rc = mss_mrep_training(i_target, port);
+		 if(rc) return rc;
 		 rc = mss_mxd_training(i_target,port,0);
+		 if(rc) return rc;
             }
 	}
 
@@ -828,15 +833,14 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
 	return rc;
     }
 
+    // If we hit either of these States, the error callout originates from Mike Jones Bad Bit code. 
     if (complete_status == MSS_INIT_CAL_STALL)
     {
 	FAPI_ERR( "+++ Partial/Full calibration stall. Check Debug trace. +++");
-	FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_INIT_CAL_STALLED);
     }
     else if (error_status == MSS_INIT_CAL_FAIL)
     {
 	FAPI_ERR( "+++ Partial/Full calibration fail. Check Debug trace. +++");
-	FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_INIT_CAL_FAILED);
     }
     else
     {
@@ -3227,7 +3231,8 @@ fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target)
 	FAPI_INF("Running flash->registers(set)");
 
 	std::vector<Target> mba_dimms;
-	fapiGetAssociatedDimms(mba_target, mba_dimms);	// functional dimms
+	rc = fapiGetAssociatedDimms(mba_target, mba_dimms);	// functional dimms
+	if(rc) return rc;
 
 	// ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port],
 	// 						 GROUP2[port], GROUP3[port]
@@ -3265,8 +3270,12 @@ fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target)
 			l_dram_width = 32;
 			break;
 		default:
+			//DECONFIG and FFDC INFO
+			const fapi::Target & TARGET_MBA_ERROR = mba_target;
+                        const uint8_t & WIDTH = l_dram_width;
+
 			FAPI_ERR("ATTR_EFF_DRAM_WIDTH is invalid %u", l_dram_width);
-			FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR);
+			FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_SETBBM);
 			return rc;
 	}
 
@@ -3539,10 +3548,17 @@ fapi::ReturnCode mss_get_dqs_lane (const fapi::Target & i_mba,
 			o_lane |= 0x03;
 			break;
 		default:
+			//DECONFIG and FFDC INFO
+			const fapi::Target & TARGET_MBA_ERROR = i_mba;
+			const uint8_t & PORT = i_port;
+			const uint8_t & BLOCK = i_block;
+			const uint8_t & QUAD = i_quad;
+			const uint8_t & PHYLANE = phy_lane;
+
 			FAPI_ERR("\t!!!  (Port%i, dp18_%i, q=%i)  phy_lane(%i)"
 				"returned from mss_c4_phy is invalid",
 				i_port, i_block, i_quad, phy_lane);
-//			FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR);
+			FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_C4_PHY_TRANSLATION_ERROR);
 	}
 	return rc;
 } //end mss_get_dqs_lane
@@ -3624,7 +3640,8 @@ fapi::ReturnCode mss_get_bbm_regs (const fapi::Target & mba_target)
 	FAPI_INF("Running (get)registers->flash");
 
 	std::vector<Target> mba_dimms;
-	fapiGetAssociatedDimms(mba_target, mba_dimms);	// functional dimms
+	rc = fapiGetAssociatedDimms(mba_target, mba_dimms);	// functional dimms
+	if(rc) return rc;
 
 	// 4 dimms per MBA, 2 per port
 	// ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port],
@@ -3656,8 +3673,12 @@ fapi::ReturnCode mss_get_bbm_regs (const fapi::Target & mba_target)
 			l_dram_width = 32;
 			break;
 		default:
+			//DECONFIG and FFDC INFO
+			const fapi::Target & TARGET_MBA_ERROR = mba_target;
+                        const uint8_t & WIDTH = l_dram_width;
+
 			FAPI_ERR("ATTR_EFF_DRAM_WIDTH is invalid %u", l_dram_width);
-			FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR);
+			FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_GETBBM);
 			return rc;
 	}
 
@@ -3836,9 +3857,17 @@ ReturnCode getC4dq2reg(const Target & i_mba, const uint8_t i_port,
 			            spare_bitmap = 0x00;
 		            break;
 					default:
+
+						//DECONFIG and FFDC INFO
+						const fapi::Target & TARGET_MBA_ERROR = i_mba;
+                        			const uint8_t & SPARE = dimm_spare[i_port][i_dimm][i_rank];
+                        			const uint8_t & PORT = i_port;
+                        			const uint8_t & DIMM = i_dimm;
+                        			const uint8_t & RANK = i_rank;
+
 						FAPI_ERR("ATTR_VPD_DIMM_SPARE is invalid %u", 
 							dimm_spare[i_port][i_dimm][i_rank]);
-						FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR);
+						FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DIMM_SPARE_INPUT_ERROR);
 						return rc;
 				}
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_funcs.C
index 85b30452a..f2f129ca0 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_funcs.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_funcs.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_funcs.C,v 1.35 2014/02/21 21:58:42 jdsloat Exp $
+// $Id: mss_funcs.C,v 1.38 2014/04/01 15:24:50 jdsloat Exp $
 /* File mss_funcs.C created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */
 
 //------------------------------------------------------------------------------
@@ -43,6 +43,9 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.38   | jdsloat  |01-APL-14| RAS review edits/changes
+//  1.37   | jdsloat  |28-MAR-14| RAS review edits/changes
+//  1.36   | kcook    | 03/12/14| Added check for DDR3 LRDIMM during mss_execut_zq_cal.
 //  1.35   | jdsloat  | 02/21/14| Fixed an inf loop with edit 1.34 and 128GB DIMMs.
 //  1.34   | jdsloat  | 02/20/14| Edited set_end_bit to add a NOP to the end of every CCS execution per CCS defect
 //  1.33   | kcook    | 08/27/13| Removed LRDIMM functions to mss_lrdimm_funcs.C. Use with mss_funcs.H v1.16.
@@ -609,16 +612,28 @@ ReturnCode mss_ccs_fail_type(
 
     if (data_buffer.getBit(3))
     {
+	//DECONFIG and FFDC INFO
+	const fapi::Target & TARGET_MBA_ERROR = i_target;
+	const ecmdDataBufferBase & REG_CONTENTS = data_buffer;
+
         FAPI_ERR("CCS returned a FAIL condtion of \"Read Miscompare\" ");
         FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_READ_MISCOMPARE);
     } 
     else if (data_buffer.getBit(4))
     {
+	//DECONFIG and FFDC INFO
+	const fapi::Target & TARGET_MBA_ERROR = i_target;
+	const ecmdDataBufferBase & REG_CONTENTS = data_buffer;
+
         FAPI_ERR("CCS returned a FAIL condition of \"UE or SUE Error\" ");
         FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_UE_SUE);
     }
     else if (data_buffer.getBit(5))
     {
+	//DECONFIG and FFDC INFO
+	const fapi::Target & TARGET_MBA_ERROR = i_target;
+	const ecmdDataBufferBase & REG_CONTENTS = data_buffer;
+
         FAPI_ERR("CCS returned a FAIL condition of \"Calibration Operation Time Out\" ");
         FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_CAL_TIMEOUT);
     }
@@ -667,6 +682,9 @@ ReturnCode mss_execute_ccs_inst_array(
 	}
 	else
 	{
+	    //DECONFIG and FFDC INFO
+	    const fapi::Target & TARGET_MBA_ERROR = i_target;
+
             FAPI_ERR("Returning a CCS HUNG RC Value.");
 	    FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_HUNG);
 	    return rc;
@@ -739,16 +757,25 @@ ReturnCode mss_rcd_parity_check(
 
     if (rcd_parity_fail)
     {
+	//DECONFIG and FFDC INFO
+	const fapi::Target & TARGET_MBA_ERROR = i_target;
+
         FAPI_ERR("Ports 0 and 1 has exceeded a maximum number of RCD Parity Errors.");
         FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_LIMIT);
     }
     else if ((port_0_error) && (i_port == 0))
     {
+	//DECONFIG and FFDC INFO
+	const fapi::Target & TARGET_MBA_ERROR = i_target;
+
         FAPI_ERR("Port 0 has recorded an RCD Parity Error. ");
         FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_PORT0);
     }
     else if ((port_1_error) && (i_port == 1))
     {
+	//DECONFIG and FFDC INFO
+	const fapi::Target & TARGET_MBA_ERROR = i_target;
+
         FAPI_ERR("Port 1 has recorded an RCD Parity Error. ");
         FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_PORT1);
     }
@@ -825,6 +852,10 @@ ReturnCode mss_execute_zq_cal(
     uint8_t num_ranks_array[2][2]; //num_ranks_array[port][dimm]
     uint8_t dimm_type;
     uint8_t lrdimm_rank_mult_mode;
+    uint8_t dram_gen = 0;
+
+    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen);
+    if(rc) return rc;
 
     rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
     if(rc) return rc;
@@ -833,6 +864,8 @@ ReturnCode mss_execute_zq_cal(
 
     //Set up CCS Mode Reg for ZQ cal long and Init cal
     rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64);
+    if(rc) return rc;
+
     rc_num = rc_num | data_buffer_64.insert(stop_on_err_buffer_1, 0, 1, 0);
     rc_num = rc_num | data_buffer_64.insert(resetn_buffer_1, 24, 1, 0);
     if(rc_num)
@@ -847,7 +880,7 @@ ReturnCode mss_execute_zq_cal(
     {
         start_rank=(4 * dimm);
 
-        if (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) 
+        if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) ) 
         {
            rc = FAPI_ATTR_GET(ATTR_LRDIMM_RANK_MULT_MODE, &i_target, lrdimm_rank_mult_mode);
            if(rc) return rc;
diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index c91c309a3..c62bc5564 100755
--- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2013              */
+/* COPYRIGHT International Business Machines Corp. 2012,2014              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_scom_addresses.H,v 1.67 2013/12/16 19:38:35 dsanner Exp $
+// $Id: cen_scom_addresses.H,v 1.68 2014/03/28 21:06:47 jdsloat Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -44,6 +44,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.64   | jdsloat  |28-MAR-14| ADDED MEM SCOM CCS MODEQ, STATQ, and CAL FIR addresses.
 //  1.63   | mwuu     |18-Jun-13| Fixed naming of IO_FET_SLICE_EN_MAP1_P0_ADR0:3
 //  1.62   | mwuu     |18-Jun-13| Fixed naming of IO_FET_SLICE_EN_MAP1_P0_ADR0_3
 //         |          |         | _0x80007C210301143F and for port 1 as well
@@ -277,6 +278,15 @@ CONST_UINT64_T( MEM_SCOM_0x03010000                    , ULL(0x03010000) );
 CONST_UINT64_T( MEM_MBA01_CCS_MODEQ_0x030106A7         , ULL(0x030106A7) );
 CONST_UINT64_T( MEM_MBA23_CCS_MODEQ_0x03010EA7         , ULL(0x03010EA7) );
 
+CONST_UINT64_T( MEM_MBA01_STATQ_0x030106A6             , ULL(0x030106A6) );
+CONST_UINT64_T( MEM_MBA23_STATQ_0x03010EA6             , ULL(0x03010EA6) );
+
+CONST_UINT64_T( MEM_MBA01_CCS_CNTLQ_0x030106A5         , ULL(0x030106A5) );
+CONST_UINT64_T( MEM_MBA23_CCS_CNTLQ_0x03010EA5         , ULL(0x03010EA5) );
+
+CONST_UINT64_T( MEM_MBA01_CALFIR_0x03010402            , ULL(0x03010402) );
+CONST_UINT64_T( MEM_MBA23_CALFIR_0x03010C00            , ULL(0x03010C00) );
+
 //------------------------------------------------------------------------------
 //      MEM TRACE
 //------------------------------------------------------------------------------
@@ -1797,6 +1807,9 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: cen_scom_addresses.H,v $
+Revision 1.68  2014/03/28 21:06:47  jdsloat
+ADDED MEM SCOM CCS MODEQ, STATQ, and CAL FIR addresses.
+
 Revision 1.67  2013/12/16 19:38:35  dsanner
 Fix compile error for proc_mpipl_clear_xstop.C