Row Repair enabled attributes and support function

Change-Id: Ic7493902fee7dcc9cbfbbddfcf9f58d47c4967c5
RTC: 195638
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61417
Reviewed-by: Devon A. Baughen <devon.baughen1@ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61432
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

4 files changed, 54 insertions, 3 deletions

diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.C
index 602b47408..988154f6c 100644
--- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.C
+++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_attr_cleanup.C
@@ -340,6 +340,30 @@ fapi2::ReturnCode set_spd_attributes( const fapi2::Target<fapi2::TARGET_TYPE_DIM
               "%s Failed to set ATTR_CEN_SPD_SDRAM_THERMAL_AND_REFRESH_OPTIONS", l_target_str_storage );
     FAPI_INF("%s Set ATTR_CEN_SPD_SDRAM_THERMAL_AND_REFRESH_OPTIONS 0x%02X ", l_target_str_storage, l_spd_byte1);
 
+    // SDRAM_OTHER_OPT_FEATURES = 9
+    l_spd_byte1 = i_spd[SDRAM_OTHER_OPT_FEATURES];
+    l_work_byte = (l_spd_byte1 >> 5) & 0x07; // bit 7-5
+
+    // Bits 7~6 (little endian order)
+    // 00: PPR not supported
+    // 01: Post package repair supported, one row per bank group
+    // 10: Reserved
+    // 11: Reserved
+
+    // Bit 5 - 0: sPPR not supported, 1: sPPR supported
+    if ( 0x03 == l_work_byte )
+    {
+        l_work2_byte = fapi2::ENUM_ATTR_ROW_REPAIR_SPPR_SUPPORTED_SUPPORTED;
+    }
+    else
+    {
+        l_work2_byte = fapi2::ENUM_ATTR_ROW_REPAIR_SPPR_SUPPORTED_UNSUPPORTED;
+    }
+
+    FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_ROW_REPAIR_SPPR_SUPPORTED, i_dimm, l_work2_byte),
+              "%s Failed to set ATTR_ROW_REPAIR_SPPR_SUPPORTED", l_target_str_storage );
+    FAPI_INF( "%s Set ATTR_ROW_REPAIR_SPPR_SUPPORTED 0x%02X ", l_target_str_storage, l_work2_byte );
+
     // MODULE_NOMINAL_VOLTAGE = 11
     l_spd_byte1 = i_spd[MODULE_NOMINAL_VOLTAGE];
     l_work_byte = l_spd_byte1 & 0x3;  // bits 1-0
diff --git a/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml b/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml
index b649ab738..f445fdf85 100644
--- a/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml
+++ b/src/import/chips/centaur/procedures/xml/attribute_info/dimm_spd_vpd_attributes.xml
@@ -339,6 +339,19 @@ The following attributes can be queried from both DDR3 and DDR4 DIMMs
 </attribute>
 
 <attribute>
+    <id>ATTR_ROW_REPAIR_SPPR_SUPPORTED</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+      True or false whether sPPR (soft post package row repair) is supported
+      Located in DDR4 SPD byte 9, bit 5 (bits 7-6 denote whether PPR in general
+      is supported)
+    </description>
+    <valueType>uint8</valueType>
+    <enum>SUPPORTED = 1, UNSUPPORTED = 0</enum>
+    <writeable/>
+</attribute>
+
+<attribute>
     <id>ATTR_CEN_SPD_MODULE_THERMAL_SENSOR</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
index 7c3104315..6e73aced9 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H
@@ -20758,8 +20758,8 @@ fapi_try_exit:
 /// @note  Row Repair Data for a DIMM target. Data for 4 master ranks * 32 bits per row
 /// repair Each row repair contains: -5 bits: DRAM position (x8: 0-9, x4: 0-19) -3
 /// bits: slave ranks (0-7) -2 bits: bank group (0-3) -3 bits: bank (0-7) -18 bits:
-/// row -1 bits:
-/// unused
+/// row -1 bits: repair validity (0: repair is invalid, 1: repair is
+/// valid)
 ///
 inline fapi2::ReturnCode row_repair_data(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t* o_array)
 {
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_spd_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_spd_attributes.xml
index b2a022ac6..caab246c0 100755
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_spd_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_spd_attributes.xml
@@ -701,7 +701,7 @@
           -2 bits:  bank group (0-3)
           -3 bits:  bank (0-7)
           -18 bits: row
-          -1 bits:  unused
+          -1 bits:  repair validity (0: repair is invalid, 1: repair is valid)
         </description>
         <initToZero></initToZero>
         <valueType>uint8</valueType>
@@ -710,4 +710,18 @@
         <mssAccessorName>row_repair_data</mssAccessorName>
     </attribute>
 
+    <attribute>
+        <id>ATTR_ROW_REPAIR_SUPPORTED_MRW</id>
+        <targetType>TARGET_TYPE_SYSTEM</targetType>
+        <description>
+          True or false whether row repair is supported
+          MRW attribute
+        </description>
+        <valueType>uint8</valueType>
+        <enum>SUPPORTED = 1, UNSUPPORTED = 0</enum>
+        <platInit/>
+        <default>0</default>
+        <writeable/>
+    </attribute>
+
 </attributes>