diff options
Diffstat (limited to 'import/chips/p9')
14 files changed, 993 insertions, 639 deletions
diff --git a/import/chips/p9/common/pmlib/include/occhw_irq_config.h b/import/chips/p9/common/pmlib/include/occhw_irq_config.h index fa6a81e0..94bf77bf 100644 --- a/import/chips/p9/common/pmlib/include/occhw_irq_config.h +++ b/import/chips/p9/common/pmlib/include/occhw_irq_config.h @@ -69,7 +69,7 @@ #define OCCHW_IRQ_ROUTES \ OCCHW_IRQ_DEBUGGER OCCHW_IRQ_TARGET_ID_NONE \ OCCHW_IRQ_TRACE_TRIGGER OCCHW_IRQ_TARGET_ID_NONE \ - OCCHW_IRQ_OCC_ERROR OCCHW_IRQ_TARGET_ID_NONE \ + OCCHW_IRQ_OCC_ERROR OCCHW_IRQ_TARGET_ID_GPE2\ OCCHW_IRQ_PBA_ERROR OCCHW_IRQ_TARGET_ID_NONE \ OCCHW_IRQ_SRT_ERROR OCCHW_IRQ_TARGET_ID_NONE \ OCCHW_IRQ_GPE0_HALT OCCHW_IRQ_TARGET_ID_405_NONCRIT \ diff --git a/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h b/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h index b6c5a5b5..9911123c 100644 --- a/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h +++ b/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h @@ -61,10 +61,11 @@ enum MESSAGE_ID_IPI2HI // #define PGPE_RC_SUCCESS 0x01 #define PGPE_WOF_RC_NOT_ENABLED 0x10 -#define PGPE_RC_PSTATES_DISABLED 0x11 +#define PGPE_RC_PSTATES_NOT_STARTED 0x11 #define PGPE_RC_REQ_PSTATE_ALREADY_STARTED 0x12 -#define PGPE_RC_REQ_PSTATE_ALREADY_SUSPENDED 0x13 +#define PGPE_RC_REQ_PSTATE_ALREADY_STOPPED 0x13 #define PGPE_RC_OCC_NOT_PMCR_OWNER 0x14 +#define PGPE_RC_PM_COMPLEX_SUSPEND_SAFE_MODE 0x15 // Active quad mismatch with requested active quads. PGPE did not switch // to using the new VFRT. The original VFRT is still being used. #define PGPE_WOF_RC_VFRT_QUAD_MISMATCH 0x20 diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h index 078c883e..95e1dabc 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe.h @@ -60,6 +60,8 @@ //#Defines // #define OCC_IPC_IMMEDIATE_RESP 0x0080 +#define CCSR_CORE_CONFIG_MASK 0x80000000 + /// PGPE PState typedef struct @@ -67,12 +69,18 @@ typedef struct PkSemaphore sem_process_req; PkSemaphore sem_actuate; PkSemaphore sem_sgpe_wait; + PkSemaphore sem_safe_mode_and_pm_suspend_req; } PgpePstateRecord; /// PGPE PState +void p9_pgpe_irq_handler_occ_error(void* arg, PkIrqId irq); +void p9_pgpe_irq_handler_sgpe_halt(void* arg, PkIrqId irq); +void p9_pgpe_irq_handler_xstop_gpe2(void* arg, PkIrqId irq); void p9_pgpe_irq_handler_pcb_type1(void* arg, PkIrqId irq); +void p9_pgpe_irq_handler_ipi2_lo(void* arg, PkIrqId irq); void p9_pgpe_thread_process_requests(void* arg); void p9_pgpe_thread_actuate_pstates(void* arg); +void p9_pgpe_thread_safe_mode_and_pm_suspend(void* arg); ///PGPE PState Info void p9_pgpe_gen_pstate_info(); @@ -83,4 +91,7 @@ void p9_pgpe_fit_init(); ///PGPE IPC void p9_pgpe_ipc_init(); +//OCB Heartbeat Error +void p9_pgpe_ocb_hb_error_init(); + #endif //_P9_PGPE_H_ diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c index 684cfd62..636a6707 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_gppb.c @@ -73,7 +73,6 @@ void p9_pgpe_gppb_init() //External VRM decreasing rate in us/uv G_ext_vrm_dec_rate_mult_usperus = 1 / G_gppb->ext_vrm_transition_rate_dec_uv_per_us; - //G_gppb->nest_frequency_mhz = 1866; } // diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c index 1b20b2b8..45bff7d3 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_ipc_handlers.c @@ -104,6 +104,22 @@ void p9_pgpe_ipc_405_start_stop(ipc_msg_t* cmd, void* arg) G_already_sem_posted = 1; } } + else if(G_pstatesStatus == PSTATE_PM_SUSPEND_PENDING || + G_pstatesStatus == PSTATE_PM_SUSPENDED || + G_pstatesStatus == PSTATE_SAFE_MODE) + { + PK_TRACE_DBG("START_STOP: PM_SUSP/Safe\n"); + args->msg_cb.rc = PGPE_RC_PM_COMPLEX_SUSPEND_SAFE_MODE; + ipc_send_rsp(cmd, IPC_RC_SUCCESS); + G_ipc_pend_tbl[IPC_PEND_PSTATE_START].pending_ack = 0; + G_ipc_pend_tbl[IPC_PEND_PSTATE_START].pending_processing = 0; + + if (G_already_sem_posted == 0) + { + pk_semaphore_post(&G_pgpe_pstate_record.sem_process_req); + G_already_sem_posted = 1; + } + } else { //START @@ -111,7 +127,7 @@ void p9_pgpe_ipc_405_start_stop(ipc_msg_t* cmd, void* arg) { if (G_ipc_pend_tbl[IPC_PEND_PSTATE_START].pending_ack == 0) { - if(G_pstatesStatus == PSTATE_DISABLE) + if(G_pstatesStatus == PSTATE_INIT || G_pstatesStatus == PSTATE_STOPPED) { PK_TRACE_DBG("START_STOP: Start Rcvd\n"); @@ -123,11 +139,9 @@ void p9_pgpe_ipc_405_start_stop(ipc_msg_t* cmd, void* arg) //Post to Actuate Thread pk_semaphore_post(&G_pgpe_pstate_record.sem_actuate); } - else + else if (G_pstatesStatus == PSTATE_ACTIVE) { - PK_TRACE_DBG("START_STOP: Pstate Already Started\n"); - args->msg_cb.rc = PGPE_RC_REQ_PSTATE_ALREADY_STARTED; - ipc_send_rsp(cmd, IPC_RC_SUCCESS); + //\todo } } else @@ -144,15 +158,15 @@ void p9_pgpe_ipc_405_start_stop(ipc_msg_t* cmd, void* arg) if (G_ipc_pend_tbl[IPC_PEND_PSTATE_STOP].pending_ack == 0) { - if(G_pstatesStatus == PSTATE_DISABLE) + if(G_pstatesStatus != PSTATE_ACTIVE) { PK_TRACE_DBG("START_STOP: Pstate Already Stopped\n"); - args->msg_cb.rc = PGPE_RC_REQ_PSTATE_ALREADY_SUSPENDED; + args->msg_cb.rc = PGPE_RC_REQ_PSTATE_ALREADY_STOPPED; ipc_send_rsp(cmd, IPC_RC_SUCCESS); } else { - G_pstatesStatus = PSTATE_DISABLE; + G_pstatesStatus = PSTATE_STOPPED; G_ipc_pend_tbl[IPC_PEND_PSTATE_STOP].cmd = cmd; G_ipc_pend_tbl[IPC_PEND_PSTATE_STOP].pending_ack = 1; G_ipc_pend_tbl[IPC_PEND_PSTATE_STOP].pending_processing = 0; diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h index df8f189a..22fb6f89 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq.h @@ -73,13 +73,13 @@ extern const uint64_t ext_irq_vectors_gpe[NUM_EXT_IRQ_PRTY_LEVELS][2]; #define IRQ_VEC_PRTY0_GPE (uint64_t)(0x0000000000000000) // Non-task hi-prty IRQs // Shared between all instances -#define IRQ_VEC_PRTY1_GPE2 (uint64_t)(0x0080000000000000) // Task1-OCB_ERROR(HeartBeat Loss)/GPE3_HALT +#define IRQ_VEC_PRTY1_GPE2 (uint64_t)(0x2080000000000000) // Task1-OCB_ERROR(HeartBeat Loss)/GPE3_HALT #define IRQ_VEC_PRTY2_GPE2 (uint64_t)(0x0001000000000000) // Task2-CHECK_STOP_GPE2 #define IRQ_VEC_PRTY3_GPE2 (uint64_t)(0x0000000000000008) // Task3-IPI2-LO(Process Flags) #define IRQ_VEC_PRTY4_GPE2 (uint64_t)(0x0000001000000000) // Task4-IPI2-HI(IPC from OCC/SGPE) #define IRQ_VEC_PRTY5_GPE2 (uint64_t)(0x0000000000020000) // Task5-PCB_INTR_TYPE1(PCB Type1 from CME) #if OVERRIDE_OTHER_ENGINES_IRQS == 1 - #define IRQ_VEC_PRTY6_GPE2 (uint64_t)(0xFF7EFF03FFFDFFF5) // Other instances' IRQs + #define IRQ_VEC_PRTY6_GPE2 (uint64_t)(0xDF7EFF03FFFDFFF5) // Other instances' IRQs #else #define IRQ_VEC_PRTY6_GPE2 (uint64_t)(0x0000000000000000) // Other instances' IRQs #endif diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c index 2e40242d..c0decc2f 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c @@ -33,19 +33,62 @@ extern uint8_t G_coresPSRequest[MAX_CORES]; //per core requested pstate extern uint8_t G_pmcrOwner; extern uint32_t G_pstatesStatus; +//extern uint32_t G_process_occ_hb_error; +//extern uint32_t G_process_safe_mode; +//extern uint32_t G_process_pm_suspend; // //OCB Error Interrupt Handler // -//\TODO: -//Implement this handler. Implement Safe Mode -void p9_pgpe_irq_handler_ocb_error(void* arg, PkIrqId irq) +#define OCC_HB_ERROR 4 +void p9_pgpe_ocb_hb_error_init() { - PK_TRACE_DBG("OCB Error: Enter\n"); + PK_TRACE_DBG("OCC HB: Enter\n"); + + uint64_t firact; + + GPE_GETSCOM(OCB_OCCLFIRACT0, firact); + firact |= BIT64(OCC_HB_ERROR); + GPE_PUTSCOM(OCB_OCCLFIRACT0, firact); + + GPE_GETSCOM(OCB_OCCLFIRACT1, firact); + firact &= ~BIT64(OCC_HB_ERROR); + GPE_PUTSCOM(OCB_OCCLFIRACT1, firact); + + GPE_PUTSCOM(OCB_OCCLFIRMASK_AND, ~BIT64(OCC_HB_ERROR)); + + out32(OCB_OIMR0_CLR, BIT32(OCC_HB_ERROR)); + + PK_TRACE_DBG("OCC HB: Exit\n"); +} + +void p9_pgpe_irq_handler_occ_error(void* arg, PkIrqId irq) +{ + PK_TRACE_DBG("OCC Error: Enter\n"); PkMachineContext ctx; - pk_irq_vec_restore(&ctx);//Restore interrupts - PK_TRACE_DBG("OCB Error: Exit\n"); + ocb_occlfir_t fir; + fir.value = 0; + + out32(OCB_OISR0_CLR, BIT32(2)); + + //Read OCB_LFIR + GPE_GETSCOM(OCB_OCCLFIR, fir.value); + + //If OCB_LFIR[occ_hb_error] + if (fir.fields.occ_hb_error == 1) + { + p9_pgpe_pstate_pm_complex_suspend(); + } + else + { + //\todo handle other FIR Bits + PK_TRACE_INF("OCC Error: can't handle OCC_FIR[0x%08x%08x] \n", fir.value); + pk_halt(); + } + + pk_irq_vec_restore(&ctx); + PK_TRACE_DBG("OCC Error: Exit\n"); } // @@ -85,8 +128,30 @@ void p9_pgpe_irq_handler_ipi2_lo(void* arg, PkIrqId irq) { PK_TRACE_DBG("IPI2 Lo: Enter\n"); PkMachineContext ctx; + ocb_occflg_t occFlag; - pk_irq_vec_restore(&ctx);//Restore interrupts + out32(OCB_OISR1_CLR, BIT32(28)); + + //Read OCC_FLAGS + occFlag.value = 0; + occFlag.value = in32(OCB_OCCFLG); + + //If OCC_FLAGS[PM_SUSPEND + if (occFlag.value & BIT32(PM_COMPLEX_SUSPEND)) + { + p9_pgpe_pstate_pm_complex_suspend(); + } + else if (occFlag.value & BIT32(PGPE_SAFE_MODE)) + { + p9_pgpe_pstate_safe_mode(); + } + else + { + PK_TRACE_DBG("IPI2 Lo: !Suspend and !SafeMode\n"); + } + + + pk_irq_vec_restore(&ctx); PK_TRACE_DBG("IPI2 Lo: Exit\n"); } @@ -104,7 +169,7 @@ void p9_pgpe_irq_handler_pcb_type1(void* arg, PkIrqId irq) uint32_t coresPendPSReq = in32(OCB_OPIT1PRA); uint32_t c; - if (G_pstatesStatus == PSTATE_ENABLE && (G_pmcrOwner == PMCR_OWNER_HOST || + if (G_pstatesStatus == PSTATE_ACTIVE && (G_pmcrOwner == PMCR_OWNER_HOST || G_pmcrOwner == PMCR_OWNER_CHAR)) { diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c index ebb19334..30f1123a 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_main.c @@ -34,20 +34,20 @@ PgpePstateRecord G_pgpe_pstate_record; EXTERNAL_IRQ_TABLE_START IRQ_HANDLER_DEFAULT //OCCHW_IRQ_DEBUGGER IRQ_HANDLER_DEFAULT //OCCHW_IRQ_TRACE_TRIGGER -IRQ_HANDLER_DEFAULT //OCCHW_IRQ_OCC_ERROR +IRQ_HANDLER(p9_pgpe_irq_handler_occ_error, NULL) //OCCHW_IRQ_OCC_ERROR IRQ_HANDLER_DEFAULT //OCCHW_IRQ_PBA_ERROR IRQ_HANDLER_DEFAULT //OCCHW_IRQ_SRT_ERROR IRQ_HANDLER_DEFAULT //OCCHW_IRQ_GPE0_HALT IRQ_HANDLER_DEFAULT //OCCHW_IRQ_GPE1_HALT IRQ_HANDLER_DEFAULT //OCCHW_IRQ_GPE2_HALT -IRQ_HANDLER_DEFAULT //OCCHW_IRQ_GPE3_HALT +IRQ_HANDLER(p9_pgpe_irq_handler_sgpe_halt, NULL) //OCCHW_IRQ_GPE3_HALT IRQ_HANDLER_DEFAULT //OCCHW_IRQ_PPC405_HALT IRQ_HANDLER_DEFAULT //OCCHW_IRQ_OCB_ERROR IRQ_HANDLER_DEFAULT //OCCHW_IRQ_SPIPSS_ERROR IRQ_HANDLER_DEFAULT //OCCHW_IRQ_CHECK_STOP_PPC405 IRQ_HANDLER_DEFAULT //OCCHW_IRQ_CHECK_STOP_GPE0 IRQ_HANDLER_DEFAULT //OCCHW_IRQ_CHECK_STOP_GPE1 -IRQ_HANDLER_DEFAULT //OCCHW_IRQ_CHECK_STOP_GPE2 +IRQ_HANDLER(p9_pgpe_irq_handler_xstop_gpe2, NULL) //OCCHW_IRQ_CHECK_STOP_GPE2 IRQ_HANDLER_DEFAULT //OCCHW_IRQ_CHECK_STOP_GPE3 IRQ_HANDLER_DEFAULT //OCCHW_IRQ_OCC_MALF_ALERT IRQ_HANDLER_DEFAULT //OCCHW_IRQ_ADU_MALF_ALERT @@ -92,7 +92,7 @@ IRQ_HANDLER_DEFAULT //OCCHW_IRQ_PMC_O2S_1B_ONGOING IRQ_HANDLER_DEFAULT //OCCHW_IRQ_PSSBRIDGE_ONGOING IRQ_HANDLER_DEFAULT //OCCHW_IRQ_IPI0_LO_PRIORITY IRQ_HANDLER_DEFAULT //OCCHW_IRQ_IPI1_LO_PRIORITY -IRQ_HANDLER_DEFAULT //OCCHW_IRQ_IPI2_LO_PRIORITY +IRQ_HANDLER(p9_pgpe_irq_handler_ipi2_lo, NULL) //OCCHW_IRQ_IPI2_LO_PRIORITY IRQ_HANDLER_DEFAULT //OCCHW_IRQ_IPI3_LO_PRIORITY IRQ_HANDLER_DEFAULT //OCCHW_IRQ_IPI4_LO_PRIORITY IRQ_HANDLER_DEFAULT //OCCHW_IRQ_RESERVED_63 @@ -101,16 +101,19 @@ EXTERNAL_IRQ_TABLE_END #define KERNEL_STACK_SIZE 512 #define THREAD_STACK_SIZE 512 +//#define PGPE_THREAD_PRIORITY_SAFE_MODE_AND_PM_SUSPEND 1 #define PGPE_THREAD_PRIORITY_PROCESS_REQUESTS 1 #define PGPE_THREAD_PRIORITY_ACTUATE_PSTATES 2 uint8_t G_kernel_stack[KERNEL_STACK_SIZE]; //Thread Stacks +//uint8_t G_p9_pgpe_thread_safe_mode_and_pm_suspend_stack[THREAD_STACK_SIZE]; uint8_t G_p9_pgpe_thread_process_requests_stack[THREAD_STACK_SIZE]; uint8_t G_p9_pgpe_thread_actuate_pstates_stack[THREAD_STACK_SIZE]; //Thread Control Block +//PkThread G_p9_pgpe_thread_safe_mode_and_pm_suspend; PkThread G_p9_pgpe_thread_process_requests; PkThread G_p9_pgpe_thread_actuate_pstates; @@ -137,6 +140,20 @@ main(int argc, char** argv) asm volatile ("trap"); } + /* + // Initialize the thread control block for G_p9_pgpe_thread_safe_mode_and_pm_suspend + pk_thread_create(&G_p9_pgpe_thread_safe_mode_and_pm_suspend, + (PkThreadRoutine)p9_pgpe_thread_safe_mode_and_pm_suspend, + (void*)NULL, + (PkAddress)G_p9_pgpe_thread_safe_mode_and_pm_suspend_stack, + (size_t)THREAD_STACK_SIZE, + (PkThreadPriority)PGPE_THREAD_PRIORITY_SAFE_MODE_AND_PM_SUSPEND); + + PK_TRACE_BIN("G_p9_pgpe_thread_safe_mode_and_pm_suspend", + &G_p9_pgpe_thread_safe_mode_and_pm_suspend, + sizeof(G_p9_pgpe_thread_safe_mode_and_pm_suspend)); + */ + // Initialize the thread control block for G_p9_pgpe_thread_process_requests pk_thread_create(&G_p9_pgpe_thread_process_requests, (PkThreadRoutine)p9_pgpe_thread_process_requests, @@ -162,13 +179,14 @@ main(int argc, char** argv) sizeof(G_p9_pgpe_thread_actuate_pstates)); // Make G_p9_pgpe_thread pstates_update runnable +// pk_thread_resume(&G_p9_pgpe_thread_safe_mode_and_pm_suspend); pk_thread_resume(&G_p9_pgpe_thread_process_requests); pk_thread_resume(&G_p9_pgpe_thread_actuate_pstates); //Do initialization p9_pgpe_header_init(); - PK_TRACE_DBG("Update PGPE Header with pertinent OCC SRAM information"); + PK_TRACE_DBG("Update PGPE Header with OCC SRAM info"); p9_pgpe_header_fill(); #if USE_BOOT_TEMP @@ -181,7 +199,7 @@ main(int argc, char** argv) p9_pgpe_boot_temp(); //This is just temporary #endif - PK_TRACE_DBG("Initializing from Global Pstate Parameter Block"); + PK_TRACE_DBG("Init from Global Pstate Parameter Block"); p9_pgpe_gppb_init(); #if GEN_PSTATE_TBL @@ -192,10 +210,13 @@ main(int argc, char** argv) PK_TRACE_DBG("Setup FIT(Fixed-Interval Timer)"); p9_pgpe_fit_init(); - PK_TRACE_DBG("Initialize all pstate related data to some default values"); + PK_TRACE_DBG("Init all pstate data to default values"); p9_pgpe_pstate_init(); - PK_TRACE_DBG("Starting PK Threads"); + PK_TRACE_DBG("Setup OCCFIR[OCC_HB Error]"); + p9_pgpe_ocb_hb_error_init(); + + PK_TRACE_DBG("Start PK Threads"); // Start running the highest priority thread. // This function never returns diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c index fd2466c2..ee1cc294 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.c @@ -34,23 +34,24 @@ #include "ipc_messages.h" #include "p9_pgpe_header.h" -#if PK_TRACE_PSTATE_ENABLE_ - #define PK_TRACE_PSTATE(...) PKTRACE(__VA_ARGS__) -#else - #define PK_TRACE_PSTATE(...) -#endif - +// +//#Defines +// +#define GPE_BUFFER(declaration) \ + declaration __attribute__ ((__aligned__(8))) __attribute__ ((section (".noncacheable"))) // //Global External Data // extern PgpeHeader_t* G_pgpe_header_data; extern GlobalPstateParmBlock* G_gppb; +extern uint32_t G_ext_vrm_inc_rate_mult_usperus; +extern uint32_t G_ext_vrm_dec_rate_mult_usperus; // //Global Data // -uint8_t G_safeModeEnabled; //safe mode enabled/disabled +//uint8_t G_safeModeEnabled; //safe mode enabled/disabled uint32_t G_pstatesStatus; uint8_t G_pmcrOwner; uint8_t G_wofEnabled; //wof enable/disable @@ -67,24 +68,27 @@ uint8_t G_quadPSCurr[MAX_QUADS]; //target Pstate per quad uint8_t G_globalPSCurr; //target global Pstate uint8_t G_quadPSNext[MAX_QUADS]; //target Pstate per quad uint8_t G_globalPSNext; +uint8_t G_safe_pstate; uint32_t G_eVidCurr, G_eVidNext; VFRT_Hcode_t* G_vfrt_ptr; quad_state0_t* G_quadState0; quad_state1_t* G_quadState1; requested_active_quads_t* G_reqActQuads; - -#define GPE_BUFFER(declaration) \ - declaration __attribute__ ((__aligned__(8))) __attribute__ ((section (".noncacheable"))) - GPE_BUFFER(ipc_async_cmd_t G_ipc_msg_pgpe_sgpe); GPE_BUFFER(ipcmsg_p2s_ctrl_stop_updates_t G_sgpe_control_updt); +GPE_BUFFER(ipcmsg_s2p_suspend_pstate_t G_sgpe_suspend_stop); +//Local Functions +inline void p9_pgpe_pstate_freq_updt(uint32_t activeCores); +void p9_pgpe_suspend_stop_callback(ipc_msg_t* msg, void* arg); +void p9_pgpe_wait_cme_db_ack(uint8_t msg_id, uint32_t activeCores); // //Data passing between IPC interrupt and threads // ipc_req_t G_ipc_pend_tbl[MAX_IPC_PEND_TBL_ENTRIES]; uint32_t G_already_sem_posted; +uint32_t G_process_pm_suspend; // @@ -94,8 +98,9 @@ void p9_pgpe_pstate_init() { uint32_t q; - G_safeModeEnabled = 0; - G_pstatesStatus = PSTATE_DISABLE; + G_process_pm_suspend = 0; +// G_safeModeEnabled = 0; + G_pstatesStatus = PSTATE_INIT; G_wofEnabled = 0; G_wofPending = 0; @@ -116,10 +121,17 @@ void p9_pgpe_pstate_init() G_quadState0 = (quad_state0_t*)G_pgpe_header_data->g_quad_status_addr; G_quadState1 = (quad_state1_t*)(G_pgpe_header_data->g_quad_status_addr + 2); G_reqActQuads = (requested_active_quads_t*)(G_pgpe_header_data->g_req_active_quad_addr); + G_safe_pstate = (G_gppb->reference_frequency_khz - G_gppb->safe_frequency_khz + + (G_gppb->frequency_step_khz - 1)) / G_gppb->frequency_step_khz; +#if OVERRIDE_PSAFE_PSTATE == 1 + G_safe_pstate = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][NOMINAL].pstate; +#endif + + PK_TRACE_INF("PS: G_safe_pstate=0x%x", G_safe_pstate); } // -//p9_pgpe_pstate_update_ +//p9_pgpe_pstate_update // void p9_pgpe_pstate_update(uint8_t* s) { @@ -142,7 +154,7 @@ void p9_pgpe_pstate_update(uint8_t* s) // void p9_pgpe_pstate_do_auction(uint8_t quadAuctionRequest) { - PK_TRACE_PSTATE("AUCT: Enter"); + PK_TRACE_INF("AUCT: Enter"); //Get active cores and quads uint32_t q, c; uint32_t activeCores = G_quadState0->fields.active_cores; @@ -176,7 +188,7 @@ void p9_pgpe_pstate_do_auction(uint8_t quadAuctionRequest) G_quadPSComputed[q] = 0xFF; } - PK_TRACE_PSTATE("AUCTION: G_quadPSComputed: 0x%x", G_quadPSComputed[q]); + PK_TRACE_INF("AUCTION: G_quadPSComputed: 0x%x", G_quadPSComputed[q]); } //Global PState Auction @@ -194,7 +206,7 @@ void p9_pgpe_pstate_do_auction(uint8_t quadAuctionRequest) } PK_TRACE_INF("AUCT glbPSCmpted: 0x%x", G_globalPSComputed); - PK_TRACE_PSTATE("AUCT: Exit"); + PK_TRACE_INF("AUCT: Exit"); } // @@ -202,17 +214,19 @@ void p9_pgpe_pstate_do_auction(uint8_t quadAuctionRequest) // void p9_pgpe_pstate_apply_clips() { - PK_TRACE_PSTATE("APCLP: Enter"); + PK_TRACE_INF("APCLP: Enter"); uint32_t q; uint32_t activeQuads = G_reqActQuads->fields.requested_active_quads; //Apply clips to quad computed - PK_TRACE_PSTATE("APCLP: 0x%x", activeQuads); + PK_TRACE_INF("APCLP: 0x%x", activeQuads); for (q = 0; q < MAX_QUADS; q++) { uint8_t maxPS = G_psClipMax[q]; + G_quadPSTarget[q] = G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][POWERSAVE].pstate; + if (activeQuads & (QUAD0_BIT_MASK >> q)) { @@ -260,7 +274,7 @@ void p9_pgpe_pstate_apply_clips() } PK_TRACE_INF("APCLP: glbPSTgt: 0x%x", G_globalPSTarget); - PK_TRACE_PSTATE("APCLP: Exit"); + PK_TRACE_INF("APCLP: Exit"); } // @@ -279,3 +293,479 @@ void p9_pgpe_pstate_ipc_rsp_cb_sem_post(ipc_msg_t* msg, void* arg) { pk_semaphore_post((PkSemaphore*)arg); } + +// +//p9_pgpe_pstate_suspend +// +void p9_pgpe_pstate_pm_complex_suspend() +{ + PK_TRACE_INF("PS:PM Susp Enter"); + + if (G_pstatesStatus == PSTATE_ACTIVE) + { + G_pstatesStatus = PSTATE_PM_SUSPEND_PENDING; + p9_pgpe_pstate_apply_safe_clips(); + } + else if (G_pstatesStatus == PSTATE_STOPPED) + { + //todo Set FIR[Bit] need to determine which one + PK_TRACE_INF("PS:PM Susp in PSTATE_STOPPED(Halting)"); + pk_halt(); + } + else if (G_pstatesStatus == PSTATE_INIT) + { + G_pstatesStatus = PSTATE_PM_SUSPEND_PENDING; + p9_pgpe_pstate_send_suspend_stop(); + } + + PK_TRACE_INF("PS:PM Susp Exit"); +} + +// +//p9_pgpe_pstate_send_suspend_stop +// +void p9_pgpe_pstate_send_suspend_stop() +{ +#if SGPE_IPC_ENABLED == 1 + int rc; + G_sgpe_suspend_stop.fields.msg_num = MSGID_PGPE_SGPE_SUSPEND_STOP; + G_sgpe_suspend_stop.fields.return_code = 0x0; + G_ipc_msg_pgpe_sgpe.cmd_data = &G_sgpe_suspend_stop; + ipc_init_msg(&G_ipc_msg_pgpe_sgpe.cmd, + MSGID_PGPE_SGPE_SUSPEND_STOP, + p9_pgpe_suspend_stop_callback, + (void*)NULL); + + //send the command + PK_TRACE_INF("PS: Susp Stop Sent"); + rc = ipc_send_cmd(&G_ipc_msg_pgpe_sgpe.cmd); + + if(rc) + { + pk_halt(); + } + +#else + p9_pgpe_suspend_stop_callback(NULL, NULL); +#endif +} + +// +//p9_pgpe_suspend_stop_callback +// +void p9_pgpe_suspend_stop_callback(ipc_msg_t* msg, void* arg) +{ + PK_TRACE_INF("PS: Susp Stop Cb"); + uint32_t occScr2 = in32(OCB_OCCS2); + occScr2 |= BIT32(PM_COMPLEX_SUSPENDED); + G_pstatesStatus = PSTATE_PM_SUSPENDED; + out32(OCB_OCCS2, occScr2); +} + + + +// +//p9_pgpe_pstate_safe_mode() +// +void p9_pgpe_pstate_safe_mode() +{ + PK_TRACE_INF("PS:Safe Mode Enter"); + + if (G_pstatesStatus == PSTATE_ACTIVE) + { + G_pstatesStatus = PSTATE_SAFE_MODE; + p9_pgpe_pstate_apply_safe_clips(); + } + else if (G_pstatesStatus == PSTATE_STOPPED) + { + //todo Set FIR[Bit] need to determine which one + PK_TRACE_INF("PS:PM Susp in PSTATE_STOPPED(Halting)"); + pk_halt(); + } + else if (G_pstatesStatus == PSTATE_INIT) + { + G_pstatesStatus = PSTATE_SAFE_MODE; + } + + PK_TRACE_INF("PS:Safe Mode Exit"); +} + +// +// +// +void p9_pgpe_pstate_apply_safe_clips() +{ + PK_TRACE_INF("PS: Apply Safe Enter"); + int q; + + //Set clips to safe pstate + for (q = 0; q < MAX_QUADS; q++) + { + G_psClipMax[q] = G_safe_pstate; + G_psClipMin[q] = G_safe_pstate; + } + + //Update clips + p9_pgpe_pstate_apply_clips(); + + PK_TRACE_INF("PS: Apply Safe Exit"); +} + +// +//p9_pgpe_pstate_at_target +// +int32_t p9_pgpe_pstate_at_target() +{ + if( G_globalPSCurr != G_globalPSTarget || + G_quadPSCurr[0] ^ G_quadPSTarget[0] || + G_quadPSCurr[1] ^ G_quadPSTarget[1] || + G_quadPSCurr[2] ^ G_quadPSTarget[2] || + G_quadPSCurr[3] ^ G_quadPSTarget[3] || + G_quadPSCurr[4] ^ G_quadPSTarget[4] || + G_quadPSCurr[5] ^ G_quadPSTarget[5] ) + { + return 0; + } + else + { + return 1; + } +} + +// +//p9_pgpe_pstate_do_step +// +void p9_pgpe_pstate_do_step() +{ + PkMachineContext ctx; + //We don't want actuate_step to interrupted by any external interrupt. + //However, we still want FIT Timer to be active, so we mask of all interrupts + //in the OIMR through UIH(by setting UIH priority lvl = 0) + pk_critical_section_enter(&ctx); + pk_irq_save_and_set_mask(0); + pk_critical_section_exit(&ctx); + + //Do one actuate step + PK_TRACE_DBG("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x", G_globalPSTarget, G_globalPSCurr); + + PK_TRACE_DBG("ACT_TH: Step Entry"); + PK_TRACE_DBG("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x", G_globalPSTarget, G_globalPSCurr); + PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[0], G_quadPSCurr[0]); + PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[1], G_quadPSCurr[1]); + PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[2], G_quadPSCurr[2]); + PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[3], G_quadPSCurr[3]); + PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[4], G_quadPSCurr[4]); + PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[5], G_quadPSCurr[5]); + uint32_t q; + ocb_qcsr_t qcsr; + qcsr.value = in32(OCB_QCSR); + uint32_t active_conf_cores = 0; + uint32_t targetEVid = p9_pgpe_gppb_intp_vdd_from_ps(G_globalPSTarget, VPD_PT_SET_BIASED_SYSP, VPD_SLOPES_BIASED); + + //Determine active and configured cores + for (q = 0; q < MAX_QUADS; q++) + { + if(G_reqActQuads->fields.requested_active_quads & (0x80 >> q)) + { + if (qcsr.fields.ex_config & (0x800 >> (q << 1))) + { + active_conf_cores |= (0xC0000000 >> (q << 2)); + } + + if (qcsr.fields.ex_config & (0x400 >> (q << 1))) + { + active_conf_cores |= (0x30000000 >> (q << 2)); + } + } + + PK_TRACE_INF("ACT_TH: act_c=0x%x", active_conf_cores); + } + + //Higher number PState + if (((int16_t)(G_globalPSTarget) - (int16_t)(G_globalPSCurr)) > 0) + { + if ((G_eVidCurr - targetEVid ) <= G_gppb->ext_vrm_step_size_mv) + { + G_eVidNext = targetEVid; + G_globalPSNext = G_globalPSTarget; + + for (q = 0; q < MAX_QUADS; q++) + { + G_quadPSNext[q] = G_quadPSTarget[q]; + } + } + else + { + G_eVidNext = G_eVidCurr - G_gppb->ext_vrm_step_size_mv; + G_globalPSNext = p9_pgpe_gppb_intp_ps_from_ext_vdd(G_eVidNext); + + for (q = 0; q < MAX_QUADS; q++) + { + if (G_quadPSTarget[q] > G_globalPSNext) //Keep localPS under GlobalPS + { + G_quadPSNext[q] = G_globalPSNext; + } + else + { + G_quadPSNext[q] = G_quadPSTarget[q]; + } + } + } + + p9_pgpe_pstate_freq_updt(active_conf_cores); + p9_pgpe_pstate_updt_ext_volt(targetEVid); + } + //Lower number PState + else if (((int16_t)(G_globalPSTarget) - (int16_t)(G_globalPSCurr)) < 0) + { + if ((targetEVid - G_eVidCurr) <= G_gppb->ext_vrm_step_size_mv) + { + G_eVidNext = targetEVid; + G_globalPSNext = G_globalPSTarget; + + for (q = 0; q < MAX_QUADS; q++) + { + G_quadPSNext[q] = G_quadPSTarget[q]; + } + } + else + { + G_eVidNext = G_eVidCurr + G_gppb->ext_vrm_step_size_mv; + G_globalPSNext = p9_pgpe_gppb_intp_ps_from_ext_vdd(G_eVidNext); + + for (q = 0; q < MAX_QUADS; q++) + { + if (G_quadPSTarget[q] < G_globalPSNext) //Keep localPS under GlobalPS + { + G_quadPSNext[q] = G_globalPSNext; + } + else + { + G_quadPSNext[q] = G_quadPSTarget[q]; + } + } + } + + p9_pgpe_pstate_updt_ext_volt(targetEVid); + p9_pgpe_pstate_freq_updt(active_conf_cores); + } + else + { + for (q = 0; q < MAX_QUADS; q++) + { + G_quadPSNext[q] = G_quadPSTarget[q]; + } + + p9_pgpe_pstate_freq_updt(active_conf_cores); + } + + //Update current + G_globalPSCurr = G_globalPSNext; + + for (q = 0; q < MAX_QUADS; q++) + { + if(G_reqActQuads->fields.requested_active_quads & (0x80 >> q) && + (qcsr.fields.ex_config & (0xC00 >> 2 * q))) + { + G_quadPSCurr[q] = G_quadPSNext[q]; + } + } + + //Update Shared SRAM + G_quadState0->fields.quad0_pstate = G_quadPSCurr[0]; + G_quadState0->fields.quad1_pstate = G_quadPSCurr[1]; + G_quadState0->fields.quad2_pstate = G_quadPSCurr[2]; + G_quadState0->fields.quad3_pstate = G_quadPSCurr[3]; + G_quadState1->fields.quad4_pstate = G_quadPSCurr[4]; + G_quadState1->fields.quad5_pstate = G_quadPSCurr[5]; + + PK_TRACE_DBG("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x", G_globalPSTarget, G_globalPSCurr); + PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[0], G_quadPSCurr[0]); + PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[1], G_quadPSCurr[1]); + PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[2], G_quadPSCurr[2]); + PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[3], G_quadPSCurr[3]); + PK_TRACE_DBG("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[4], G_quadPSCurr[4]); + PK_TRACE_DBG("ACT_TH: Step Exit"); + + + //Now, PGPE is done with actuate step, let's + //restore the interrupts in OIMR through UIH + pk_irq_vec_restore(&ctx); +} + +// +//p9_pgpe_pstate__updt_ext_volt +// +//Update External VRM to G_eVidNext +void p9_pgpe_pstate_updt_ext_volt(uint32_t tgtEVid) +{ +#if !EPM_P9_TUNING + uint32_t delay_us = 0; + + //Decreasing + if (G_eVidNext < G_eVidCurr) + { + delay_us = (G_eVidCurr - G_eVidNext) * + G_ext_vrm_dec_rate_mult_usperus; + } + //Increasing + else if(G_eVidNext > G_eVidCurr) + { + delay_us = (G_eVidNext - G_eVidCurr) * + G_ext_vrm_inc_rate_mult_usperus; + } + +#endif + + //Update external voltage + external_voltage_control_write(G_eVidNext); + +#if !EPM_P9_TUNING + + //Delay for delay_us + if (delay_us > 0) + { + pk_sleep(PK_MICROSECONDS((delay_us))); + } + + if(G_eVidNext == tgtEVid) + { + pk_sleep(PK_MICROSECONDS((G_gppb->ext_vrm_stabilization_time_us))); + } + +#endif + + G_eVidCurr = G_eVidNext; +} + +// +//Frequency Update +// +//Sends a DB0 to all active CMEs, so that Quad Managers(CMEs) update DPLL +inline void p9_pgpe_pstate_freq_updt(uint32_t activeCores) +{ + PK_TRACE_INF("ACT_TH: FreqUpdt Enter"); + PK_TRACE_INF("ACT_TH: act_cores=0x%x", activeCores); + pgpe_db0_glb_bcast_t db0; + db0.value = 0; + db0.fields.msg_id = MSGID_DB0_GLOBAL_ACTUAL_BROADCAST; + db0.fields.global_actual = G_globalPSNext; + db0.fields.quad0_ps = G_quadPSNext[0]; + db0.fields.quad1_ps = G_quadPSNext[1]; + db0.fields.quad2_ps = G_quadPSNext[2]; + db0.fields.quad3_ps = G_quadPSNext[3]; + db0.fields.quad4_ps = G_quadPSNext[4]; + db0.fields.quad5_ps = G_quadPSNext[5]; + p9_dd1_db_multicast_wr(PCB_MUTLICAST_GRP1 | CPPM_CMEDB0, db0.value, activeCores); + PK_TRACE_INF("ACT_TH: MCAST DB0"); + p9_pgpe_wait_cme_db_ack(MSGID_DB0_GLOBAL_ACTUAL_BROADCAST, activeCores);//Wait for ACKs from all CMEs + PK_TRACE_INF("ACT_TH: Freq Updt Exit"); +} + + +// +//Wait for CME to ack DB0 +// +void p9_pgpe_wait_cme_db_ack(uint8_t msg_id, uint32_t active_conf_cores) +{ + int32_t c, q; + uint32_t opit4pr; + uint8_t pendingAcks = 0; + uint8_t quadPendDBAck[MAX_QUADS]; + + for (q = 0; q < MAX_QUADS; q++) + { + if (active_conf_cores & (0xF0000000 >> (q << 2))) + { + quadPendDBAck[q] = 1; + } + else + { + quadPendDBAck[q] = 0; + } + } + + //Wait for all the acks to come + pendingAcks = 1; + + while (pendingAcks) + { + //Process acks + opit4pr = in32(OCB_OPIT4PRA); + + for (c = 0; c < MAX_CORES; c++) + { + if (opit4pr & (CCSR_CORE_CONFIG_MASK >> c)) + { + if (quadPendDBAck[QUAD_FROM_CORE(c)]) + { + quadPendDBAck[QUAD_FROM_CORE(c)] = 0; + out32(OCB_OPIT4PRA_CLR, CCSR_CORE_CONFIG_MASK >> c); //Clear out pending bits + PK_TRACE_INF("ACT_TH: Ack C%02u", c); + } + else + { + PK_TRACE_INF("ACT_TH: BadAck C%02u", c); + pk_halt(); + } + } + } + + //Check if any pending left + pendingAcks = 0; + + for (q = 0; q < MAX_QUADS; q++) + { + if (quadPendDBAck[q]) + { + pendingAcks = 1; + } + } + } +} + + +void p9_pgpe_pstate_set_pmcr_owner(uint32_t owner) +{ + int q = 0; + ocb_qcsr_t qcsr; + qcsr.value = in32(OCB_QCSR); +//Write to LMCR register in SIMICS results in error +//So, adding a build flag for SIMICS. +//For SIMICS, LMCR should be set through command line +#if !SIMICS_TUNING + + for (q = 0; q < MAX_QUADS; q++) + { + if(G_reqActQuads->fields.requested_active_quads & (0x80 >> q)) + { + //CME0 within this quad + if (qcsr.fields.ex_config & (0x800 >> 2 * q)) + { + if (owner == PMCR_OWNER_HOST) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_CLR, q, 0), BIT64(0)); + } + else if (owner == PMCR_OWNER_OCC) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 0), BIT64(0)); + } + } + + //CME1 within this quad + if (qcsr.fields.ex_config & (0x400 >> 2 * q)) + { + if (owner == PMCR_OWNER_HOST) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_CLR, q, 1), BIT64(0)); + } + else if (owner == PMCR_OWNER_OCC) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 1), BIT64(0)); + } + } + } + } + +#endif +} diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.h index 17c599af..29790422 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.h +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_pstate.h @@ -53,10 +53,14 @@ enum PSTATE_STATUS { - PSTATE_DISABLE = 0, - PSTATE_START_PENDING = 1, - PSTATE_SUSPENDED = 3, - PSTATE_ENABLE = 4 + PSTATE_INIT = 0, + PSTATE_START_PENDING = 1, + PSTATE_ACTIVE = 2, + PSTATE_STOPPED = 3, + PSTATE_SUSPENDED = 4, + PSTATE_PM_SUSPEND_PENDING = 5, + PSTATE_PM_SUSPENDED = 6, + PSTATE_SAFE_MODE = 7 }; // @@ -78,5 +82,14 @@ void p9_pgpe_pstate_do_auction(uint8_t quadAuctionRequest); void p9_pgpe_pstate_calc_wof(); void p9_pgpe_pstate_apply_clips(); void p9_pgpe_pstate_ipc_rsp_cb_sem_post(ipc_msg_t* msg, void* arg); +void p9_pgpe_pstate_pm_complex_suspend(); +void p9_pgpe_pstate_send_suspend_stop(); +void p9_pgpe_pstate_safe_mode(); +void p9_pgpe_pstate_apply_safe_clips(); +int32_t p9_pgpe_pstate_at_target(); +void p9_pgpe_pstate_do_step(); +void p9_pgpe_pstate_set_pmcr_owner(uint32_t owner); +void p9_pgpe_wait_cme_db_ack(uint8_t msg_id, uint32_t activeCores); +void p9_pgpe_pstate_updt_ext_volt(uint32_t tgtEVid); #endif // diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c index 26760412..05a80187 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_actuate_pstates.c @@ -34,22 +34,9 @@ #include "p9_dd1_doorbell_wr.h" #include "avs_driver.h" -#if PK_TRACE_ACT_TH_ENABLE_ - #define PK_TRACE_ACT_TH(...) PKTRACE(__VA_ARGS__) -#else - #define PK_TRACE_ACT_TH(...) -#endif - -//Constants, #defines -#define CCSR_CORE_CONFIG_MASK 0x80000000 - //Local Function Prototypes void p9_pgpe_thread_actuate_start(); void p9_pgpe_thread_actuate_stop(); -void p9_pgpe_wait_cme_db_ack(uint8_t msg_id, uint32_t activeCores); -void p9_pgpe_thread_actuate_updt_ext_volt(uint32_t tgtEVid); -void p9_pgpe_thread_actuate_freq_updt(uint32_t activeCores); -void p9_pgpe_thread_actuate_do_step(); void p9_pgpe_thread_actuate_init_actual_quad(); // @@ -71,9 +58,6 @@ extern uint8_t G_psClipMax[MAX_QUADS], extern uint8_t G_pmcrOwner; extern ipc_req_t G_ipc_pend_tbl[MAX_IPC_PEND_TBL_ENTRIES]; extern uint8_t G_pstate0_dpll_value; -extern uint32_t G_ext_vrm_inc_rate_mult_usperus; -extern uint32_t G_ext_vrm_dec_rate_mult_usperus; -extern VpdOperatingPoint G_operating_points[NUM_VPD_PTS_SET][VPD_PV_POINTS]; extern quad_state0_t* G_quadState0; extern quad_state1_t* G_quadState1; extern requested_active_quads_t* G_reqActQuads; @@ -86,7 +70,7 @@ GPE_BUFFER(extern ipcmsg_p2s_ctrl_stop_updates_t G_sgpe_control_updt); // void p9_pgpe_thread_actuate_pstates(void* arg) { - PK_TRACE_ACT_TH("ACT_TH: Started"); + PK_TRACE_DBG("ACT_TH: Started"); uint32_t inRange, q = 0; PkMachineContext ctx; uint32_t restore_irq = 0; @@ -96,7 +80,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg) pk_semaphore_create(&(G_pgpe_pstate_record.sem_actuate), 0, 1); pk_semaphore_create(&(G_pgpe_pstate_record.sem_sgpe_wait), 0, 1); - PK_TRACE_ACT_TH("ACT_TH: Inited"); + PK_TRACE_DBG("ACT_TH: Inited"); //Initialize Shared SRAM to a known state p9_pgpe_thread_actuate_init_actual_quad(); @@ -104,16 +88,13 @@ void p9_pgpe_thread_actuate_pstates(void* arg) // Set OCC Scratch2[PGPE_ACTIVE] uint32_t occScr2 = in32(OCB_OCCS2); occScr2 |= BIT32(PGPE_ACTIVE); -#if PGPE_UNIT_TEST - occScr2 |= BIT32(30); -#endif PK_TRACE_INF("Setting PGPE_ACTIVE in OCC SCRATCH2 addr %X = %X", OCB_OCCS2, occScr2); out32(OCB_OCCS2, occScr2); //Thread Loop while(1) { - PK_TRACE_ACT_TH("ACT_TH: Pend"); + PK_TRACE_DBG("ACT_TH: Pend"); pk_semaphore_pend(&(G_pgpe_pstate_record.sem_actuate), PK_WAIT_FOREVER); wrteei(1); @@ -121,38 +102,18 @@ void p9_pgpe_thread_actuate_pstates(void* arg) p9_pgpe_thread_actuate_start(); //Loop while Pstate is enabled - PK_TRACE_ACT_TH("ACT_TH: Status=%d", G_pstatesStatus); + PK_TRACE_DBG("ACT_TH: Status=%d", G_pstatesStatus); restore_irq = 0; - while(G_pstatesStatus == PSTATE_ENABLE || G_pstatesStatus == PSTATE_SUSPENDED) + while(G_pstatesStatus == PSTATE_ACTIVE || G_pstatesStatus == PSTATE_SUSPENDED) { if(G_pstatesStatus != PSTATE_SUSPENDED) { //Actuate step(if needed) - if( G_globalPSCurr != G_globalPSTarget || - G_quadPSCurr[0] ^ G_quadPSTarget[0] || - G_quadPSCurr[1] ^ G_quadPSTarget[1] || - G_quadPSCurr[2] ^ G_quadPSTarget[2] || - G_quadPSCurr[3] ^ G_quadPSTarget[3] || - G_quadPSCurr[4] ^ G_quadPSTarget[4] || - G_quadPSCurr[5] ^ G_quadPSTarget[5] ) + if(p9_pgpe_pstate_at_target() == 0) { - //We don't want actuate_step to interrupted by any external interrupt. - //However, we still want FIT Timer to be active, so we mask of all interrupts - //in the OIMR through UIH(by setting UIH priority lvl = 0) - pk_critical_section_enter(&ctx); - pk_irq_save_and_set_mask(0); - pk_critical_section_exit(&ctx); - - //Do one actuate step - PK_TRACE_ACT_TH("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x", G_globalPSTarget, G_globalPSCurr); - p9_pgpe_thread_actuate_do_step(); - - - //Now, PGPE is done with actuate step, let's - //restore the interrupts in OIMR through UIH - pk_irq_vec_restore(&ctx); + p9_pgpe_pstate_do_step(); } //Check if CLIP_UPDT is pending and Pstates are clipped @@ -168,7 +129,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg) if (G_quadPSCurr[q] > G_psClipMax[q] || G_quadPSCurr[q] < G_psClipMin[q]) { - PK_TRACE_ACT_TH("ACT_TH:!Clipped[%d) qPSCur: 0x%x", q, G_quadPSCurr[q]); + PK_TRACE_DBG("ACT_TH:!Clipped[%d) qPSCur: 0x%x", q, G_quadPSCurr[q]); inRange = 0; } } @@ -190,16 +151,39 @@ void p9_pgpe_thread_actuate_pstates(void* arg) //Check if IPC should be opened again if (restore_irq == 1) { - PK_TRACE_ACT_TH("ACT_TH: IRQ Restore"); + PK_TRACE_DBG("ACT_TH: IRQ Restore"); restore_irq = 0; pk_irq_vec_restore(&ctx); } } } //while loop - //Pstates Stop - //This call will unmask IPC and block on SGPE ACK - p9_pgpe_thread_actuate_stop(); + if (G_pstatesStatus == PSTATE_STOPPED) + { + //Pstates Stop + //If we entered SAFE_MODE already, then do STOP protocol + //This call will unmask IPC and block on SGPE ACK + p9_pgpe_thread_actuate_stop(); + } + else if (G_pstatesStatus == PSTATE_PM_SUSPEND_PENDING || G_pstatesStatus == PSTATE_SAFE_MODE) + { + //Actuate to PSAFE Pstate + while (p9_pgpe_pstate_at_target() == 0) + { + p9_pgpe_pstate_do_step(); + } + + if (G_pstatesStatus == PSTATE_PM_SUSPEND_PENDING) + { + p9_pgpe_pstate_send_suspend_stop(); //Notify SGPE} + } + else if (G_pstatesStatus == PSTATE_SAFE_MODE) + { + uint32_t occScr2 = in32(OCB_OCCS2); + occScr2 |= BIT32(PGPE_SAFE_MODE_ACTIVE); + out32(OCB_OCCS2, occScr2); + } + } }//Thread loop } @@ -208,7 +192,7 @@ void p9_pgpe_thread_actuate_pstates(void* arg) // void p9_pgpe_thread_actuate_start() { - PK_TRACE_ACT_TH("ACT_TH: Start Enter"); + PK_TRACE_DBG("ACT_TH: Start Enter"); ocb_ccsr_t ccsr; ccsr.value = in32(OCB_CCSR); ocb_qcsr_t qcsr; @@ -235,7 +219,7 @@ void p9_pgpe_thread_actuate_start() (void*)&G_pgpe_pstate_record.sem_sgpe_wait); //send the command - PK_TRACE_ACT_TH("ACT_TH: CtrlStopUpdt Sent"); + PK_TRACE_DBG("ACT_TH: CtrlStopUpdt Sent"); rc = ipc_send_cmd(&G_ipc_msg_pgpe_sgpe.cmd); if(rc) @@ -247,20 +231,22 @@ void p9_pgpe_thread_actuate_start() pk_irq_vec_restore(&ctx); pk_semaphore_pend(&(G_pgpe_pstate_record.sem_sgpe_wait), PK_WAIT_FOREVER); - PK_TRACE_ACT_TH("ACT_TH: CtrlStopUpdt Resp"); + PK_TRACE_DBG("ACT_TH: CtrlStopUpdt Resp"); if (G_sgpe_control_updt.fields.return_code == SGPE_PGPE_IPC_RC_SUCCESS) { //Update Shared Memory Region + PK_TRACE_DBG("ACT_TH: ctrl_updt=0x%08x%08x", G_sgpe_control_updt.value >> 32, G_sgpe_control_updt.value); G_quadState0->fields.active_cores = (ccsr.value >> 16); G_quadState1->fields.active_cores = ccsr.value & 0xFF00 ; G_reqActQuads->fields.requested_active_quads = G_sgpe_control_updt.fields.active_quads << 2; - PK_TRACE_ACT_TH("ACT_TH: core_pwr_st0=0x%x", (uint32_t)G_quadState0->fields.active_cores); - PK_TRACE_ACT_TH("ACT_TH: core_pwr_st1=0x%x", (uint32_t)G_quadState1->fields.active_cores); - PK_TRACE_ACT_TH("ACT_TH: req_active_quad=0x%x", (uint32_t)G_reqActQuads->fields.requested_active_quads); + PK_TRACE_DBG("ACT_TH: core_pwr_st0=0x%x", (uint32_t)G_quadState0->fields.active_cores); + PK_TRACE_DBG("ACT_TH: core_pwr_st1=0x%x", (uint32_t)G_quadState1->fields.active_cores); + PK_TRACE_DBG("ACT_TH: req_active_quad=0x%x", (uint32_t)G_reqActQuads->fields.requested_active_quads); } else { + PK_TRACE_DBG("ACT_TH: SGPE Ctrl Stop rc=0x%x", (uint32_t)G_sgpe_control_updt.fields.return_code); pk_halt(); } @@ -279,7 +265,7 @@ void p9_pgpe_thread_actuate_start() #endif //_SGPE_IPC_ENABLED_ - PK_TRACE_ACT_TH("ACT_TH: Shr Mem Updt"); + PK_TRACE_DBG("ACT_TH: Shr Mem Updt"); //2. Read DPLLs lowestDpll = 0xFFF; @@ -295,7 +281,7 @@ void p9_pgpe_thread_actuate_start() GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(QPPM_DPLL_STAT, q), dpll.value); #else dpll.fields.freqout = (G_pstate0_dpll_value - - G_operating_points[VPD_PT_SET_BIASED_SYSP][NOMINAL].pstate); + - G_gppb->operating_points_set[VPD_PT_SET_BIASED_SYSP][NOMINAL].pstate); #endif if ((dpll.fields.freqout) < lowestDpll ) @@ -303,7 +289,7 @@ void p9_pgpe_thread_actuate_start() lowestDpll = dpll.fields.freqout; } - PK_TRACE_ACT_TH("ACT_TH: Quad[%d]: DPLL=0x%x", q, (dpll.fields.freqout)); + PK_TRACE_DBG("ACT_TH: Quad[%d]: DPLL=0x%x", q, (dpll.fields.freqout)); active_conf_cores |= (0xF0000000 >> q * 4); } } @@ -346,27 +332,27 @@ void p9_pgpe_thread_actuate_start() //4. Determine PMCR Owner //We save it off so that CMEs that are currently in STOP11 //can be told upon STOP11 Exit - PK_TRACE_ACT_TH("ACT_TH: g_oimr_override:0x%llx", g_oimr_override); + PK_TRACE_DBG("ACT_TH: g_oimr_override:0x%llx", g_oimr_override); ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)G_ipc_pend_tbl[IPC_PEND_PSTATE_START].cmd; ipcmsg_start_stop_t* args = (ipcmsg_start_stop_t*)async_cmd->cmd_data; if (args->pmcr_owner == PMCR_OWNER_HOST) { - PK_TRACE_ACT_TH("ACT_TH: OWNER_HOST"); + PK_TRACE_DBG("ACT_TH: OWNER_HOST"); G_pmcrOwner = PMCR_OWNER_HOST; g_oimr_override &= ~(BIT64(46)); out32(OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1 } else if (args->pmcr_owner == PMCR_OWNER_OCC) { - PK_TRACE_ACT_TH("ACT_TH: OWNER_OCC"); + PK_TRACE_DBG("ACT_TH: OWNER_OCC"); G_pmcrOwner = PMCR_OWNER_OCC; g_oimr_override |= BIT64(46); out32(OCB_OIMR1_OR, BIT32(14)); //Disable PCB_INTR_TYPE1 } else if (args->pmcr_owner == PMCR_OWNER_CHAR) { - PK_TRACE_ACT_TH("ACT_TH: OWNER_CHAR"); + PK_TRACE_DBG("ACT_TH: OWNER_CHAR"); G_pmcrOwner = PMCR_OWNER_CHAR; g_oimr_override &= ~(BIT64(46)); out32(OCB_OIMR1_CLR, BIT32(14)); //Enable PCB_INTR_TYPE1 @@ -376,45 +362,49 @@ void p9_pgpe_thread_actuate_start() pk_halt(); } -// PK_TRACE_ACT_TH("ACT_TH: g_oimr_override:0x%llx", g_oimr_override); //Set LMCR for each CME -#if !SIMICS_TUNING - - //8 Byte write to LMCR register in SIMICS results in error - //So, adding a build flag for SIMICS this out. Instead, in SIMICS set this through command line - for (q = 0; q < MAX_QUADS; q++) + if (G_pmcrOwner == PMCR_OWNER_HOST) { - if(G_reqActQuads->fields.requested_active_quads & (0x80 >> q)) + p9_pgpe_pstate_set_pmcr_owner(PMCR_OWNER_HOST); + } + else if (G_pmcrOwner == PMCR_OWNER_OCC) + { + p9_pgpe_pstate_set_pmcr_owner(PMCR_OWNER_OCC); + } + + /* + for (q = 0; q < MAX_QUADS; q++) { - //CME0 within this quad - if (qcsr.fields.ex_config & (0x800 >> 2 * q)) + if(G_reqActQuads->fields.requested_active_quads & (0x80 >> q)) { - if (G_pmcrOwner == PMCR_OWNER_HOST) - { - GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_CLR, q, 0), BIT64(0)); - } - else if (G_pmcrOwner == PMCR_OWNER_OCC) + //CME0 within this quad + if (qcsr.fields.ex_config & (0x800 >> 2 * q)) { - GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 0), BIT64(0)); + if (G_pmcrOwner == PMCR_OWNER_HOST) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_CLR, q, 0), BIT64(0)); + } + else if (G_pmcrOwner == PMCR_OWNER_OCC) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 0), BIT64(0)); + } } - } - //CME1 within this quad - if (qcsr.fields.ex_config & (0x400 >> 2 * q)) - { - if (G_pmcrOwner == PMCR_OWNER_HOST) - { - GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_CLR, q, 1), BIT64(0)); - } - else if (G_pmcrOwner == PMCR_OWNER_OCC) + //CME1 within this quad + if (qcsr.fields.ex_config & (0x400 >> 2 * q)) { - GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 1), BIT64(0)); + if (G_pmcrOwner == PMCR_OWNER_HOST) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_CLR, q, 1), BIT64(0)); + } + else if (G_pmcrOwner == PMCR_OWNER_OCC) + { + GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LMCR_OR, q, 1), BIT64(0)); + } } } } - } - -#endif + */ //4. Set External VRM and Send DB0 to every active CME //\TODO: Need Greg's Response @@ -442,18 +432,18 @@ void p9_pgpe_thread_actuate_start() if (G_eVidCurr > G_eVidNext) { p9_dd1_db_multicast_wr(PCB_MUTLICAST_GRP1 | CPPM_CMEDB0, db0.value, active_conf_cores); - PK_TRACE_ACT_TH("ACT_TH: Send DB0"); + PK_TRACE_DBG("ACT_TH: Send DB0"); p9_pgpe_wait_cme_db_ack(MSGID_DB0_START_PSTATE_BROADCAST, active_conf_cores);//Wait for ACKs from all QuadManagers - PK_TRACE_ACT_TH("ACT_TH: DB0 ACK"); - p9_pgpe_thread_actuate_updt_ext_volt(G_eVidNext); + PK_TRACE_DBG("ACT_TH: DB0 ACK"); + p9_pgpe_pstate_updt_ext_volt(G_eVidNext); } else { - p9_pgpe_thread_actuate_updt_ext_volt(G_eVidNext); + p9_pgpe_pstate_updt_ext_volt(G_eVidNext); p9_dd1_db_multicast_wr(PCB_MUTLICAST_GRP1 | CPPM_CMEDB0, db0.value, active_conf_cores); - PK_TRACE_ACT_TH("ACT_TH: Send DB0"); + PK_TRACE_DBG("ACT_TH: Send DB0"); p9_pgpe_wait_cme_db_ack(MSGID_DB0_START_PSTATE_BROADCAST, active_conf_cores);//Wait for ACKs from all QuadManagers - PK_TRACE_ACT_TH("ACT_TH: DB0 ACK"); + PK_TRACE_DBG("ACT_TH: DB0 ACK"); } G_globalPSCurr = G_globalPSTarget; @@ -474,8 +464,8 @@ void p9_pgpe_thread_actuate_start() //7. Enable PStates - G_pstatesStatus = PSTATE_ENABLE; - PK_TRACE_ACT_TH("ACT_TH: PSTATE_ENABLE"); + G_pstatesStatus = PSTATE_ACTIVE; + PK_TRACE_DBG("ACT_TH: PSTATE_ACTIVE"); //8. Send Pstate Start ACK to OCC args->msg_cb.rc = PGPE_RC_SUCCESS; @@ -485,16 +475,16 @@ void p9_pgpe_thread_actuate_start() if ((G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_CORES_UPDT].pending_processing == 1) || (G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].pending_processing == 1)) { - PK_TRACE_ACT_TH("ACT_TH: Post PROC_TH"); + PK_TRACE_DBG("ACT_TH: Post PROC_TH"); pk_semaphore_post(&G_pgpe_pstate_record.sem_process_req); } else { - PK_TRACE_ACT_TH("ACT_TH: Restoring IRQs"); + PK_TRACE_DBG("ACT_TH: Restoring IRQs"); pk_irq_vec_restore(&ctx); } - PK_TRACE_ACT_TH("ACT_TH: Start Exit"); + PK_TRACE_DBG("ACT_TH: Start Exit"); } // @@ -502,9 +492,9 @@ void p9_pgpe_thread_actuate_start() // void p9_pgpe_thread_actuate_stop() { - PK_TRACE_ACT_TH("ACT_TH: Stop Enter"); - PK_TRACE_ACT_TH("ACT_TH: GlbPSCurr:0x%x", G_globalPSCurr ); - PK_TRACE_ACT_TH("ACT_TH: GlblPsTgt:0x%x", G_globalPSTarget); + PK_TRACE_DBG("ACT_TH: Stop Enter"); + PK_TRACE_DBG("ACT_TH: GlbPSCurr:0x%x", G_globalPSCurr ); + PK_TRACE_DBG("ACT_TH: GlblPsTgt:0x%x", G_globalPSTarget); uint32_t q; PkMachineContext ctx; uint32_t active_conf_cores = 0; @@ -548,7 +538,7 @@ void p9_pgpe_thread_actuate_stop() (void*)&G_pgpe_pstate_record.sem_sgpe_wait); //send the command - PK_TRACE_ACT_TH("ACT_TH: CtrlStopUpdt Sent"); + PK_TRACE_DBG("ACT_TH: CtrlStopUpdt Sent"); rc = ipc_send_cmd(&G_ipc_msg_pgpe_sgpe.cmd); if(rc) @@ -560,7 +550,7 @@ void p9_pgpe_thread_actuate_stop() pk_irq_vec_restore(&ctx); pk_semaphore_pend(&(G_pgpe_pstate_record.sem_sgpe_wait), PK_WAIT_FOREVER); - PK_TRACE_ACT_TH("ACT_TH: CtrlStopUpdt Rcvd"); + PK_TRACE_DBG("ACT_TH: CtrlStopUpdt Rcvd"); if (G_sgpe_control_updt.fields.return_code != SGPE_PGPE_IPC_RC_SUCCESS) { @@ -576,294 +566,18 @@ void p9_pgpe_thread_actuate_stop() G_ipc_pend_tbl[IPC_PEND_PSTATE_STOP].pending_ack = 0; ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_PSTATE_STOP].cmd, IPC_RC_SUCCESS); - // PK_TRACE_ACT_TH("ACT_TH: GlbPSCurr:0x%x", G_globalPSCurr ); - // PK_TRACE_ACT_TH("ACT_TH: GlblPsTgt:0x%x", G_globalPSTarget); + // PK_TRACE_DBG("ACT_TH: GlbPSCurr:0x%x", G_globalPSCurr ); + // PK_TRACE_DBG("ACT_TH: GlblPsTgt:0x%x", G_globalPSTarget); pk_irq_vec_restore(&ctx); - PK_TRACE_ACT_TH("ACT_TH: Stop Exit"); + PK_TRACE_DBG("ACT_TH: Stop Exit"); } // //p9_pgpe_thread_actuate_do_step // -void p9_pgpe_thread_actuate_do_step() -{ - PK_TRACE_ACT_TH("ACT_TH: Step Entry"); - PK_TRACE_ACT_TH("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x", G_globalPSTarget, G_globalPSCurr); - PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[0], G_quadPSCurr[0]); - PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[1], G_quadPSCurr[1]); - PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[2], G_quadPSCurr[2]); - PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[3], G_quadPSCurr[3]); - PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[4], G_quadPSCurr[4]); - PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[5], G_quadPSCurr[5]); - uint32_t q; - ocb_qcsr_t qcsr; - qcsr.value = in32(OCB_QCSR); - uint32_t active_conf_cores = 0; - uint32_t targetEVid = p9_pgpe_gppb_intp_vdd_from_ps(G_globalPSTarget, VPD_PT_SET_BIASED_SYSP, VPD_SLOPES_BIASED); - - //Determine active and configured cores - for (q = 0; q < MAX_QUADS; q++) - { - if(G_reqActQuads->fields.requested_active_quads & (0x80 >> q)) - { - if (qcsr.fields.ex_config & (0x800 >> (q << 1))) - { - active_conf_cores |= (0xC0000000 >> (q << 2)); - } - - if (qcsr.fields.ex_config & (0x400 >> (q << 1))) - { - active_conf_cores |= (0x30000000 >> (q << 2)); - } - } - - PK_TRACE_ACT_TH("ACT_TH: act_c=0x%x", active_conf_cores); - } - - //Higher number PState - if (((int16_t)(G_globalPSTarget) - (int16_t)(G_globalPSCurr)) > 0) - { - if ((G_eVidCurr - targetEVid ) <= G_gppb->ext_vrm_step_size_mv) - { - G_eVidNext = targetEVid; - G_globalPSNext = G_globalPSTarget; - - for (q = 0; q < MAX_QUADS; q++) - { - G_quadPSNext[q] = G_quadPSTarget[q]; - } - } - else - { - G_eVidNext = G_eVidCurr - G_gppb->ext_vrm_step_size_mv; - G_globalPSNext = p9_pgpe_gppb_intp_ps_from_ext_vdd(G_eVidNext); - - for (q = 0; q < MAX_QUADS; q++) - { - if (G_quadPSTarget[q] > G_globalPSNext) //Keep localPS under GlobalPS - { - G_quadPSNext[q] = G_globalPSNext; - } - else - { - G_quadPSNext[q] = G_quadPSTarget[q]; - } - } - } - - p9_pgpe_thread_actuate_freq_updt(active_conf_cores); - p9_pgpe_thread_actuate_updt_ext_volt(targetEVid); - } - //Lower number PState - else if (((int16_t)(G_globalPSTarget) - (int16_t)(G_globalPSCurr)) < 0) - { - if ((targetEVid - G_eVidCurr) <= G_gppb->ext_vrm_step_size_mv) - { - G_eVidNext = targetEVid; - G_globalPSNext = G_globalPSTarget; - - for (q = 0; q < MAX_QUADS; q++) - { - G_quadPSNext[q] = G_quadPSTarget[q]; - } - } - else - { - G_eVidNext = G_eVidCurr + G_gppb->ext_vrm_step_size_mv; - G_globalPSNext = p9_pgpe_gppb_intp_ps_from_ext_vdd(G_eVidNext); - - for (q = 0; q < MAX_QUADS; q++) - { - if (G_quadPSTarget[q] < G_globalPSNext) //Keep localPS under GlobalPS - { - G_quadPSNext[q] = G_globalPSNext; - } - else - { - G_quadPSNext[q] = G_quadPSTarget[q]; - } - } - } - - p9_pgpe_thread_actuate_updt_ext_volt(targetEVid); - p9_pgpe_thread_actuate_freq_updt(active_conf_cores); - } - else - { - for (q = 0; q < MAX_QUADS; q++) - { - G_quadPSNext[q] = G_quadPSTarget[q]; - } - - p9_pgpe_thread_actuate_freq_updt(active_conf_cores); - } - - //Update current - G_globalPSCurr = G_globalPSNext; - - for (q = 0; q < MAX_QUADS; q++) - { - if(G_reqActQuads->fields.requested_active_quads & (0x80 >> q) && - (qcsr.fields.ex_config & (0xC00 >> 2 * q))) - { - G_quadPSCurr[q] = G_quadPSNext[q]; - } - } - - //Update Shared SRAM - G_quadState0->fields.quad0_pstate = G_quadPSCurr[0]; - G_quadState0->fields.quad1_pstate = G_quadPSCurr[1]; - G_quadState0->fields.quad2_pstate = G_quadPSCurr[2]; - G_quadState0->fields.quad3_pstate = G_quadPSCurr[3]; - G_quadState1->fields.quad4_pstate = G_quadPSCurr[4]; - G_quadState1->fields.quad5_pstate = G_quadPSCurr[5]; - - PK_TRACE_ACT_TH("ACT_TH: PSTgt: 0x%x PSCurr: 0x%x", G_globalPSTarget, G_globalPSCurr); - PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[0], G_quadPSCurr[0]); - PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[1], G_quadPSCurr[1]); - PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[2], G_quadPSCurr[2]); - PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[3], G_quadPSCurr[3]); - PK_TRACE_ACT_TH("ACT_TH: QTgt: 0x%x QCurr: 0x%x", G_quadPSTarget[4], G_quadPSCurr[4]); - PK_TRACE_ACT_TH("ACT_TH: Step Exit"); -} - -// -//p9_pgpe_thread_actuate_updt_ext_volt -// -//Update External VRM to G_eVidNext -void p9_pgpe_thread_actuate_updt_ext_volt(uint32_t tgtEVid) -{ -#if !EPM_P9_TUNING - uint32_t delay_us = 0; - - //Decreasing - if (G_eVidNext < G_eVidCurr) - { - delay_us = (G_eVidCurr - G_eVidNext) * - G_ext_vrm_dec_rate_mult_usperus; - } - //Increasing - else if(G_eVidNext > G_eVidCurr) - { - delay_us = (G_eVidNext - G_eVidCurr) * - G_ext_vrm_inc_rate_mult_usperus; - } - -#endif - - //Update external voltage - external_voltage_control_write(G_eVidNext); - -#if !EPM_P9_TUNING - - //Delay for delay_us - if (delay_us > 0) - { - pk_sleep(PK_MICROSECONDS((delay_us))); - } - - if(G_eVidNext == tgtEVid) - { - pk_sleep(PK_MICROSECONDS((G_gppb->ext_vrm_stabilization_time_us))); - } - -#endif - - G_eVidCurr = G_eVidNext; -} - -// -//Frequency Update -// -//Sends a DB0 to all active CMEs, so that Quad Managers(CMEs) update DPLL -void p9_pgpe_thread_actuate_freq_updt(uint32_t activeCores) -{ - PK_TRACE_ACT_TH("ACT_TH: FreqUpdt Enter"); - PK_TRACE_ACT_TH("ACT_TH: act_cores=0x%x", activeCores); - pgpe_db0_glb_bcast_t db0; - db0.value = 0; - db0.fields.msg_id = MSGID_DB0_GLOBAL_ACTUAL_BROADCAST; - db0.fields.global_actual = G_globalPSNext; - db0.fields.quad0_ps = G_quadPSNext[0]; - db0.fields.quad1_ps = G_quadPSNext[1]; - db0.fields.quad2_ps = G_quadPSNext[2]; - db0.fields.quad3_ps = G_quadPSNext[3]; - db0.fields.quad4_ps = G_quadPSNext[4]; - db0.fields.quad5_ps = G_quadPSNext[5]; - p9_dd1_db_multicast_wr(PCB_MUTLICAST_GRP1 | CPPM_CMEDB0, db0.value, activeCores); - PK_TRACE_ACT_TH("ACT_TH: MCAST DB0"); - p9_pgpe_wait_cme_db_ack(MSGID_DB0_GLOBAL_ACTUAL_BROADCAST, activeCores);//Wait for ACKs from all CMEs - PK_TRACE_ACT_TH("ACT_TH: Freq Updt Exit"); -} - - -// -//Wait for CME to ack DB0 -// -void p9_pgpe_wait_cme_db_ack(uint8_t msg_id, uint32_t active_conf_cores) -{ - int32_t c, q; - uint32_t opit4pr; - uint8_t pendingAcks = 0; - uint8_t quadPendDBAck[MAX_QUADS]; - - for (q = 0; q < MAX_QUADS; q++) - { - if (active_conf_cores & (0xF0000000 >> (q << 2))) - { - quadPendDBAck[q] = 1; - } - else - { - quadPendDBAck[q] = 0; - } - } - - //Wait for all the acks to come - pendingAcks = 1; - - while (pendingAcks) - { - //Process acks - opit4pr = in32(OCB_OPIT4PRA); - - for (c = 0; c < MAX_CORES; c++) - { - if (opit4pr & (CCSR_CORE_CONFIG_MASK >> c)) - { - if (quadPendDBAck[QUAD_FROM_CORE(c)]) - { - quadPendDBAck[QUAD_FROM_CORE(c)] = 0; - /*#if SIMICS_TUNING == 1 - uint32_t opit4prCurr; - opit4prCurr = in32(OCB_OPIT4PRA); - PK_TRACE_ACT_TH("ACT_TH: temp=0x%x", opit4prCurr); - out32(OCB_OPIT4PRA, (~(CCSR_CORE_CONFIG_MASK >> c)) & opit4prCurr); - #endif*/ - out32(OCB_OPIT4PRA_CLR, CCSR_CORE_CONFIG_MASK >> c); //Clear out pending bits - PK_TRACE_ACT_TH("ACT_TH: Ack C%02u", c); - } - else - { - PK_TRACE_ACT_TH("ACT_TH: BadAck C%02u", c); - pk_halt(); - } - } - } - - //Check if any pending left - pendingAcks = 0; - - for (q = 0; q < MAX_QUADS; q++) - { - if (quadPendDBAck[q]) - { - pendingAcks = 1; - } - } - } -} - +//void p9_pgpe_thread_actuate_do_step() +//{ +//} void p9_pgpe_thread_actuate_init_actual_quad() { diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c index f7849d6e..2dabab12 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_thread_process_requests.c @@ -91,6 +91,11 @@ void p9_pgpe_thread_process_requests(void* arg) pk_semaphore_pend(&(G_pgpe_pstate_record.sem_process_req), PK_WAIT_FOREVER); wrteei(1); + //Enter Sub-Critical Section. Timer Interrupts are enabled + pk_critical_section_enter(&ctx); + pk_irq_save_and_set_mask(0); + pk_critical_section_exit(&ctx); + G_already_sem_posted = 0; restore_irq = 1; @@ -175,6 +180,8 @@ void p9_pgpe_thread_process_requests(void* arg) restore_irq = 0; } + pk_irq_vec_restore(&ctx); //End Sub-Critical Section + //Restore IPC if no pending acks. Otherwise, actuate thread will //eventually restore IPC interrupt if (restore_irq == 1) @@ -195,22 +202,29 @@ void p9_pgpe_process_sgpe_updt_active_cores() ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_CORES_UPDT].cmd; ipcmsg_s2p_update_active_cores_t* args = (ipcmsg_s2p_update_active_cores_t*)async_cmd->cmd_data; - + //If in PM_SUSPENDED state, then ack back with error + if (G_pstatesStatus == PSTATE_PM_SUSPENDED ) + { + args->fields.return_code = SGPE_PGPE_RC_PM_COMPLEX_SUSPEND; + G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_CORES_UPDT].pending_ack = 0; + ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_CORES_UPDT].cmd, IPC_RC_SUCCESS); + pk_halt(); + } //Active quad updates should only be received if Pstates and WOF are enabled. //However, if we have start pending, then we should not process is here. Once, //actuate thread completes actuate_start, it checks for any pending_processing tasks, //if there are any it post to process thread(this thread). This cmd will get processed //then - if(G_pstatesStatus != PSTATE_START_PENDING) + else if(G_pstatesStatus != PSTATE_START_PENDING) { G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_CORES_UPDT].pending_processing = 0; - if(G_pstatesStatus == PSTATE_DISABLE || G_wofEnabled == 0) + if(G_pstatesStatus == PSTATE_STOPPED || G_pstatesStatus == PSTATE_INIT || G_wofEnabled == 0) { - if(G_pstatesStatus == PSTATE_DISABLE) + if(G_pstatesStatus == PSTATE_STOPPED || G_pstatesStatus == PSTATE_INIT) { - PK_TRACE_DBG("PROCTH: C Updt(Pstate Disabled)\n"); - args->fields.return_code = PGPE_RC_PSTATES_DISABLED; + PK_TRACE_DBG("PROCTH: C Updt(Pstate !Started)\n"); + args->fields.return_code = PGPE_RC_PSTATES_NOT_STARTED; } else { @@ -255,21 +269,27 @@ void p9_pgpe_process_sgpe_updt_active_quads() ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].cmd; ipcmsg_s2p_update_active_quads_t* args = (ipcmsg_s2p_update_active_quads_t*)async_cmd->cmd_data; - + //If in PM_SUSPENDED state, then ack back with error + if (G_pstatesStatus == PSTATE_PM_SUSPENDED ) + { + args->fields.return_code = SGPE_PGPE_RC_PM_COMPLEX_SUSPEND; + G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].pending_ack = 0; + ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].cmd, IPC_RC_SUCCESS); + pk_halt(); + } //Active quad updates should only be received if Pstates are enabled. //However, if we have start pending, then we should not process it here. Once, //actuate thread completes actuate_start, it checks for any pending_processing tasks, //if there are any it post to process thread(this thread). This cmd will get processed //then - // - if(G_pstatesStatus != PSTATE_START_PENDING) + else if(G_pstatesStatus != PSTATE_START_PENDING) { G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].pending_processing = 0; - if(G_pstatesStatus == PSTATE_DISABLE) + if(G_pstatesStatus == PSTATE_INIT || G_pstatesStatus == PSTATE_STOPPED) { - PK_TRACE_DBG("PROCTH: Q Updt(Pstate Disabled)\n"); - args->fields.return_code = PGPE_RC_PSTATES_DISABLED; + PK_TRACE_DBG("PROCTH: Q Updt(Pstate Stopped)\n"); + args->fields.return_code = PGPE_RC_PSTATES_NOT_STARTED; G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].pending_ack = 0; ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].cmd, IPC_RC_SUCCESS); } @@ -314,21 +334,29 @@ void p9_pgpe_process_sgpe_suspend_pstates() ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)G_ipc_pend_tbl[IPC_PEND_SGPE_SUSPEND_PSTATES].cmd; ipcmsg_s2p_suspend_pstate_t* args = (ipcmsg_s2p_suspend_pstate_t*)async_cmd->cmd_data; - //Active quad updates should only be received if Pstates are enabled. - //However, if we have start pending, then we should not process is here. Once, - //actuate thread completes actuate_start, it checks for any pending_processing tasks, - //if there are any it post to process thread(this thread). This cmd will get processed - //then - if(G_pstatesStatus != PSTATE_START_PENDING) + //If in PM_SUSPENDED state, then ack back with error + if (G_pstatesStatus == PSTATE_PM_SUSPENDED ) + { + args->fields.return_code = SGPE_PGPE_RC_PM_COMPLEX_SUSPEND; + G_ipc_pend_tbl[IPC_PEND_SGPE_SUSPEND_PSTATES].pending_ack = 0; + ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_SGPE_SUSPEND_PSTATES].cmd, IPC_RC_SUCCESS); + pk_halt(); + //Active quad updates should only be received if Pstates are enabled. + //However, if we have start pending, then we should not process it here. Once, + //actuate thread completes actuate_start, it checks for any pending_processing tasks, + //if there are any it posts to process thread(this thread). + //This cmd will get processed then + } + else if(G_pstatesStatus != PSTATE_START_PENDING) { G_ipc_pend_tbl[IPC_PEND_SGPE_SUSPEND_PSTATES].pending_processing = 0; - if(G_pstatesStatus == PSTATE_DISABLE) + if(G_pstatesStatus == PSTATE_INIT || G_pstatesStatus == PSTATE_STOPPED) { - PK_TRACE_DBG("PROCTH: Susp Pst(Pstate Disabled)\n"); - args->fields.return_code = PGPE_RC_PSTATES_DISABLED; - G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].pending_ack = 0; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_SGPE_ACTIVE_QUADS_UPDT].cmd, IPC_RC_SUCCESS); + PK_TRACE_DBG("PROCTH: Susp Pst(Pstate !Started)\n"); + args->fields.return_code = PGPE_RC_PSTATES_NOT_STARTED; + G_ipc_pend_tbl[IPC_PEND_SGPE_SUSPEND_PSTATES].pending_ack = 0; + ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_SGPE_SUSPEND_PSTATES].cmd, IPC_RC_SUCCESS); } else { @@ -346,8 +374,7 @@ void p9_pgpe_process_clip_updt() { PK_TRACE_DBG("PROCTH: Clip Updt Entry\n"); - uint32_t q; - uint32_t rc; + uint32_t q, ack = 0; ipc_async_cmd_t* async_cmd = (ipc_async_cmd_t*)G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].cmd; ipcmsg_clip_update_t* args = (ipcmsg_clip_update_t*)async_cmd->cmd_data; @@ -356,13 +383,19 @@ void p9_pgpe_process_clip_updt() if(G_pgpe_header_data->g_pgpe_qm_flags & OCC_IPC_IMMEDIATE_RESP) { PK_TRACE_DBG("PROCTH: Clip Updt Imme\n"); - G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].pending_ack = 0; args->msg_cb.rc = PGPE_RC_SUCCESS; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].cmd, IPC_RC_SUCCESS); + ack = 1; + } + else if (G_pstatesStatus == PSTATE_PM_SUSPENDED || + G_pstatesStatus == PSTATE_PM_SUSPEND_PENDING || + G_pstatesStatus == PSTATE_SAFE_MODE) + { + PK_TRACE_DBG("PROCTH: Clip Updt PMSUSP/Safe\n"); + args->msg_cb.rc = PGPE_RC_PM_COMPLEX_SUSPEND_SAFE_MODE; + ack = 1; } else { - //IPC from 405 treats clip_min as Pstate for min frequency(higher numbered) //and clip_max as Pstate for max frequency(lower numbered). However, PGPE //Hcode stores them with reverse interpretation. @@ -374,23 +407,20 @@ void p9_pgpe_process_clip_updt() p9_pgpe_pstate_apply_clips(&G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT]); - if (G_pstatesStatus == PSTATE_DISABLE) + if (G_pstatesStatus == PSTATE_INIT || G_pstatesStatus == PSTATE_STOPPED) { args->msg_cb.rc = PGPE_RC_SUCCESS; - G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].pending_ack = 0; - rc = ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].cmd, IPC_RC_SUCCESS); - - if (rc != IPC_RC_SUCCESS) - { - pk_halt(); - } - else - { - PK_TRACE_DBG("PROCTH: Clip Upd Acked\n"); - } + ack = 1; } } + //Clips ACKed in error cases or if Pstates are not active + if (ack == 1) + { + G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].pending_ack = 0; + ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_CLIP_UPDT].cmd, IPC_RC_SUCCESS); + } + PK_TRACE_DBG("PROCTH: Clip Upd Exit\n"); } @@ -409,84 +439,79 @@ void p9_pgpe_process_wof_ctrl() if(G_pgpe_header_data->g_pgpe_qm_flags & OCC_IPC_IMMEDIATE_RESP) { PK_TRACE_DBG("PROCTH: WOF Ctrl Updt Imme\n"); - G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].pending_ack = 0; args->msg_cb.rc = PGPE_RC_SUCCESS; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].cmd, IPC_RC_SUCCESS); + } + else if (G_pstatesStatus == PSTATE_PM_SUSPENDED || + G_pstatesStatus == PSTATE_PM_SUSPEND_PENDING || + G_pstatesStatus == PSTATE_SAFE_MODE) + { + PK_TRACE_DBG("PROCTH: Clip Updt PMSUSP/Safe\n"); + args->msg_cb.rc = PGPE_RC_PM_COMPLEX_SUSPEND_SAFE_MODE; + } + else if(G_pstatesStatus == PSTATE_INIT || G_pstatesStatus == PSTATE_STOPPED) + { + args->msg_cb.rc = PGPE_RC_PSTATES_NOT_STARTED; } else { - if(G_pstatesStatus == PSTATE_DISABLE) + args->msg_cb.rc = PGPE_RC_SUCCESS; + + //If WOF ON + if (args->action == PGPE_ACTION_WOF_ON) { - args->msg_cb.rc = PGPE_RC_PSTATES_DISABLED; - G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].pending_ack = 0; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].cmd, IPC_RC_SUCCESS); + if(G_wofEnabled == 0) + { + G_wofPending = 1; + } } - else + else if (args->action == PGPE_ACTION_WOF_OFF) { - //If WOF ON - if (args->action == PGPE_ACTION_WOF_ON) + if(G_wofEnabled == 1) { - if(G_wofEnabled == 1) - { - G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].pending_ack = 0; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].cmd, IPC_RC_SUCCESS); - } - else +#if SGPE_IPC_ENABLED == 1 + uint32_t rc; + PkMachineContext ctx; + //Send "Disable Core Stop Updates" IPC to SGPE + G_sgpe_control_updt.fields.return_code = 0x0; + G_sgpe_control_updt.fields.action = CTRL_STOP_UPDT_DISABLE_CORE; + G_ipc_msg_pgpe_sgpe.cmd_data = &G_sgpe_control_updt; + ipc_init_msg(&G_ipc_msg_pgpe_sgpe.cmd, + IPC_MSGID_PGPE_SGPE_CONTROL_STOP_UPDATES, + p9_pgpe_pstate_ipc_rsp_cb_sem_post, + (void*)&G_pgpe_pstate_record.sem_sgpe_wait); + + //send the command + rc = ipc_send_cmd(&G_ipc_msg_pgpe_sgpe.cmd); + + if(rc) { - G_wofPending = 1; + pk_halt(); } - } - else if (args->action == PGPE_ACTION_WOF_OFF) - { - if(G_wofEnabled == 0) + + //Wait for SGPE ACK with alive Quads + pk_irq_vec_restore(&ctx); + pk_semaphore_pend(&(G_pgpe_pstate_record.sem_actuate), PK_WAIT_FOREVER); + + if (G_sgpe_control_updt.fields.return_code == SGPE_PGPE_IPC_RC_SUCCESS) { - G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].pending_ack = 0; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].cmd, IPC_RC_SUCCESS); + //Update Shared Memory Region + G_quadState0->fields.active_cores = G_sgpe_control_updt.fields.active_cores >> 8; + G_quadState1->fields.active_cores = G_sgpe_control_updt.fields.active_cores & 0xFF; + G_reqActQuads->fields.requested_active_quads = G_sgpe_control_updt.fields.active_quads; } else { -#if SGPE_IPC_ENABLED == 1 - uint32_t rc; - PkMachineContext ctx; - //Send "Disable Core Stop Updates" IPC to SGPE - G_sgpe_control_updt.fields.return_code = 0x0; - G_sgpe_control_updt.fields.action = CTRL_STOP_UPDT_DISABLE_CORE; - G_ipc_msg_pgpe_sgpe.cmd_data = &G_sgpe_control_updt; - ipc_init_msg(&G_ipc_msg_pgpe_sgpe.cmd, - IPC_MSGID_PGPE_SGPE_CONTROL_STOP_UPDATES, - p9_pgpe_pstate_ipc_rsp_cb_sem_post, - (void*)&G_pgpe_pstate_record.sem_sgpe_wait); - - //send the command - rc = ipc_send_cmd(&G_ipc_msg_pgpe_sgpe.cmd); - - if(rc) - { - pk_halt(); - } - - //Wait for SGPE ACK with alive Quads - pk_irq_vec_restore(&ctx); - pk_semaphore_pend(&(G_pgpe_pstate_record.sem_actuate), PK_WAIT_FOREVER); - - if (G_sgpe_control_updt.fields.return_code == SGPE_PGPE_IPC_RC_SUCCESS) - { - //Update Shared Memory Region - G_quadState0->fields.active_cores = G_sgpe_control_updt.fields.active_cores >> 8; - G_quadState1->fields.active_cores = G_sgpe_control_updt.fields.active_cores & 0xFF; - G_reqActQuads->fields.requested_active_quads = G_sgpe_control_updt.fields.active_quads; - } - else - { - pk_halt(); - } + pk_halt(); + } #endif// _SGPE_IPC_ENABLED_ - } } } } + G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].pending_ack = 0; + ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_WOF_CTRL].cmd, IPC_RC_SUCCESS); + PK_TRACE_DBG("PROCTH: WOF Ctrl Exit\n"); } @@ -505,81 +530,83 @@ void p9_pgpe_process_wof_vfrt() if(G_pgpe_header_data->g_pgpe_qm_flags & OCC_IPC_IMMEDIATE_RESP) { PK_TRACE_DBG("PROCTH: WOF VFRT Imme\n"); - G_ipc_pend_tbl[IPC_PEND_WOF_VFRT].pending_ack = 0; args->msg_cb.rc = PGPE_RC_SUCCESS; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_WOF_VFRT].cmd, IPC_RC_SUCCESS); + } + else if (G_pstatesStatus == PSTATE_PM_SUSPENDED || + G_pstatesStatus == PSTATE_PM_SUSPEND_PENDING || + G_pstatesStatus == PSTATE_SAFE_MODE) + { + PK_TRACE_DBG("PROCTH: Clip Updt PMSUSP/Safe\n"); + args->msg_cb.rc = PGPE_RC_PM_COMPLEX_SUSPEND_SAFE_MODE; + } + else if(G_pstatesStatus == PSTATE_STOPPED || G_pstatesStatus == PSTATE_INIT || + (G_wofEnabled == 0 && G_wofPending == 0)) + { + args->msg_cb.rc = PGPE_RC_PSTATES_NOT_STARTED; } else { - if(G_pstatesStatus == PSTATE_DISABLE || (G_wofEnabled == 0 && G_wofPending == 0)) + //Update VFRT pointer + G_vfrt_ptr = args->vfrt_ptr; + + //If active_quads field of this IPC matches requested active quads + //in Shared SRAM, then clear OCCFLG[REQUESTED_ACTIVE_QUAD_UPDATE] + if (args->active_quads == G_reqActQuads->fields.requested_active_quads) { - G_ipc_pend_tbl[IPC_PEND_WOF_VFRT].pending_ack = 0; - args->msg_cb.rc = PGPE_RC_PSTATES_DISABLED; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_WOF_VFRT].cmd, IPC_RC_SUCCESS); + GPE_PUTSCOM(OCB_OCCFLG_CLR, BIT32(30)); + p9_pgpe_pstate_calc_wof(); } - else + + if (G_wofPending == 1) { - //Update VFRT pointer - G_vfrt_ptr = args->vfrt_ptr; + G_wofEnabled = 1; + G_wofPending = 0; - //If active_quads field of this IPC matches requested active quads - //in Shared SRAM, then clear OCCFLG[REQUESTED_ACTIVE_QUAD_UPDATE] - if (args->active_quads == G_reqActQuads->fields.requested_active_quads) +#if SGPE_IPC_ENABLED == 1 + uint32_t rc; + PkMachineContext ctx; + //Send "Disable Core Stop Updates" IPC to SGPE + G_sgpe_control_updt.fields.return_code = 0x0; + G_sgpe_control_updt.fields.action = CTRL_STOP_UPDT_DISABLE_CORE; + G_ipc_msg_pgpe_sgpe.cmd_data = &G_sgpe_control_updt; + ipc_init_msg(&G_ipc_msg_pgpe_sgpe.cmd, + IPC_MSGID_PGPE_SGPE_CONTROL_STOP_UPDATES, + p9_pgpe_pstate_ipc_rsp_cb_sem_post, + (void*)&G_pgpe_pstate_record.sem_sgpe_wait); + + //send the command + rc = ipc_send_cmd(&G_ipc_msg_pgpe_sgpe.cmd); + + if(rc) { - GPE_PUTSCOM(OCB_OCCFLG_CLR, BIT32(30)); - p9_pgpe_pstate_calc_wof(); + pk_halt(); } - if (G_wofPending == 1) - { - G_wofEnabled = 1; - G_wofPending = 0; - -#if SGPE_IPC_ENABLED == 1 - uint32_t rc; - PkMachineContext ctx; - //Send "Disable Core Stop Updates" IPC to SGPE - G_sgpe_control_updt.fields.return_code = 0x0; - G_sgpe_control_updt.fields.action = CTRL_STOP_UPDT_DISABLE_CORE; - G_ipc_msg_pgpe_sgpe.cmd_data = &G_sgpe_control_updt; - ipc_init_msg(&G_ipc_msg_pgpe_sgpe.cmd, - IPC_MSGID_PGPE_SGPE_CONTROL_STOP_UPDATES, - p9_pgpe_pstate_ipc_rsp_cb_sem_post, - (void*)&G_pgpe_pstate_record.sem_sgpe_wait); - - //send the command - rc = ipc_send_cmd(&G_ipc_msg_pgpe_sgpe.cmd); - - if(rc) - { - pk_halt(); - } - - //Wait for SGPE ACK with alive Quads - pk_irq_vec_restore(&ctx); - pk_semaphore_pend(&(G_pgpe_pstate_record.sem_actuate), PK_WAIT_FOREVER); - - if (G_sgpe_control_updt.fields.return_code == SGPE_PGPE_IPC_RC_SUCCESS) - { - //Update Shared Memory Region - G_quadState0->fields.active_cores = G_sgpe_control_updt.fields.active_cores >> 8; - G_quadState1->fields.active_cores = G_sgpe_control_updt.fields.active_cores & 0xFF; - G_reqActQuads->fields.requested_active_quads = G_sgpe_control_updt.fields.active_quads; - } - else - { - pk_halt(); - } + //Wait for SGPE ACK with alive Quads + pk_irq_vec_restore(&ctx); + pk_semaphore_pend(&(G_pgpe_pstate_record.sem_actuate), PK_WAIT_FOREVER); -#endif// _SGPE_IPC_ENABLED_ + if (G_sgpe_control_updt.fields.return_code == SGPE_PGPE_IPC_RC_SUCCESS) + { + //Update Shared Memory Region + G_quadState0->fields.active_cores = G_sgpe_control_updt.fields.active_cores >> 8; + G_quadState1->fields.active_cores = G_sgpe_control_updt.fields.active_cores & 0xFF; + G_reqActQuads->fields.requested_active_quads = G_sgpe_control_updt.fields.active_quads; + } + else + { + pk_halt(); } - G_ipc_pend_tbl[IPC_PEND_WOF_VFRT].pending_ack = 0; - args->msg_cb.rc = PGPE_RC_SUCCESS; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_WOF_VFRT].cmd, IPC_RC_SUCCESS); +#endif// _SGPE_IPC_ENABLED_ } + + args->msg_cb.rc = PGPE_RC_SUCCESS; } + G_ipc_pend_tbl[IPC_PEND_WOF_VFRT].pending_ack = 0; + ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_WOF_VFRT].cmd, IPC_RC_SUCCESS); + PK_TRACE_DBG("PROCTH: WOF VFRT Exit\n"); } @@ -599,48 +626,48 @@ void p9_pgpe_process_set_pmcr_req() if(G_pgpe_header_data->g_pgpe_qm_flags & OCC_IPC_IMMEDIATE_RESP) { PK_TRACE_DBG("PROCTH: Set PMCR Imme\n"); - G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].pending_ack = 0; args->msg_cb.rc = PGPE_RC_SUCCESS; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].cmd, IPC_RC_SUCCESS); + } + else if(G_pmcrOwner != PMCR_OWNER_OCC) + { + PK_TRACE_DBG("PROCTH: !OCC_PMCR_OWNER\n"); + args->msg_cb.rc = PGPE_RC_OCC_NOT_PMCR_OWNER; + } + else if (G_pstatesStatus == PSTATE_INIT || G_pstatesStatus == PSTATE_STOPPED) + { + PK_TRACE_DBG("PROCTH: Pstates !Started\n"); + args->msg_cb.rc = PGPE_RC_PSTATES_NOT_STARTED; + } + else if (G_pstatesStatus == PSTATE_PM_SUSPENDED || + G_pstatesStatus == PSTATE_PM_SUSPEND_PENDING || + G_pstatesStatus == PSTATE_SAFE_MODE) + { + PK_TRACE_DBG("PROCTH: Clip Updt PMSUSP/Safe\n"); + args->msg_cb.rc = PGPE_RC_PM_COMPLEX_SUSPEND_SAFE_MODE; } else { - if(G_pmcrOwner != PMCR_OWNER_OCC) - { - args->msg_cb.rc = PGPE_RC_OCC_NOT_PMCR_OWNER; - G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].pending_ack = 0; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].cmd, IPC_RC_SUCCESS); - } - else if (G_pstatesStatus == PSTATE_DISABLE) - { - PK_TRACE_DBG("PROCTH: Pstates Disabled\n"); - args->msg_cb.rc = PGPE_RC_PSTATES_DISABLED; - G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].pending_ack = 0; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].cmd, IPC_RC_SUCCESS); - } - else - { - PK_TRACE_DBG("PROCTH: Upd coresPSReq\n"); + PK_TRACE_DBG("PROCTH: Upd coresPSReq\n"); - for (q = 0; q < MAX_QUADS; q++) + for (q = 0; q < MAX_QUADS; q++) + { + for (c = (q * CORES_PER_QUAD); c < (q + 1)*CORES_PER_QUAD; c++) { - for (c = (q * CORES_PER_QUAD); c < (q + 1)*CORES_PER_QUAD; c++) - { - G_coresPSRequest[c] = (args->pmcr[q] >> 48) & 0x00FF; - } - - PK_TRACE_DBG("PROCTH: coresPSReq: 0x%x\n", G_coresPSRequest[q * CORES_PER_QUAD]); + G_coresPSRequest[c] = (args->pmcr[q] >> 48) & 0x00FF; } - p9_pgpe_pstate_do_auction(ALL_QUADS_BIT_MASK); - p9_pgpe_pstate_apply_clips(); - - //Send ACK to OCC - G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].pending_ack = 0; - args->msg_cb.rc = PGPE_RC_SUCCESS; - ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].cmd, IPC_RC_SUCCESS); + PK_TRACE_DBG("PROCTH: coresPSReq: 0x%x\n", G_coresPSRequest[q * CORES_PER_QUAD]); } + + p9_pgpe_pstate_do_auction(ALL_QUADS_BIT_MASK); + p9_pgpe_pstate_apply_clips(); + + args->msg_cb.rc = PGPE_RC_SUCCESS; //Return Code } + //Ack back to OCC + G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].pending_ack = 0; + ipc_send_rsp(G_ipc_pend_tbl[IPC_PEND_SET_PMCR_REQ].cmd, IPC_RC_SUCCESS); + PK_TRACE_DBG("PROCTH: Set PMCR Exit\n"); } diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h index 03d2d8f2..8b51888f 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pk_app_cfg.h @@ -43,7 +43,8 @@ #define DEV_DEBUG 1 #define PK_TRACE_TIMER_OUTPUT 0 #define SGPE_IPC_ENABLED 0 -#define OVERRIDE_OTHER_ENGINES_IRQS 1 +#define OVERRIDE_OTHER_ENGINES_IRQS 0 +#define OVERRIDE_PSAFE_PSTATE 1 ///This application uses IPC code #define GLOBAL_CFG_USE_IPC @@ -80,10 +81,10 @@ #define PK_KERNEL_TRACE_ENABLE 0 #elif PK_TRACE_LEVEL == 2 /*only PK_TRACE_INF+DBG+KERNEL*/ #define PK_TRACE_ENABLE 1 - #define PK_TRACE_DBG_SUPPRESS 1 + #define PK_TRACE_DBG_SUPPRESS 0 #define PK_TRACE_CRIT_ENABLE 1 #define PK_TRACE_CKPT_ENABLE 1 - #define PK_KERNEL_TRACE_ENABLE 1 + #define PK_KERNEL_TRACE_ENABLE 0 #else /*All TRACEs*/ #define PK_TRACE_ENABLE 1 #define PK_TRACE_DBG_SUPPRESS 0 @@ -119,6 +120,7 @@ /// IRQ#, TYPE, POLARITY, ENABLE /// #define APPCFG_EXT_IRQS_CONFIG \ + OCCHW_IRQ_OCC_ERROR OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ OCCHW_IRQ_GPE3_HALT OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ OCCHW_IRQ_CHECK_STOP_GPE2 OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ OCCHW_IRQ_IPI2_HI_PRIORITY OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ diff --git a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk index 0221d630..3d28de77 100644 --- a/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk +++ b/import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/pstate_gpe.mk @@ -80,10 +80,7 @@ $(IMAGE)_TRACE_HASH_PREFIX := $(shell echo $(IMAGE) | md5sum | cut -c1-4 \ | xargs -i printf "%d" 0x{}) # Options for PK_TRACE -$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=3 -$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_ACT_TH_ENABLE=1 -$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_PROC_TH_ENABLE=0 -$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_PSTATE_ENABLE=0 +$(IMAGE)_COMMONFLAGS+= -DPK_TRACE_LEVEL=2 $(IMAGE)_COMMONFLAGS+= -DPK_TRACE_TIMER_OUTPUT=0 |
