diff options
Diffstat (limited to 'import/chips/p9')
14 files changed, 279 insertions, 184 deletions
diff --git a/import/chips/p9/common/pmlib/include/occhw_irq_config.h b/import/chips/p9/common/pmlib/include/occhw_irq_config.h index 94bf77bf..07d55103 100644 --- a/import/chips/p9/common/pmlib/include/occhw_irq_config.h +++ b/import/chips/p9/common/pmlib/include/occhw_irq_config.h @@ -117,7 +117,7 @@ OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING OCCHW_IRQ_TARGET_ID_GPE3 \ OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING OCCHW_IRQ_TARGET_ID_GPE3 \ OCCHW_IRQ_PMC_PCB_INTR_TYPE4_PENDING OCCHW_IRQ_TARGET_ID_GPE2 \ - OCCHW_IRQ_PMC_PCB_INTR_TYPE5_PENDING OCCHW_IRQ_TARGET_ID_NONE \ + OCCHW_IRQ_PMC_PCB_INTR_TYPE5_PENDING OCCHW_IRQ_TARGET_ID_GPE3 \ OCCHW_IRQ_PMC_PCB_INTR_TYPE6_PENDING OCCHW_IRQ_TARGET_ID_GPE3 \ OCCHW_IRQ_PMC_PCB_INTR_TYPE7_PENDING OCCHW_IRQ_TARGET_ID_NONE \ OCCHW_IRQ_PMC_O2S_0A_ONGOING OCCHW_IRQ_TARGET_ID_NONE \ diff --git a/import/chips/p9/common/pmlib/include/stop_sgpe_cme_api.h b/import/chips/p9/common/pmlib/include/stop_sgpe_cme_api.h index eed0399f..1df005c0 100644 --- a/import/chips/p9/common/pmlib/include/stop_sgpe_cme_api.h +++ b/import/chips/p9/common/pmlib/include/stop_sgpe_cme_api.h @@ -30,14 +30,14 @@ enum SGPE_STOP_IRQ_PAYLOAD_MASKS { TYPE2_PAYLOAD_STOP_LEVEL = 0x00F, TYPE2_PAYLOAD_ENTRY_EVENT = 0x000, // 0000 - TYPE2_PAYLOAD_ENTRY_RCLK = 0x100, // 0001 + TYPE5_PAYLOAD_ENTRY_RCLK = 0x100, // 0001 // 0010 reserved // 0011 reserved TYPE2_PAYLOAD_EXIT_EVENT = 0xC00, // 1100 TYPE2_PAYLOAD_HARDWARE_WAKEUP = 0x800, // 1000 TYPE2_PAYLOAD_SOFTWARE_WAKEUP = 0x400, // 0100 - TYPE2_PAYLOAD_EXIT_RCLK = 0x500, // 0101 + TYPE5_PAYLOAD_EXIT_RCLK = 0x500, // 0101 // 0110 reserved TYPE2_PAYLOAD_DECREMENTER_WAKEUP = 0x700, // 0111 @@ -55,7 +55,8 @@ enum SGPE_STOP_IRQ_PAYLOAD_MASKS enum CME_STOP_PIG_TYPES { PIG_TYPE2 = 2, - PIG_TYPE3 = 3 + PIG_TYPE3 = 3, + PIG_TYPE5 = 5 }; /// Numberical Doorbell Message IDs(used by CME check) diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c index c03a7537..15b89193 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_irq_handlers.c @@ -273,8 +273,8 @@ p9_cme_stop_db2_handler(void* arg, PkIrqId irq) #endif #endif // Finish handshake with SGPE for Stop11 via PIG - pig.fields.req_intr_type = PIG_TYPE3; - pig.fields.req_intr_payload = TYPE2_PAYLOAD_ENTRY_RCLK | STOP_LEVEL_11; + pig.fields.req_intr_type = PIG_TYPE5; + pig.fields.req_intr_payload = TYPE5_PAYLOAD_ENTRY_RCLK | STOP_LEVEL_11; CME_PUTSCOM_NOP(PPM_PIG, core, pig.value); break; @@ -300,8 +300,8 @@ p9_cme_stop_db2_handler(void* arg, PkIrqId irq) #endif #endif // Finish handshake with SGPE for Stop11 via PIG - pig.fields.req_intr_type = PIG_TYPE3; - pig.fields.req_intr_payload = TYPE2_PAYLOAD_EXIT_RCLK; + pig.fields.req_intr_type = PIG_TYPE5; + pig.fields.req_intr_payload = TYPE5_PAYLOAD_EXIT_RCLK; CME_PUTSCOM_NOP(PPM_PIG, core, pig.value); break; diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c index 28710bf9..f61cccb8 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.c @@ -59,7 +59,8 @@ const uint64_t ext_irq_vectors_sgpe[NUM_EXT_IRQ_PRTY_LEVELS][2] = IRQ_VEC_PRTY3_SGPE | IRQ_VEC_PRTY4_SGPE | IRQ_VEC_PRTY5_SGPE | - IRQ_VEC_PRTY6_SGPE + IRQ_VEC_PRTY6_SGPE | + IRQ_VEC_PRTY7_SGPE }, { IRQ_VEC_PRTY1_SGPE, /* 1: IDX_PRTY_LVL_IPI3_HIGH */ @@ -68,7 +69,8 @@ const uint64_t ext_irq_vectors_sgpe[NUM_EXT_IRQ_PRTY_LEVELS][2] = IRQ_VEC_PRTY3_SGPE | IRQ_VEC_PRTY4_SGPE | IRQ_VEC_PRTY5_SGPE | - IRQ_VEC_PRTY6_SGPE + IRQ_VEC_PRTY6_SGPE | + IRQ_VEC_PRTY7_SGPE }, { IRQ_VEC_PRTY2_SGPE, /* 2: IDX_PRTY_LVL_PIG_TYPE2 */ @@ -76,29 +78,38 @@ const uint64_t ext_irq_vectors_sgpe[NUM_EXT_IRQ_PRTY_LEVELS][2] = IRQ_VEC_PRTY3_SGPE | IRQ_VEC_PRTY4_SGPE | IRQ_VEC_PRTY5_SGPE | - IRQ_VEC_PRTY6_SGPE + IRQ_VEC_PRTY6_SGPE | + IRQ_VEC_PRTY7_SGPE }, { IRQ_VEC_PRTY3_SGPE, /* 3: IDX_PRTY_LVL_PIG_TYPE6 */ IRQ_VEC_PRTY3_SGPE | IRQ_VEC_PRTY4_SGPE | IRQ_VEC_PRTY5_SGPE | - IRQ_VEC_PRTY6_SGPE + IRQ_VEC_PRTY6_SGPE | + IRQ_VEC_PRTY7_SGPE }, { - IRQ_VEC_PRTY4_SGPE, /* 3: IDX_PRTY_LVL_PIG_TYPE3 */ + IRQ_VEC_PRTY4_SGPE, /* 4: IDX_PRTY_LVL_PIG_TYPE5 */ IRQ_VEC_PRTY4_SGPE | IRQ_VEC_PRTY5_SGPE | - IRQ_VEC_PRTY6_SGPE + IRQ_VEC_PRTY6_SGPE | + IRQ_VEC_PRTY7_SGPE }, { - IRQ_VEC_PRTY5_SGPE, /* 3: IDX_PRTY_LVL_IPI3_LOW */ + IRQ_VEC_PRTY5_SGPE, /* 5: IDX_PRTY_LVL_PIG_TYPE3 */ IRQ_VEC_PRTY5_SGPE | - IRQ_VEC_PRTY6_SGPE + IRQ_VEC_PRTY6_SGPE | + IRQ_VEC_PRTY7_SGPE }, { - IRQ_VEC_PRTY6_SGPE, /* 4: IDX_PRTY_LVL_DISABLED */ - IRQ_VEC_PRTY6_SGPE + IRQ_VEC_PRTY6_SGPE, /* 6: IDX_PRTY_LVL_IPI3_LOW */ + IRQ_VEC_PRTY6_SGPE | + IRQ_VEC_PRTY7_SGPE + }, + { + IRQ_VEC_PRTY7_SGPE, /* 7: IDX_PRTY_LVL_DISABLED */ + IRQ_VEC_PRTY7_SGPE } }; diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h index 45486cc8..63f83070 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_irq.h @@ -51,12 +51,13 @@ #define IDX_PRTY_LVL_IPI3_HIGH 1 #define IDX_PRTY_LVL_PIG_TYPE2 2 #define IDX_PRTY_LVL_PIG_TYPE6 3 -#define IDX_PRTY_LVL_PIG_TYPE3 4 -#define IDX_PRTY_LVL_IPI3_LOW 5 -#define IDX_PRTY_LVL_DISABLED 6 +#define IDX_PRTY_LVL_PIG_TYPE5 4 +#define IDX_PRTY_LVL_PIG_TYPE3 5 +#define IDX_PRTY_LVL_IPI3_LOW 6 +#define IDX_PRTY_LVL_DISABLED 7 #define IDX_PRTY_VEC 0 #define IDX_MASK_VEC 1 -#define NUM_EXT_IRQ_PRTY_LEVELS (uint8_t)(7) +#define NUM_EXT_IRQ_PRTY_LEVELS (uint8_t)(8) extern const uint64_t ext_irq_vectors_sgpe[NUM_EXT_IRQ_PRTY_LEVELS][2]; // Group0: Non-task hi-prty IRQs @@ -68,20 +69,23 @@ extern const uint64_t ext_irq_vectors_sgpe[NUM_EXT_IRQ_PRTY_LEVELS][2]; #define IRQ_VEC_PRTY2_SGPE (uint64_t)(0x0000000000010000) // Group3: pig_type6 #define IRQ_VEC_PRTY3_SGPE (uint64_t)(0x0000000000001000) +// Group3: pig_type5 +#define IRQ_VEC_PRTY4_SGPE (uint64_t)(0x0000000000002000) // Group4: pig_type3 -#define IRQ_VEC_PRTY4_SGPE (uint64_t)(0x0000000000008000) +#define IRQ_VEC_PRTY5_SGPE (uint64_t)(0x0000000000008000) // Group5: ipi3_low -#define IRQ_VEC_PRTY5_SGPE (uint64_t)(0x0000000000000004) +#define IRQ_VEC_PRTY6_SGPE (uint64_t)(0x0000000000000004) // Group6: We should never detect these -#define IRQ_VEC_PRTY6_SGPE (uint64_t)(0x0100800000000000) -//#define IRQ_VEC_PRTY6_SGPE (uint64_t)(0xFEFF7FF7FFFE6FFB) +#define IRQ_VEC_PRTY7_SGPE (uint64_t)(0x0100800000000000) +//#define IRQ_VEC_PRTY7_SGPE (uint64_t)(0xFEFF7FF7FFFE6FFB) #define IRQ_VEC_ALL_OUR_IRQS ( IRQ_VEC_PRTY0_SGPE | \ IRQ_VEC_PRTY1_SGPE | \ IRQ_VEC_PRTY2_SGPE | \ IRQ_VEC_PRTY3_SGPE | \ IRQ_VEC_PRTY4_SGPE | \ - IRQ_VEC_PRTY5_SGPE ) // Note, we do not incl PRTY6 here! + IRQ_VEC_PRTY5_SGPE | \ + IRQ_VEC_PRTY6_SGPE ) // Note, we do not incl PRTY6 here! // This should be 0xFFFFFFFFFFFFFFFF #define IRQ_VEC_PRTY_CHECK ( IRQ_VEC_PRTY0_SGPE | \ @@ -90,7 +94,8 @@ extern const uint64_t ext_irq_vectors_sgpe[NUM_EXT_IRQ_PRTY_LEVELS][2]; IRQ_VEC_PRTY3_SGPE | \ IRQ_VEC_PRTY4_SGPE | \ IRQ_VEC_PRTY5_SGPE | \ - IRQ_VEC_PRTY6_SGPE ) + IRQ_VEC_PRTY6_SGPE | \ + IRQ_VEC_PRTY7_SGPE ) extern uint8_t g_current_prty_level; extern uint8_t g_oimr_stack[NUM_EXT_IRQ_PRTY_LEVELS]; diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C index 14ce1f10..1295170e 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_main.C @@ -77,7 +77,7 @@ IRQ_HANDLER_DEFAULT //OCCHW_IRQ_PMC_PCB_INTR_TYPE1_PENDING IRQ_HANDLER(p9_sgpe_pig_type2_handler, 0) //OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING IRQ_HANDLER(p9_sgpe_pig_type3_handler, 0) //OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING IRQ_HANDLER_DEFAULT //OCCHW_IRQ_PMC_PCB_INTR_TYPE4_PENDING -IRQ_HANDLER_DEFAULT //OCCHW_IRQ_PMC_PCB_INTR_TYPE5_PENDING +IRQ_HANDLER(p9_sgpe_pig_type5_handler, 0) //OCCHW_IRQ_PMC_PCB_INTR_TYPE5_PENDING IRQ_HANDLER(p9_sgpe_pig_type6_handler, 0) //OCCHW_IRQ_PMC_PCB_INTR_TYPE6_PENDING IRQ_HANDLER_DEFAULT //OCCHW_IRQ_PMC_PCB_INTR_TYPE7_PENDING IRQ_HANDLER_DEFAULT //OCCHW_IRQ_PMC_O2S_0A_ONGOING diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h index 3f9eefce..f4a2d3b7 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop.h @@ -47,6 +47,7 @@ extern "C" { #include "ppm_register_addresses.h" #include "cppm_register_addresses.h" #include "qppm_register_addresses.h" +#include "gpe_register_addresses.h" #include "ocb_firmware_registers.h" #include "cme_firmware_registers.h" @@ -279,6 +280,11 @@ typedef struct ipc_msg_t* suspend_cmd; } sgpe_wof_t; +typedef struct +{ + uint32_t strave_counter; +} sgpe_fit_t; + /// SGPE Stop Score Board Structure typedef struct { @@ -290,6 +296,7 @@ typedef struct // group of ex and quad entering or exiting the stop sgpe_group_t group; sgpe_wof_t wof; + sgpe_fit_t fit; PkSemaphore sem[2]; } SgpeStopRecord __attribute__ ((aligned (8))); @@ -320,8 +327,10 @@ void p9_sgpe_ipc_pgpe_suspend_stop(ipc_msg_t*, void*); void p9_sgpe_stop_suspend_all_cmes(); /// SGPE STOP Interrupt Handlers +void p9_sgpe_fit_handler(); void p9_sgpe_pig_type2_handler(void*, PkIrqId); void p9_sgpe_pig_type3_handler(void*, PkIrqId); +void p9_sgpe_pig_type5_handler(void*, PkIrqId); void p9_sgpe_pig_type6_handler(void*, PkIrqId); void p9_sgpe_ipi3_low_handler(void*, PkIrqId); void p9_sgpe_stop_suspend_db1_cme(uint32_t, uint32_t); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_enter_marks.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_enter_marks.h index c5a4c897..3e083da2 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_enter_marks.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_enter_marks.h @@ -40,7 +40,8 @@ enum SGPE_SE_MARKS ENDSCOPE_STOP_ENTRY = 0x18, STOP_PIG_TYPE2_HANDLER = 0x20, STOP_PIG_TYPE3_HANDLER = 0x28, - STOP_PIG_TYPE6_HANDLER = 0x30, + STOP_PIG_TYPE5_HANDLER = 0x30, + STOP_PIG_TYPE6_HANDLER = 0x38, SE_LESSTHAN8_DONE = 0x68, SE_STOP_L2_CLKS = 0xe0, SE_STOP_L2_GRID = 0xe8, @@ -66,6 +67,7 @@ const std::vector<SGPE_SE_MARKS> MARKS = ENDSCOPE_STOP_ENTRY, STOP_PIG_TYPE2_HANDLER, STOP_PIG_TYPE3_HANDLER, + STOP_PIG_TYPE5_HANDLER, STOP_PIG_TYPE6_HANDLER, SE_LESSTHAN8_DONE, SE_STOP_L2_CLKS, diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index eff1f817..9e82aca3 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -82,6 +82,8 @@ p9_sgpe_stop_entry() for(qloop = 0; qloop < MAX_QUADS; qloop++) { if ((G_sgpe_stop_record.group.qswu[VECTOR_ACTIVE] | + G_sgpe_stop_record.group.quad[VECTOR_RCLKE] | + G_sgpe_stop_record.group.quad[VECTOR_BLOCKE] | (~G_sgpe_stop_record.group.quad[VECTOR_CONFIG])) & BIT32(qloop)) { continue; @@ -125,9 +127,9 @@ p9_sgpe_stop_entry() G_sgpe_stop_record.state[qloop].req_state_q >= LEVEL_EQ_BASE) { // if resonant clock disable is completed, process stop11 entry - if (G_sgpe_stop_record.group.quad[VECTOR_RCLKE] & BIT32(qloop)) + if (G_sgpe_stop_record.group.quad[VECTOR_RCLKE] & BIT32((qloop + 16))) { - G_sgpe_stop_record.group.quad[VECTOR_RCLKE] &= ~BIT32(qloop); + G_sgpe_stop_record.group.quad[VECTOR_RCLKE] &= ~BIT32((qloop + 16)); // if during resonant clock disable, any exit occured, re-assert them, // but we are going to complete the stop11 entry prior to process it @@ -163,6 +165,9 @@ p9_sgpe_stop_entry() // send DB to Quad-Manager to disable the resonant clock else { + // from this point on, only process wakeup when stop11 is entered + G_sgpe_stop_record.group.quad[VECTOR_RCLKE] |= BIT32(qloop); + // assume ex0 core0 is good cindex = (qloop << 2); @@ -537,18 +542,6 @@ p9_sgpe_stop_entry() PK_TRACE_INF("SE.11A: Quad[%d] EX_PG[%d] Shutting Cache Down", qloop, ex); - PK_TRACE("Acquire cache PCB slave atomic lock"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), BITS64(0, 5)); - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), scom_data.value); - - if ((scom_data.words.upper & BITS32(0, 5)) != 0xC0000000) - { - PK_TRACE_ERR("ERROR: Failed to Obtain Cache %d PCB Slave Atomic Lock. Register Content: %x", - qloop, scom_data.words.upper); - SGPE_STOP_QUAD_ERROR_HANDLER(qloop, SGPE_STOP_ENTRY_GET_SLV_LOCK_FAILED); - continue; - } - PK_TRACE("Update QSSR: stop_entry_ongoing"); out32(OCB_QSSR_OR, BIT32(qloop + 20)); @@ -739,17 +732,6 @@ p9_sgpe_stop_entry() { PK_TRACE_INF("Abort: L3 Purge Aborted"); - PK_TRACE("Release cache PCB slave atomic lock"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), 0); - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), scom_data.value); - - if (scom_data.words.upper & BIT32(0)) - { - PK_TRACE_ERR("ERROR: Failed to Release Cache %d PCB Slave Atomic Lock. Register Content: %x", - qloop, scom_data.words.upper); - PK_PANIC(SGPE_STOP_EXIT_DROP_SLV_LOCK_FAILED); - } - // assume ex0 core0 is good cindex = (qloop << 2); @@ -851,6 +833,18 @@ p9_sgpe_stop_entry() MARK_TAG(SE_PURGE_PB, (32 >> qloop)) //================================== + PK_TRACE("Acquire cache PCB slave atomic lock"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), BITS64(0, 5)); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), scom_data.value); + + if ((scom_data.words.upper & BITS32(0, 5)) != 0xC0000000) + { + PK_TRACE_ERR("ERROR: Failed to Obtain Cache %d PCB Slave Atomic Lock. Register Content: %x", + qloop, scom_data.words.upper); + SGPE_STOP_QUAD_ERROR_HANDLER(qloop, SGPE_STOP_ENTRY_GET_SLV_LOCK_FAILED); + continue; + } + // Stopping CME first in case CME initiates Powerbus Traffic if (ex & FST_EX_IN_QUAD) diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c index 21be69af..ffc45738 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_exit.c @@ -803,9 +803,19 @@ p9_sgpe_stop_exit() continue; } - //================================== - MARK_TAG(SX_CME_BOOT, (32 >> qloop)) - //================================== + //======================================= + MARK_TAG(SX_RUNTIME_INITS, (32 >> qloop)) + //======================================= + + PK_TRACE_DBG("Cache RAS Runtime Scom"); + p9_hcd_cache_ras_runtime_scom(qloop); + + PK_TRACE_DBG("Cache OCC Runtime Scom"); + p9_hcd_cache_occ_runtime_scom(qloop); + + //========================= + MARK_TRAP(SX_ENABLE_ANALOG) + //========================= if(pSgpeImgHdr->g_sgpe_reserve_flags & SGPE_VDM_ENABLE_BIT_POS) { @@ -848,6 +858,10 @@ p9_sgpe_stop_exit() PK_TRACE("Assert inter-ppm settings via QPMMR[20,22,24,EX0PB:21,23,25,27]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(QPPM_QPMMR_OR, qloop), scom_data.value); + //================================== + MARK_TAG(SX_CME_BOOT, (32 >> qloop)) + //================================== + // Setting up cme_flags do { @@ -927,6 +941,18 @@ p9_sgpe_stop_exit() } } + PK_TRACE("Release cache PCB slave atomic lock"); + GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), 0); + GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), scom_data.value); + + if (scom_data.words.upper & BIT32(0)) + { + PK_TRACE_ERR("ERROR: Failed to Release Cache %d PCB Slave Atomic Lock. Register Content: %x", + qloop, scom_data.words.upper); + SGPE_STOP_QUAD_ERROR_HANDLER(qloop, SGPE_STOP_EXIT_DROP_SLV_LOCK_FAILED); + continue; + } + if (in32(OCB_OCCS2) & BIT32(CME_DEBUG_TRAP_ENABLE)) { PK_TRACE_INF("BREAK: Trap Before CME Boot"); @@ -943,34 +969,8 @@ p9_sgpe_stop_exit() GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(PPM_GPMMR_CLR, qloop), BIT64(15)); #endif - //======================================= - MARK_TAG(SX_RUNTIME_INITS, (32 >> qloop)) - //======================================= - - PK_TRACE_DBG("Cache RAS Runtime Scom"); - p9_hcd_cache_ras_runtime_scom(qloop); - - PK_TRACE_DBG("Cache OCC Runtime Scom"); - p9_hcd_cache_occ_runtime_scom(qloop); - - //========================= - MARK_TRAP(SX_ENABLE_ANALOG) - //========================= - #endif - PK_TRACE("Release cache PCB slave atomic lock"); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), 0); - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_QPPM_ATOMIC_LOCK, qloop), scom_data.value); - - if (scom_data.words.upper & BIT32(0)) - { - PK_TRACE_ERR("ERROR: Failed to Release Cache %d PCB Slave Atomic Lock. Register Content: %x", - qloop, scom_data.words.upper); - SGPE_STOP_QUAD_ERROR_HANDLER(qloop, SGPE_STOP_EXIT_DROP_SLV_LOCK_FAILED); - continue; - } - PK_TRACE("Update STOP history on quad[%d]: \ STOP exit completed, cache ready", qloop); scom_data.words.lower = 0; diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c index a5e79976..da7514fa 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c @@ -593,12 +593,17 @@ p9_sgpe_stop_init() #endif + PK_TRACE("Configure and Enable Fit Timer"); + out32(GPE_GPE3TSEL, BIT32(4)); + ppe42_fit_setup((PkIrqHandler)p9_sgpe_fit_handler, 0); + PK_TRACE_INF("Setup: Clear and Unmask Type 2/3/6 Interrupt"); - out32(OCB_OISR1_CLR, (BITS32(15, 2) | BIT32(19))); + out32(OCB_OISR1_CLR, (BITS32(15, 2) | BITS32(18, 2))); out32(OCB_OPITNPRA_CLR(2), BITS32(0, 24)); out32(OCB_OPITNPRA_CLR(3), BITS32(0, 24)); - out32(OCB_OPITNPRA_CLR(6), BITS32(0, 24)); - out32(OCB_OIMR1_CLR, (BITS32(15, 2) | BIT32(19))); + out32(OCB_OPITNPRA_CLR(5), BITS32(0, 24)); + out32(OCB_OPIT6PRB_CLR, BITS32(0, 6)); + out32(OCB_OIMR1_CLR, (BITS32(15, 2) | BITS32(18, 2))); //-------------------------------------------------------------------------- // SGPE Init Completed diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c index 3651f306..d439b827 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_irq_handlers.c @@ -57,11 +57,47 @@ SgpeStopRecord G_sgpe_stop_record __attribute__((section (".dump_ptrs"))) = }, // wof status {0, 0, 0}, + // fit status + {0}, // semaphores {{0, 0, 0}} }; +void +p9_sgpe_fit_handler() +{ + PK_TRACE("FIT: Handler Fired"); + + uint32_t tpending = in32(OCB_OPITNPRA(PIG_TYPE3)) | + in32(OCB_OPITNPRA(PIG_TYPE5)) | + in32(OCB_OPIT6PRB); + + // count to 10 times that stop8+ is not serviced, then block stop5 + if (G_sgpe_stop_record.wof.status_stop == STATUS_IDLE && tpending) + { + PK_TRACE("FIT: Stravation Counter: %d", G_sgpe_stop_record.fit.strave_counter); + + if (G_sgpe_stop_record.fit.strave_counter < 25) + { + G_sgpe_stop_record.fit.strave_counter++; + } + else + { + PK_TRACE_INF("FIT: Stop8+ Stravation Detected"); + G_sgpe_stop_record.fit.strave_counter = 0; + out32(OCB_OIMR1_OR, BIT32(15)); + g_oimr_override |= BIT64(47); + } + } + // reset counter if current processing stop8+ + else if (G_sgpe_stop_record.wof.status_stop == STATUS_PROCESSING) + { + G_sgpe_stop_record.fit.strave_counter = 0; + } +} + + void p9_sgpe_stop_suspend_db1_cme(uint32_t qloop, uint32_t msgid) @@ -259,7 +295,7 @@ p9_sgpe_ipi3_low_handler(void* arg, PkIrqId irq) static void -p9_sgpe_pig_type23_parser(const uint32_t type) +p9_sgpe_pig_cpayload_parser(const uint32_t type) { uint32_t timeout = 0; uint32_t qloop = 0; @@ -270,8 +306,7 @@ p9_sgpe_pig_type23_parser(const uint32_t type) uint32_t center = 0; uint32_t cpending = 0; uint32_t cpayload = 0; - uint32_t payload2 = 0; - uint32_t payload3 = 0; + uint32_t tpayload = 0; uint32_t vector_index = 0; uint32_t request_index = 0; uint32_t suspend_index = 0; @@ -322,10 +357,15 @@ p9_sgpe_pig_type23_parser(const uint32_t type) { cpayload = in32(OCB_OPIT2CN(cindex)); } - else + else if (type == 3) { cpayload = in32(OCB_OPIT3CN(cindex)); } + else + { + cpayload = in32(OCB_OPIT5CN(cindex)); + } + PK_TRACE_INF("Core[%d] sent PIG Type[%d] with Payload [%x]", cindex, type, cpayload); @@ -415,21 +455,22 @@ p9_sgpe_pig_type23_parser(const uint32_t type) // and process it instead of this phantom; if type 3 entry, then ignore both // as type3 needs to be hanndled in type3 handler while current is obvious type2 - if ((scom_data.words.upper & BIT32(13)) && cpayload == TYPE2_PAYLOAD_DECREMENTER_WAKEUP) + if ((scom_data.words.upper & BIT32(13)) && + (type == PIG_TYPE2) && + (cpayload == TYPE2_PAYLOAD_DECREMENTER_WAKEUP)) { - payload2 = in32(OCB_OPIT2CN(cindex)); - payload3 = in32(OCB_OPIT3CN(cindex)); + tpayload = in32(OCB_OPIT2CN(cindex)); - if ((!(payload2 & TYPE2_PAYLOAD_EXIT_EVENT)) && - (payload2 & TYPE2_PAYLOAD_STOP_LEVEL)) + if ((in32(OCB_OPITNPRA(PIG_TYPE2)) & BIT32(cindex)) && + (!(tpayload & TYPE2_PAYLOAD_EXIT_EVENT)) && + (tpayload & TYPE2_PAYLOAD_STOP_LEVEL)) { PK_TRACE_INF("WARNING: Leftover dec wakeup following by new TYPE2 entry PIG"); - cpayload = payload2; + cpayload = tpayload; } - else if ((!(payload3 & TYPE2_PAYLOAD_EXIT_EVENT)) && - (payload3 & TYPE2_PAYLOAD_STOP_LEVEL)) + else if (in32(OCB_OPITNPRA(PIG_TYPE3)) & BIT32(cindex)) { - PK_TRACE_INF("WARNING: Leftover dec wakeup following by new TYPE3 entry PIG"); + PK_TRACE_INF("WARNING: Leftover dec wakeup following by new TYPE3 PIG"); continue; } } @@ -440,16 +481,17 @@ p9_sgpe_pig_type23_parser(const uint32_t type) if (!(scom_data.words.upper & BIT32(13))) { // type2 duplicate wakeup can happen due to manual PCWU vs other HW wakeup - if (cpayload == TYPE2_PAYLOAD_DECREMENTER_WAKEUP) + if ((type == PIG_TYPE2) && (cpayload == TYPE2_PAYLOAD_DECREMENTER_WAKEUP)) { PK_TRACE_INF("WARNING: Ignore Phantom Software PC/Decrementer Wakeup PIG \ (already handoff cme by other wakeup"); } // otherwise PPM shouldnt send duplicate pig if wakeup is present + // also not suppose to handoff to cme if resclk is not enabled before(type5) else { - PK_TRACE_INF("ERROR: Received Phantom Hardware Type2/3 Wakeup PIG \ - When Wakeup_notify_select = 0. HALT SGPE!"); + PK_TRACE_INF("ERROR: Received Phantom Hardware Type%d Wakeup PIG \ + When Wakeup_notify_select = 0. HALT SGPE!", type); PK_PANIC(SGPE_PIG_TYPE23_EXIT_WNS_CME); } } @@ -457,25 +499,31 @@ p9_sgpe_pig_type23_parser(const uint32_t type) { // if wakeup by pc_intr_pending, // go exit with flag to do extra doorbell from normal wakeup - if (cpayload == TYPE2_PAYLOAD_DECREMENTER_WAKEUP) + if ((type == PIG_TYPE2) && (cpayload == TYPE2_PAYLOAD_DECREMENTER_WAKEUP)) { PK_TRACE_INF("Core Request Exit with Decrementer Wakeup"); G_sgpe_stop_record.group.core[VECTOR_PCWU] |= BIT32(cindex); } - // Quad-Manager completed the resonant clock enable, proceed stop5 exit - if (cpayload == TYPE2_PAYLOAD_EXIT_RCLK) + // if having ongoing stop11 in resclk disable phase, hold on to all exits + if (G_sgpe_stop_record.group.quad[VECTOR_RCLKE] & BIT32(qloop)) { - PK_TRACE_INF("Core Request Exit Allowed as Resonant Clock Enable is Completed"); - G_sgpe_stop_record.group.quad[VECTOR_RCLKX] &= ~BIT32(qloop); - } + if ((type == PIG_TYPE5) && (cpayload == TYPE5_PAYLOAD_EXIT_RCLK)) + { + PK_TRACE_ERR("ERROR: IMPOSSIBLE! RCLK PROTOCOL BROKEN! HALT SGPE!"); + pk_halt(); + } - if (G_sgpe_stop_record.group.quad[VECTOR_BLOCKX] & BIT32(qloop)) + PK_TRACE_INF("Core Request Exit But Resonent Clock Disable Ongoing so ignore"); + G_sgpe_stop_record.group.core[VECTOR_RCLKE] |= BIT32(cindex); + } + else if (G_sgpe_stop_record.group.quad[VECTOR_BLOCKX] & BIT32(qloop)) { PK_TRACE_DBG("Core Request Exit But in Block Wakeup Mode so Ignore"); - if (cpayload == TYPE2_PAYLOAD_EXIT_RCLK) + if ((type == PIG_TYPE5) && (cpayload == TYPE5_PAYLOAD_EXIT_RCLK)) { + G_sgpe_stop_record.group.quad[VECTOR_RCLKX] &= ~BIT32(qloop); G_sgpe_stop_record.group.core[VECTOR_BLOCKX] |= G_sgpe_stop_record.group.core[VECTOR_RCLKX]; } @@ -484,36 +532,23 @@ p9_sgpe_pig_type23_parser(const uint32_t type) G_sgpe_stop_record.group.core[VECTOR_BLOCKX] |= BIT32(cindex); } } - // FIXME exit unblock above can bypass rclk exit block - else if (G_sgpe_stop_record.group.quad[VECTOR_RCLKE] & BIT32(qloop)) + // Quad-Manager completed the resonant clock enable, proceed stop5 exit is now allowed + else if ((type == PIG_TYPE5) && (cpayload == TYPE5_PAYLOAD_EXIT_RCLK)) { - if (cpayload == TYPE2_PAYLOAD_EXIT_RCLK) - { - PK_TRACE_ERR("ERROR: IMPOSSIBLE! RCLK PROTOCOL BROKEN! HALT SGPE!"); - pk_halt(); - } - - PK_TRACE_INF("Core Request Exit But Resonent Clock Disable Ongoing so Ignore"); - G_sgpe_stop_record.group.core[VECTOR_RCLKE] |= BIT32(cindex); + PK_TRACE_INF("Core Request Exit Allowed as Resonant Clock Enable is Completed"); + G_sgpe_stop_record.group.quad[VECTOR_RCLKX] &= ~BIT32(qloop); + G_sgpe_stop_record.group.core[VECTOR_PIGX] |= + G_sgpe_stop_record.group.core[VECTOR_RCLKX]; } else { PK_TRACE_INF("Core Request Exit Confirmed"); + G_sgpe_stop_record.group.core[VECTOR_PIGX] |= BIT32(cindex); - if (cpayload == TYPE2_PAYLOAD_EXIT_RCLK) - { - G_sgpe_stop_record.group.core[VECTOR_PIGX] |= - G_sgpe_stop_record.group.core[VECTOR_RCLKX]; - } - else - { - G_sgpe_stop_record.group.core[VECTOR_PIGX] |= BIT32(cindex); - - PK_TRACE("Update STOP history on core: in transition of exit"); - scom_data.words.upper = SSH_EXIT_IN_SESSION; - scom_data.words.lower = 0; - GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, cindex, 0, scom_data.value); - } + PK_TRACE("Update STOP history on core: in transition of exit"); + scom_data.words.upper = SSH_EXIT_IN_SESSION; + scom_data.words.lower = 0; + GPE_PUTSCOM_VAR(PPM_SSHSRC, CORE_ADDR_BASE, cindex, 0, scom_data.value); } } } @@ -537,10 +572,13 @@ p9_sgpe_pig_type23_parser(const uint32_t type) } // Quad-Manager completed the resonant clock disable, proceed stop11 entry - if (cpayload == (TYPE2_PAYLOAD_ENTRY_RCLK | STOP_LEVEL_11)) + // block entry protocol is checked in the entry code instead of here below + if ((type == PIG_TYPE5) && + (cpayload == (TYPE5_PAYLOAD_ENTRY_RCLK | STOP_LEVEL_11))) { PK_TRACE_INF("Core Request Entry Allowed as Resonant Clock Disable is Completed"); - G_sgpe_stop_record.group.quad[VECTOR_RCLKE] |= BIT32(qloop); + G_sgpe_stop_record.group.quad[VECTOR_RCLKE] &= ~BIT32(qloop); + G_sgpe_stop_record.group.quad[VECTOR_RCLKE] |= BIT32((qloop + 16)); } if (G_sgpe_stop_record.group.quad[VECTOR_BLOCKE] & BIT32(qloop)) @@ -665,6 +703,50 @@ p9_sgpe_pig_type23_parser(const uint32_t type) +static void +p9_sgpe_pig_thread_lanucher() +{ + PkMachineContext ctx; + + // clear group before analyzing input + G_sgpe_stop_record.group.core[VECTOR_ENTRY] = 0; + G_sgpe_stop_record.group.core[VECTOR_EXIT] = 0; + + // Taking Stop8/11 Actions if any + if (G_sgpe_stop_record.group.core[VECTOR_PIGX] || + G_sgpe_stop_record.group.core[VECTOR_PIGE]) + { + // block both type3 and type5, 6 + // so another doesnt interrupt until next round + out32(OCB_OIMR1_OR, (BIT32(16) | BITS32(18, 2))); + g_oimr_override |= (BIT64(48) | BITS64(50, 2)); + + if (G_sgpe_stop_record.group.core[VECTOR_PIGX]) + { + PK_TRACE_INF("Unblock Exit Thread"); + G_sgpe_stop_record.group.core[VECTOR_EXIT] = + G_sgpe_stop_record.group.core[VECTOR_PIGX]; + pk_semaphore_post(&(G_sgpe_stop_record.sem[1])); + } + + if (G_sgpe_stop_record.group.core[VECTOR_PIGE]) + { + PK_TRACE_INF("Unblock Entry Thread"); + G_sgpe_stop_record.group.core[VECTOR_ENTRY] = + G_sgpe_stop_record.group.core[VECTOR_PIGE]; + pk_semaphore_post(&(G_sgpe_stop_record.sem[0])); + } + } + else + { + PK_TRACE_INF("Nothing to do, Enable Interrupts"); + g_oimr_override &= ~BIT64(47); + pk_irq_vec_restore(&ctx); + } +} + + + void p9_sgpe_pig_type2_handler(void* arg, PkIrqId irq) { @@ -679,7 +761,7 @@ p9_sgpe_pig_type2_handler(void* arg, PkIrqId irq) out32(OCB_OISR1_CLR, BIT32(15)); // Parse Type2 Requests - p9_sgpe_pig_type23_parser(2); + p9_sgpe_pig_cpayload_parser(PIG_TYPE2); // Enable Interrupts pk_irq_vec_restore(&ctx); @@ -690,8 +772,6 @@ p9_sgpe_pig_type2_handler(void* arg, PkIrqId irq) void p9_sgpe_pig_type3_handler(void* arg, PkIrqId irq) { - PkMachineContext ctx; - //=============================== MARK_TRAP(STOP_PIG_TYPE3_HANDLER) //=============================== @@ -700,46 +780,34 @@ p9_sgpe_pig_type3_handler(void* arg, PkIrqId irq) // Clear Type3 Interrupt out32(OCB_OISR1_CLR, BIT32(16)); - // Parse Type2 Requests - p9_sgpe_pig_type23_parser(3); + // Parse Type3 Requests + p9_sgpe_pig_cpayload_parser(PIG_TYPE3); - // clear group before analyzing input - G_sgpe_stop_record.group.core[VECTOR_ENTRY] = 0; - G_sgpe_stop_record.group.core[VECTOR_EXIT] = 0; + // decide if launch the thread + p9_sgpe_pig_thread_lanucher(); +} - // Taking Stop8/11 Actions if any - if (G_sgpe_stop_record.group.core[VECTOR_PIGX] || - G_sgpe_stop_record.group.core[VECTOR_PIGE]) - { - // block both type3 and type6 - // so another doesnt interrupt until next round - out32(OCB_OIMR1_OR, (BIT32(16) | BIT32(19))); - g_oimr_override |= (BIT64(48) | BIT64(51)); - if (G_sgpe_stop_record.group.core[VECTOR_PIGX]) - { - PK_TRACE_INF("Unblock Exit Thread"); - G_sgpe_stop_record.group.core[VECTOR_EXIT] = - G_sgpe_stop_record.group.core[VECTOR_PIGX]; - pk_semaphore_post(&(G_sgpe_stop_record.sem[1])); - } +void +p9_sgpe_pig_type5_handler(void* arg, PkIrqId irq) +{ + //=============================== + MARK_TRAP(STOP_PIG_TYPE5_HANDLER) + //=============================== + PK_TRACE_DBG("PIG-TYPE5: %d", irq); - if (G_sgpe_stop_record.group.core[VECTOR_PIGE]) - { - PK_TRACE_INF("Unblock Entry Thread"); - G_sgpe_stop_record.group.core[VECTOR_ENTRY] = - G_sgpe_stop_record.group.core[VECTOR_PIGE]; - pk_semaphore_post(&(G_sgpe_stop_record.sem[0])); - } - } - else - { - PK_TRACE_INF("Nothing to do, Enable Interrupts"); - pk_irq_vec_restore(&ctx); - } + // Clear Type5 Interrupt + out32(OCB_OISR1_CLR, BIT32(18)); + + // Parse Type5 Requests + p9_sgpe_pig_cpayload_parser(PIG_TYPE5); + + // decide if launch the thread + p9_sgpe_pig_thread_lanucher(); } + void p9_sgpe_pig_type6_handler(void* arg, PkIrqId irq) { @@ -829,10 +897,10 @@ p9_sgpe_pig_type6_handler(void* arg, PkIrqId irq) if (G_sgpe_stop_record.group.qswu[VECTOR_EXIT] || G_sgpe_stop_record.group.qswu[VECTOR_ENTRY]) { - // block both type3 and type6 + // block both type3 and type5, 6 // so another doesnt interrupt until next round - out32(OCB_OIMR1_OR, (BIT32(16) | BIT32(19))); - g_oimr_override |= (BIT64(48) | BIT64(51)); + out32(OCB_OIMR1_OR, (BIT32(16) | BITS32(18, 2))); + g_oimr_override |= (BIT64(48) | BITS64(50, 2)); if (G_sgpe_stop_record.group.qswu[VECTOR_EXIT]) { @@ -849,6 +917,7 @@ p9_sgpe_pig_type6_handler(void* arg, PkIrqId irq) else { PK_TRACE_INF("Nothing to do, Enable Interrupts"); + g_oimr_override &= ~BIT64(47); pk_irq_vec_restore(&ctx); } } diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_threads.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_threads.c index f44f5c18..87b64191 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_threads.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_threads.c @@ -28,8 +28,6 @@ extern SgpeStopRecord G_sgpe_stop_record; - - void p9_sgpe_stop_exit_thread(void* arg) { @@ -67,8 +65,8 @@ p9_sgpe_stop_exit_thread(void* arg) p9_sgpe_ack_pgpe_ctrl_stop_updates(); } - PK_TRACE_INF("Setup: Exit Done,no Entry Request.Enable Type2/3/6 Interrupt"); - g_oimr_override &= ~(BIT64(48) | BIT64(51)); + PK_TRACE_INF("Setup: Exit Done,no Entry Request.Enable Type2/3/5/6 Interrupt"); + g_oimr_override &= ~(BITS64(47, 2) | BITS64(50, 2)); pk_irq_vec_restore(&ctx); #if !SKIP_IPC @@ -117,8 +115,8 @@ p9_sgpe_stop_enter_thread(void* arg) p9_sgpe_ack_pgpe_ctrl_stop_updates(); } - PK_TRACE_INF("Setup: Entry done. Enable Type2/3/6 Interrupt"); - g_oimr_override &= ~(BIT64(48) | BIT64(51)); + PK_TRACE_INF("Setup: Entry done. Enable Type2/3/5/6 Interrupt"); + g_oimr_override &= ~(BITS64(47, 2) | BITS64(50, 2)); pk_irq_vec_restore(&ctx); #if !SKIP_IPC diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h index f6c1ada3..f544d168 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/pk_app_cfg.h @@ -147,8 +147,9 @@ OCCHW_IRQ_CHECK_STOP_GPE3 OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ OCCHW_IRQ_IPI3_HI_PRIORITY OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ OCCHW_IRQ_IPI3_LO_PRIORITY OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ - OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING OCCHW_IRQ_TYPE_LEVEL OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ - OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING OCCHW_IRQ_TYPE_LEVEL OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED \ + OCCHW_IRQ_PMC_PCB_INTR_TYPE2_PENDING OCCHW_IRQ_TYPE_LEVEL OCCHW_IRQ_POLARITY_HI OCCHW_IRQ_MASKED \ + OCCHW_IRQ_PMC_PCB_INTR_TYPE3_PENDING OCCHW_IRQ_TYPE_LEVEL OCCHW_IRQ_POLARITY_HI OCCHW_IRQ_MASKED \ + OCCHW_IRQ_PMC_PCB_INTR_TYPE5_PENDING OCCHW_IRQ_TYPE_LEVEL OCCHW_IRQ_POLARITY_HI OCCHW_IRQ_MASKED \ OCCHW_IRQ_PMC_PCB_INTR_TYPE6_PENDING OCCHW_IRQ_TYPE_EDGE OCCHW_IRQ_POLARITY_RISING OCCHW_IRQ_MASKED // -------------------- |
