diff options
9 files changed, 353 insertions, 72 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index aea5a525..26353bac 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -94,12 +94,10 @@ HCD_HDR_UINT32( quadCmnRingOccOffset, 0); HCD_HDR_UINT32( quadSpecRingOccOffset, 0); HCD_HDR_UINT32( quadCmnScomOccOffset, 0); HCD_HDR_PAD(512); -//HCD_HDR_PAD(QPMR_HEADER_SIZE); #ifdef __ASSEMBLER__ .endm #else } __attribute__((packed, aligned(512))) QpmrHeaderLayout_t; -//} __attribute__((packed, aligned(QPMR_HEADER_SIZE))) QpmrHeaderLayout_t; #endif // @todo Get around the above hardcoding. @@ -138,12 +136,10 @@ HCD_HDR_UINT32( coreSpecRingLength, 0); HCD_HDR_UINT32( coreScomOffset, 0); HCD_HDR_UINT32( coreScomLength, 0); HCD_HDR_PAD(256); -//HCD_HDR_PAD(CPMR_HEADER_SIZE); #ifdef __ASSEMBLER__ .endm #else } __attribute__((packed, aligned(256))) cpmrHeader_t; -//} __attribute__((packed, aligned(CPMR_HEADER_SIZE))) cpmrHeader_t; #endif // @todo Get around the above hardcoding. @@ -180,9 +176,11 @@ HCD_HDR_UINT64(g_sgpe_reserve_flags, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_ovrd_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_spec_ring_occ_offset, 0); -HCD_HDR_UINT32(g_sgpe_spec_ring_ovrd_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_cmn_scom_offset, 0); -HCD_HDR_UINT32(g_sgpe_reserve3, 0); +HCD_HDR_UINT32(g_sgpe_cmn_scom_mem_offset, 0); +HCD_HDR_UINT32(g_sgpe_cmn_scom_length, 0); +HCD_HDR_UINT32(g_sgpe_24x7_offset, 0); +HCD_HDR_UINT32(g_sgpe_24x7_length, 0); HCD_HDR_PAD(IMG_HDR_ALIGN_SIZE); #ifdef __ASSEMBLER__ .endm @@ -299,6 +297,7 @@ enum MAX_CME_PER_CHIP = 12, MAX_CACHE_CHIPLETS = 6, CACH0_CHIPLET_ID = 0x10, + MAX_CORES_PER_EX = 2, CORE0_CHIPLET_ID = 0x20, PAD_OPCODE = 0x00000200, //ATTN Opcode PPE_RESERVE_AREA = 0x200, @@ -316,11 +315,9 @@ enum //** Hcode SGPE_INT_VECT = 384, - //SGPE_IMG_HEADER = 64, SGPE_IMG_HEADER = sizeof(sgpeHeader_t), SGPE_DBG_PTR_AREA_SIZE = 64, - //SGPE_HCODE_SIZE = 32 * ONE_KB, // FIXME RTC 155018 Revisit after Hcode optimization - SGPE_HCODE_SIZE = 45 * ONE_KB, // @todo RTC 158543 Reallocate space + SGPE_HCODE_SIZE = (45 * ONE_KB) + HALF_KB, // @todo RTC 158543 Reallocate space SGPE_EXE_SIZE = (SGPE_HCODE_SIZE - ( SGPE_INT_VECT + SGPE_IMG_HEADER + PK_DBG_PTR_AREA_SIZE )), @@ -328,17 +325,17 @@ enum SGPE_ALLOCATED_SIZE = SGPE_HCODE_SIZE, // @todo RTC 158543 Reallocate space (collapse??) //** Scan - //SGPE_COMMON_RING = 13 * ONE_KB, // Common rings (10KB) + Override rings(3KB) SGPE_COMMON_RING_SIZE = 13 * ONE_KB, // 400B * 9 rings * 3 types (base, RL, CC) SGPE_OVERRIDE_RING_SIZE = 3 * ONE_KB, // 300B * 9 rings CACHE_INST_SPECIFIC_SIZE = (3 * ONE_KB) + HALF_KB, // per cache, 1KB/ring x 5 rings/cache - CACHE_SPECIFIC_RING_SIZE = MAX_CACHE_CHIPLETS * CACHE_INST_SPECIFIC_SIZE, SGPE_INSTRUMENTATION_SIZE = 2 * ONE_KB, + MAX_CACHE_CHIPLET = 6, + MAX_QUAD_SPEC_RING_SIZE = 19 * ONE_KB, //** SCOM NUM_CACHE_SCOM_REGS = 47 + 1, // 16 L2 repr, 16 L3 repr, 15 non-repr, 1 NULL - CACHE_SCOM_RESTORE_SIZE = MAX_CACHE_CHIPLETS * NUM_CACHE_SCOM_REGS * SCOM_ENTRY_SIZE, + CACHE_SCOM_RESTORE_SIZE = 6 * ONE_KB, //4488B rounded to 6KB CACHE_SCOM_START = 128 * ONE_KB, // HOMER offset from QPMR @@ -363,35 +360,28 @@ enum //** SCOM CORE_SCOM_START = (256 * ONE_KB), CORE_SCOM_RESTORE_SIZE = SCOM_ENTRY_SIZE * 16, // (15 registers + 1 NULL) per core - CORE_SCOM_RES_SIZE = CORE_SCOM_RESTORE_SIZE * MAX_CORES_PER_CHIP, CME_SCOM_AREA = CORE_SCOM_RESTORE_SIZE * 2, // 2 cores SCOM_AREA_PER_CME = HALF_KB, // 256(ea ) * 2( CORES PER CME) (???) //** Hcode + CORE_SCOM_PER_CME = 512, + CORE_SCOM_RES_SIZE = MAX_CME_PER_CHIP * SCOM_AREA_PER_CME, CME_INT_VECTOR_SIZE = 384, CME_IMG_HEADER_SIZE = 64, CPMR_CME_HCODE_OFFSET = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), - CME_HCODE_SIZE = (28 * ONE_KB) + HALF_KB, + CME_HCODE_SIZE = (30 * ONE_KB), //FIXME RTC 159737 Needs review before merge of P-State //** Scan - CORE_COMMON_RING_SIZE = 3 * ONE_KB, // common ring( 2KB) + common overrides (1KB) - CORE_SPECIFIC_RING = 2 * ONE_KB, // per core + CORE_COMMON_RING_SIZE = 1 * ONE_KB, // common ring( 2KB) + common overrides (1KB) + MAX_SIZE_CME_INST_RING = 1 * ONE_KB, CORE_OVERRIDE_RING = 1 * ONE_KB, // common for all cores QUAD_PSTATE_SIZE = HALF_KB, // common for all cores CME_INSTRUMENTATION_SIZE = HALF_KB, // per CME INSTRUMENTATION_COUNTERS = HALF_KB, // (???) - - CORE_RESERVE_SIZE = CORE_SCOM_START - - ( CORE_RESTORE_SIZE + - CME_HCODE_SIZE + - CORE_COMMON_RING_SIZE + - QUAD_PSTATE_SIZE ), - CME_SRAM_HCODE_OFFSET = 0x00, //(???) - CME_REGION_START = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), CME_INST_SPEC_RING_START = 300 * ONE_KB, - RESERVE_CME_RING_AREA = ( CME_INST_SPEC_RING_START - - (CME_REGION_START + + CME_REGION_START = (CORE_SCOM_START + CORE_SCOM_RES_SIZE), + RESERVE_CME_RING_AREA = ( CME_INST_SPEC_RING_START - ( CME_REGION_START + CME_HCODE_SIZE + CORE_COMMON_RING_SIZE + QUAD_PSTATE_SIZE)), @@ -407,10 +397,13 @@ enum PGPE_HCODE_SIZE = 30 * ONE_KB, PGPE_PARAM_BLOCK_SIZE = 8 * ONE_KB, //Global and OCC PPB PSTATE_OUTPUT_TABLE = 8 * ONE_KB, - IGNORE_CHIPLET_INSTANCE = 0xFF, PGPE_MAX_AREA_SIZE = 48 * ONE_KB, // @todo RTC 158543 Reallocate space + IGNORE_CHIPLET_INSTANCE = 0xFF, + + //RING LAYOUT + RING_ALIGN_BOUNDARY = 0x08, }; /** @@ -446,9 +439,159 @@ enum ImgBldRetCode_t BUILD_FAIL_PGPE_BL2 = 25, BUILD_FAIL_PGPE_HCODE = 26, BUILD_FAIL_OVERRIDE = 27, + BUILD_SEC_SIZE_OVERFLOW = 28, + BUILD_FAIL_INVALID_SECTN = 29, + BUILD_FAIL_RING_EXTRACTN = 30, }; /** + * @brief models layout of core common rings in HOMER. + * @note Ring list below is primarily for debug. + */ +typedef struct +{ + uint16_t ecFuncRing; + uint16_t ecGptrRing; + uint16_t ecTimeRing; + uint16_t ecModeRing; +} CoreCmnRingsList_t; + +typedef struct +{ + CoreCmnRingsList_t cmnRings; + uint8_t cmnScanRingPayload[CORE_COMMON_RING_SIZE - sizeof(CoreCmnRingsList_t)]; +} CoreCmnRingsCme_t; + +typedef union +{ + CoreCmnRingsCme_t cmnRingIndex; + uint8_t cmnScanRings[CORE_COMMON_RING_SIZE]; +} CoreCmnRingLayout_t; + +/** + * @brief models layout of core instance specific ring in HOMER. + * @note Ring list below is primarily for debug. + */ +typedef struct +{ + uint16_t ecRepr0; + uint16_t ecRepr1; + uint8_t ecReserve[4]; +} CoreSpecRingList_t; +typedef struct +{ + CoreSpecRingList_t coreSpecRings; + uint8_t instanceRingPayLoad[ MAX_SIZE_CME_INST_RING - sizeof(CoreSpecRingList_t)]; +} CoreSpecRingCme_t; + +typedef union +{ + CoreSpecRingCme_t instRingIndex; + uint8_t instScanRings[ MAX_SIZE_CME_INST_RING ]; +} CoreSpecRingLayout_t; + +/** + * @brief models layout of quad common rings in HOMER. + * @note this layout resides in QPMR region and is consumed by SGPE. + * Ring list below is primarily for debug. + */ + +typedef struct +{ + uint16_t eqFureRing; + uint16_t eqGptrRing; + uint16_t eqTimeRing; + uint16_t eqModeRing; + uint16_t exL3FureRing; + uint16_t exL3GptrRing; + uint16_t exL3TimeRing; + uint16_t exL2ModeRing; + uint16_t exL2FureRing; + uint16_t exL2GptrRing; + uint16_t exL2TimeRing; + uint16_t exL3RefrFureRing; + uint16_t exL3RefrGptrRing; + uint16_t eqAnaFuncRing; + uint16_t eqAnaGptrRing; + uint16_t eqDpllFuncRing; + uint16_t eqDpllGptrRing; + uint16_t eqDpllModeRing; + uint16_t eqAnaBndyRingBucket0; + uint16_t eqAnaBndyRingBucket1; + uint16_t eqAnaBndyRingBucket2; + uint16_t eqAnaBndyRingBucket3; + uint16_t eqAnaBndyRingBucket4; + uint16_t eqAnaBndyRingBucket5; + uint16_t eqAnaBndyRingBucket6; + uint16_t eqAnaBndyRingBucket7; + uint16_t eqAnaBndyRingBucket8; + uint16_t eqAnaBndyRingBucket9; + uint16_t eqAnaBndyRingBucket10; + uint16_t eqAnaBndyRingBucket11; + uint16_t eqAnaBndyRingBucket12; + uint16_t eqAnaBndyRingBucket13; + uint16_t eqAnaBndyRingBucket14; + uint16_t eqAnaBndyRingBucket15; + uint16_t eqAnaBndyRingBucket16; + uint16_t eqAnaBndyRingBucket17; + uint16_t eqAnaBndyRingBucket18; + uint16_t eqAnaBndyRingBucket19; + uint16_t eqAnaBndyRingBucket20; + uint16_t eqAnaBndyRingBucket21; + uint16_t eqAnaBndyRingBucket22; + uint16_t eqAnaBndyRingBucket23; + uint16_t eqAnaBndyRingBucket24; + uint16_t eqAnaBndyRingBucket25; + uint16_t eqAnaBndyRingl3dccBucket26; + uint16_t eqAnaModeRing; + uint16_t ex_l2_fure_1; + uint16_t ex_l3_fure_1; +} QuadCmnRingsList_t; + +typedef struct +{ + QuadCmnRingsList_t quadCmnRingList; + uint8_t cmnRingPayLoad[SGPE_COMMON_RING_SIZE - sizeof(QuadCmnRingsList_t)]; +} QuadCmnRingsSgpe_t; + +typedef union +{ + QuadCmnRingsSgpe_t cmnRingIndex; + uint8_t cmnScanRings[SGPE_COMMON_RING_SIZE]; +} CmnRingLayoutSgpe_t; + +/** + * @brief models layout of quad/ex instance specific ring in HOMER. + * @note this layout resides in QPMR region and is consumed by SGPE. + * Ring list below is primarily for debug. + */ +typedef struct +{ + uint16_t eqRepr0Index; + uint16_t ex0L3ReprIndex; + uint16_t ex1L3ReprIndex; + uint16_t ex0L2ReprIndex; + uint16_t ex1L2ReprIndex; + uint16_t ex0L3RefrReprIndex; + uint16_t ex1L3RefrReprIndex; + uint16_t ex0L3RefrTimeIndex; + uint16_t ex1L3RefrTimeIndex; + uint8_t eqReserve[6]; +} QuadSpecRingsList_t; + +typedef struct +{ + QuadSpecRingsList_t quadSpecRings[MAX_CACHE_CHIPLET]; + uint8_t quadSpecRingPayLoad[ MAX_QUAD_SPEC_RING_SIZE - (MAX_CACHE_CHIPLET * sizeof(QuadSpecRingsList_t))]; +} QuadSpecRing_t; + +typedef union +{ + QuadSpecRing_t instRingIndex; + uint8_t instScanRings[ MAX_QUAD_SPEC_RING_SIZE ]; +} InstRingLayoutSgpe_t; + +/** * @brief models image section of SGPE in HOMER. */ typedef struct @@ -460,10 +603,8 @@ typedef struct uint8_t imgHeader[sizeof(sgpeHeader_t)]; uint8_t debugPtrs[PK_DBG_PTR_AREA_SIZE]; uint8_t hcode[SGPE_EXE_SIZE]; - uint8_t commonRings[SGPE_COMMON_RING_SIZE]; - uint8_t cacheSpecificRing[CACHE_SPECIFIC_RING_SIZE]; - uint8_t overrideRings[SGPE_OVERRIDE_RING_SIZE]; - uint8_t cacheScomRestore[CACHE_SCOM_RESTORE_SIZE]; + CmnRingLayoutSgpe_t quadCmnRingArea; + InstRingLayoutSgpe_t quadSpecRingArea; } SgpeLayout_t; typedef union CPMRSelfRestoreLayout @@ -501,12 +642,12 @@ typedef union CmeHcodeLayout typedef struct { - SelfRestoreLayout_t selfRestoreRegion; - CmeHcodeLayout_t cmeBin; - uint8_t commonRings[CORE_COMMON_RING_SIZE]; - uint8_t quadPstateArea[QUAD_PSTATE_SIZE]; - uint8_t resvRingArea[RESERVE_CME_RING_AREA]; - uint8_t instSpecificRing[MAX_CORES_PER_CHIP * CORE_SPECIFIC_RING]; + SelfRestoreLayout_t selfRestoreRegion; + CmeHcodeLayout_t cmeBin; + CoreCmnRingLayout_t coreCmnRingArea; + uint8_t quadPstateArea[QUAD_PSTATE_SIZE]; + uint8_t resvRingArea[RESERVE_CME_RING_AREA]; + CoreSpecRingLayout_t coreSpecRingArea[MAX_CME_PER_CHIP]; } CPMRLayout_t; /** diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c index c54a64bd..f4f975a0 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_copy_scan_ring.c @@ -63,7 +63,7 @@ void instance_scan_init( ) //calculate start address of block copy and length of block copy l_bcLength = pCmeImgHdr->g_cme_max_spec_ring_length; // integral multiple of 32. //let us find out HOMER address where core specific scan rings reside. - l_bceMbase = l_bceMbase + ( l_cmePir * l_bcLength ); + l_bceMbase = l_bceMbase + (( l_cmePir * l_bcLength ) << 5 ); l_bceMbase = (l_bceMbase >> 5 ); // calculate the CME SRAM destination block number(SBASE) diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_repair_initf.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_repair_initf.c index f88ca770..013e85a3 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_repair_initf.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_hcd_core_repair_initf.c @@ -23,13 +23,38 @@ /* */ /* IBM_PROLOG_END_TAG */ + +#include "plat_ring_traverse.h" #include "p9_cme_stop.h" #include "p9_cme_stop_exit_marks.h" - +#include "p9_ringid_cme_enums.h" int p9_hcd_core_repair_initf(uint32_t core) { int rc = CME_STOP_SUCCESS; + int i = 0; + // Markers needed for repair ininf + if (core == 3) + { + for (i = 0; i < 2; ++i) + { + core = 2; + + if (i) + { + core = 1; + } + + PK_TRACE("Scan ec_repr ring core value %d", core); + putRing(core, CME_SCOM_EQ, ec_repr); + } + } + else + { + PK_TRACE("Scan ec_repr ring core value %d", core); + putRing(core, CME_SCOM_EQ, ec_repr); + } + return rc; } diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c index 20254411..d973bfc7 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c +++ b/import/chips/p9/procedures/ppe_closed/cme/utils/p9_putringutils.c @@ -379,7 +379,8 @@ int rs4DecompressionSvc( if(l_readHeader != 0xa5a5a5a5a5a5a5a5) { - MY_TRACE_ERR ("Check word data mismatch"); + PK_TRACE("Check word data mismatch"); + pk_halt(); } else { diff --git a/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c b/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c index f083131c..0694b4fe 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c +++ b/import/chips/p9/procedures/ppe_closed/cme/utils/plat_ring_traverse.c @@ -81,9 +81,10 @@ int putRing( l_chipletData.iv_num_variants = 0; uint8_t l_chipletID = 0; uint32_t* l_sectionAddr; + uint16_t* l_ringTorAddr; + getRingProperties(i_ringID, &l_torOffset, &l_ringType); - PK_TRACE ("Inside putring ringId %d ringtype %d", i_ringID, l_ringType); CmeHcodeLayout_t* l_hcodeLayout = (CmeHcodeLayout_t*)(CME_SRAM_BASE); @@ -95,19 +96,26 @@ int putRing( if(INSTANCE_RING == l_ringType) { + uint8_t l_core = 1; + if (!(l_cmeHeader->g_cme_core_spec_ring_offset)) { break; } l_sectionAddr = - (uint32_t*)(CME_SRAM_BASE + l_cmeHeader->g_cme_core_spec_ring_offset); + (uint32_t*)(CME_SRAM_BASE + (l_cmeHeader->g_cme_core_spec_ring_offset * 32)); + + if (i_core == 2) + { + l_core = 0; + } - l_chipletID = i_core + l_chipletData.iv_base_chiplet_number; + l_chipletID = l_core + l_chipletData.iv_base_chiplet_number; uint8_t l_chipletOffset = (l_chipletID - l_chipletData.iv_base_chiplet_number); - l_sectionAddr += (l_chipletOffset * - l_chipletData.iv_num_instance_rings); + l_ringTorAddr = (uint16_t*)(l_sectionAddr ) + ((l_chipletOffset * + l_chipletData.iv_num_instance_rings ) + (l_torOffset)); } else { @@ -118,19 +126,10 @@ int putRing( l_sectionAddr = (uint32_t*)(CME_SRAM_BASE + l_cmeHeader->g_cme_common_ring_offset); - } - - - // The ring variants in section TOR are expected to be in the sequence - - // 1. Base - // 2. Risk Level - - PK_TRACE("l_sectionAddr %08x", (uint32_t)l_sectionAddr); - - // TOR records of Ring TOR are 2 bytes in size. - uint16_t* l_ringTorAddr = (uint16_t*)(l_sectionAddr) + - (l_torOffset * l_chipletData.iv_num_variants); + // TOR records of Ring TOR are 2 bytes in size. + l_ringTorAddr = (uint16_t*)(l_sectionAddr) + (l_torOffset); + } if(*l_ringTorAddr != 0) { diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_repair_initf.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_repair_initf.C new file mode 100644 index 00000000..61637c21 --- /dev/null +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_repair_initf.C @@ -0,0 +1,95 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_repair_initf.C $ */ +/* */ +/* OpenPOWER HCODE Project */ +/* */ +/* COPYRIGHT 2015,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_repair_initf.C +/// @brief Load Repair ring for EX non-core +/// +/// Procedure Summary: +/// Load cache ring images from MVPD +/// These rings must contain ALL chip customization data. +/// This includes the following: Repair Power headers, and DTS +/// Historically this was stored in MVPD keywords are #R, #G. Still stored in +/// MVPD, but SBE image is customized with rings for booting cores + +// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com> +// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +// *HWP Team : PM +// *HWP Consumed by : SBE:SGPE +// *HWP Level : 2 + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include "p9_sgpe_stop.h" +#include "p9_sgpe_stop_exit_marks.h" +#include "hw_access.H" +#include "p9_ringid_sgpe.H" +#include <fapi2.H> + + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load Repair ring for cache +//------------------------------------------------------------------------------ + + +extern "C" int p9_hcd_cache_repair_initf(uint32_t quad) +{ + FAPI_INF(">>p9_hcd_cache_repair_initf"); + + int rc = SGPE_STOP_SUCCESS; + fapi2::Target<fapi2::TARGET_TYPE_EQ> l_eqTarget + ( + fapi2::plat_getTargetHandleByChipletNumber((uint8_t)quad + EQ_CHIPLET_OFFSET) + ); + + auto l_ex_targets = l_eqTarget.getChildren<fapi2::TARGET_TYPE_EX>(); + + PK_TRACE("Scan eq_repr ring"); + FAPI_TRY(fapi2::putRing(l_eqTarget, eq_repr)); + + for (auto l_ex : l_ex_targets) + { + PK_TRACE("Scan ex_l3_repr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_repr)); + + PK_TRACE("Scan ex_l2_repr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l2_repr)); + + PK_TRACE("Scan ex_l3_refr_repr ring"); + FAPI_TRY(fapi2::putRing(l_ex, ex_l3_refr_repr)); + } + + +fapi_try_exit: + + FAPI_INF("<<p9_hcd_cache_repair_initf"); + return rc; +} diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk index 61eded4b..1b25c814 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/topfiles.mk @@ -33,7 +33,6 @@ TOP-C-SOURCES = p9_sgpe_stop_entry.c \ p9_hcd_cache_gptr_time_initf.c \ p9_hcd_cache_dpll_setup.c \ p9_hcd_cache_chiplet_init.c \ - p9_hcd_cache_repair_initf.c \ p9_hcd_cache_arrayinit.c \ p9_hcd_cache_startclocks.c \ p9_hcd_cache_l2_startclocks.c \ @@ -53,6 +52,7 @@ TOP-CPP-SOURCES += p9_hcd_cache_initf.C TOP-CPP-SOURCES += p9_hcd_cache_dpll_initf.C TOP-CPP-SOURCES += p9_hcd_cache_chiplet_l3_dcc_setup.C TOP-CPP-SOURCES += p9_hcd_cache_dcc_skewadjust_setup.C +TOP-CPP-SOURCES += p9_hcd_cache_repair_initf.C UTILS_OBJECTS = $(UTILS-SRC:.C=.o) TOP_OBJECTS = $(TOP-C-SOURCES:.c=.o) $(TOP-S-SOURCES:.S=.o) $(TOP-CPP-SOURCES:.C=.o) diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C index 81095581..7afe6205 100755 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/p9_putringutils.C @@ -336,9 +336,14 @@ fapi2::ReturnCode verifyHeader(const fapi2::Target<fapi2::TARGET_TYPE_ALL>& { FAPI_ERR("Read header(%016x) data incorrect", uint64_t(l_readHeader)); l_rc = fapi2::FAPI2_RC_PLAT_ERR_RING_HEADER_CHECK; + pk_halt(); break; //PK_PANIC(0xFABD); } + else + { + PK_TRACE("CHECK word matched"); + } } while(0); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C index e05289d3..00e454ac 100755 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/utils/plat_ring_traverse.C @@ -56,6 +56,8 @@ fapi2::ReturnCode findRS4InImageAndApply( l_chipletData.iv_num_common_rings = 0; l_chipletData.iv_num_instance_rings = 0; l_chipletData.iv_num_variants = 0; + uint16_t* l_ringTorAddr = NULL; + uint32_t* l_sectionAddr = NULL; getRingProperties(i_ringID, &l_torOffset, &l_ringType); @@ -64,16 +66,7 @@ fapi2::ReturnCode findRS4InImageAndApply( l_chipletData = g_eqData; - if( l_hcodeLayout->g_sgpe_cmn_ring_occ_offset == 0) - { - FAPI_INF("No data COMMON ring section"); - break; - } - uint32_t l_chipletID = i_target.getChipletNumber(); - // Determine the section TOR address for the ring - uint32_t* l_sectionAddr = - (uint32_t*)(SGPE_SRAM_BASE + l_hcodeLayout->g_sgpe_cmn_ring_occ_offset); if(INSTANCE_RING == l_ringType) { @@ -85,13 +78,35 @@ fapi2::ReturnCode findRS4InImageAndApply( l_sectionAddr = (uint32_t*)(SGPE_SRAM_BASE + l_hcodeLayout->g_sgpe_spec_ring_occ_offset); - l_sectionAddr += ((l_chipletID - - l_chipletData.iv_base_chiplet_number) * l_chipletData.iv_num_instance_rings); + if ( l_chipletID >= l_chipletData.iv_base_chiplet_number) + { + uint32_t l_ex_number = 0; + uint8_t l_chipletOffset = (l_chipletID - l_chipletData.iv_base_chiplet_number); + + if (fapi2::TARGET_TYPE_EX & (i_target.getTargetType())) + { + l_ex_number = (i_target.getTargetNumber()) % 2; + PK_TRACE ("l_chipletID %d l_ex_number %d", l_chipletID, l_ex_number); + } + + //12 is considered as instance ring size + l_ringTorAddr = reinterpret_cast<uint16_t*>(l_sectionAddr ) + ((l_chipletOffset * + 12) + (l_torOffset + l_ex_number)); + } } + else + { + if (l_hcodeLayout->g_sgpe_cmn_ring_occ_offset == 0) + { + FAPI_INF("No data in common ring section"); + } + + l_sectionAddr = + (uint32_t*)(SGPE_SRAM_BASE + l_hcodeLayout->g_sgpe_cmn_ring_occ_offset); + + l_ringTorAddr = reinterpret_cast<uint16_t*>(l_sectionAddr) + (l_torOffset); - // TOR records of Ring TOR are 2 bytes in size. - uint16_t* l_ringTorAddr = (uint16_t*)(l_sectionAddr) + - (l_torOffset * l_chipletData.iv_num_variants); + } if(*l_ringTorAddr != 0) { |
