diff options
3 files changed, 1 insertions, 23 deletions
diff --git a/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H b/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H index 99619d57..b075c862 100644 --- a/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H +++ b/import/chips/p9/procedures/hwp/lib/p9_common_poweronoff.H @@ -528,17 +528,6 @@ p9_common_poweronoff( FAPI_DBG("Assert vital thold via NET_CTRL0[16]"); FAPI_TRY(putScom(i_target, NET_CTRL0_WOR[l_type], MASK_SET(16))); - if (l_type == 1) - { - // upon power off cache, dpll is about to be unlocked - // to prevent pcb fir fires, need to mask the bit for the time being - // the error will be cleared and unmasked when dpll is locked again - FAPI_DBG("Mask DPLL unlock error in FIR via SLAVE_CONFIG[12]"); - FAPI_TRY(getScom(i_target, EQ_SLAVE_CONFIG_REG, l_data64)); - l_data64.setBit<12>(); - FAPI_TRY(putScom(i_target, EQ_SLAVE_CONFIG_REG, l_data64));// - } - /////////////////////////////////////////////////////////////////////////// // Procedure code /////////////////////////////////////////////////////////////////////////// diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c index 0de59f29..8a075b47 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_hcd_cache_dpll_setup.c @@ -128,11 +128,8 @@ p9_hcd_cache_dpll_setup(uint32_t quad) #endif GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_OPCG_ALIGN, quad), scom_data); - PK_TRACE("Clear PLL unlock errors in PCB slave, unmask FIR propagation"); + PK_TRACE("Clear PLL unlock errors in PCB slave"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_ERROR_REG, quad), 0xFFFFFFFFFFFFFFFF); - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_SLAVE_CONFIG_REG, quad), scom_data); - scom_data &= ~BIT64(12); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_SLAVE_CONFIG_REG, quad), scom_data); PK_TRACE("Drop skew/duty cycle adjust func_clksel via NET_CTRL0[22]"); GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_NET_CTRL0_WAND, quad), ~BIT64(22)); diff --git a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c index d1f28eb2..d1b06e5b 100644 --- a/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_entry.c @@ -1169,14 +1169,6 @@ p9_sgpe_stop_entry() } else { - // upon power off cache, dpll is about to be unlocked - // to prevent pcb fir fires, need to mask the bit for the time being - // the error will be cleared and unmasked when dpll is locked again - PK_TRACE("Mask DPLL unlock error in FIR via SLAVE_CONFIG[12]"); - GPE_GETSCOM(GPE_SCOM_ADDR_QUAD(EQ_SLAVE_CONFIG_REG, qloop), scom_data.value); - scom_data.words.upper |= BIT32(12); - GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(EQ_SLAVE_CONFIG_REG, qloop), scom_data.value); - PK_TRACE("Drop vdd/vcs_pfet_val/sel_override/regulation_finger_en via PFCS[4-7,8]"); // vdd_pfet_val/sel_override = 0 (disbaled) // vcs_pfet_val/sel_override = 0 (disbaled) |
