diff options
3 files changed, 55 insertions, 57 deletions
diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h index 5dde000d..d5ed4b75 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop.h @@ -290,7 +290,7 @@ typedef struct /// CME STOP Entry and Exit Prototypes -#ifdef HW405292_NDD1_PCBMUX_SAVIOR +#if HW405292_NDD1_PCBMUX_SAVIOR void p9_cme_pcbmux_savior_prologue(uint32_t); void p9_cme_pcbmux_savior_epilogue(uint32_t); #endif diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c index d9e823ab..2b5dfabc 100755 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_entry.c @@ -55,15 +55,6 @@ extern CmeStopRecord G_cme_stop_record; void prepare_for_ramming (uint32_t core) { uint64_t scom_data; - PK_TRACE("LPID Assert block interrupt to PC via SICR[2/3]"); - out32(CME_LCL_SICR_OR, core << SHIFT32(3)); - - PK_TRACE("LPID Waking up the core(pm_exit=1) via SICR[4/5]"); - out32(CME_LCL_SICR_OR, core << SHIFT32(5)); - - PK_TRACE("LPID Polling for core wakeup(pm_active=0) via EINR[20/21]"); - - while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); // Now core thinks its awake and ramming is allowed PK_TRACE("RAMMING Put in core maintenance mode via direct controls"); @@ -178,26 +169,15 @@ void turn_off_ram_mode (uint32_t core) PK_TRACE("LPID Clear core maintenance mode via direct controls"); CME_PUTSCOM(DIRECT_CONTROLS, core, (BIT64(3) | BIT64(11) | BIT64(19) | BIT64(27))); - PK_TRACE("LPID Drop pm_exit via SICR[4/5]"); - out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); - - PK_TRACE("LPID Polling for core to stop(pm_active=1) via EINR[20/21]"); - - while((~(in32(CME_LCL_EINR))) & (core << SHIFT32(21))); - - PK_TRACE("LPID Clear pm_active status via EISR[20/21]"); - out32(CME_LCL_EISR_CLR, core << SHIFT32(21)); - - PK_TRACE("LPID Drop block interrupt to PC via SICR[2/3]"); - out32(CME_LCL_SICR_CLR, core << SHIFT32(3)); - + PK_TRACE("LPID Wait for 8K Core Cycles"); + PPE_WAIT_CORE_CYCLES(8000); } #endif -#ifdef HW405292_NDD1_PCBMUX_SAVIOR +#if HW405292_NDD1_PCBMUX_SAVIOR void p9_cme_pcbmux_savior_prologue(uint32_t core) { @@ -391,6 +371,8 @@ p9_cme_stop_entry() PK_TRACE("+++++ +++++ STOP LEVEL 1 ENTRY +++++ +++++"); //---------------------------------------------------------------------- + // Note: Only Stop1 requires pulsing entry ack to pc, + // thus this is NDD1 only as well. PK_TRACE("Pulse STOP entry acknowledgement to PC via SICR[0/1]"); out32(CME_LCL_SICR_OR, core_stop1 << SHIFT32(1)); out32(CME_LCL_SICR_CLR, core_stop1 << SHIFT32(1)); @@ -422,8 +404,10 @@ p9_cme_stop_entry() PK_TRACE("+++++ +++++ STOP LEVEL 2 ENTRY +++++ +++++"); //---------------------------------------------------------------------- -#ifdef HW405292_NDD1_PCBMUX_SAVIOR +#if HW405292_NDD1_PCBMUX_SAVIOR + p9_cme_pcbmux_savior_prologue(core); + #endif PK_TRACE("Request PCB mux via SICR[10/11]"); @@ -435,19 +419,12 @@ p9_cme_stop_entry() PK_TRACE("PCB Mux Granted on Core[%d]", core); -#ifdef HW405292_NDD1_PCBMUX_SAVIOR +#if HW405292_NDD1_PCBMUX_SAVIOR - if (1) - { - p9_cme_pcbmux_savior_epilogue(core); - } + p9_cme_pcbmux_savior_epilogue(core); #endif - PK_TRACE("Pulse STOP entry acknowledgement to PC via SICR[0/1]"); - out32(CME_LCL_SICR_OR, core << SHIFT32(1)); - out32(CME_LCL_SICR_CLR, core << SHIFT32(1)); - // set target_level from pm_state for both cores or just one core target_level = (core == CME_MASK_C0) ? G_cme_stop_record.req_level[0] : G_cme_stop_record.req_level[1]; @@ -488,9 +465,23 @@ p9_cme_stop_entry() PK_TRACE_DBG("Check: core[%d] target_lv[%d] deeper_lv[%d] deeper_core[%d]", core, target_level, deeper_level, deeper_core); + // Permanent workaround for HW407385 + + PK_TRACE("HW407385: Assert block interrupt to PC via SICR[2/3]"); + out32(CME_LCL_SICR_OR, core << SHIFT32(3)); + + PK_TRACE("HW407385: Waking up the core(pm_exit=1) via SICR[4/5]"); + out32(CME_LCL_SICR_OR, core << SHIFT32(5)); + + PK_TRACE("HW407385: Polling for core wakeup(pm_active=0) via EINR[20/21]"); + + while((in32(CME_LCL_EINR)) & (core << SHIFT32(21))); + + // end of HW407385 + #if HW402407_NDD1_TLBIE_STOP_WORKAROUND -// Save thread's LPIDs and overwrite with POWMAN_RESERVED_LPID + // Save thread's LPIDs and overwrite with POWMAN_RESERVED_LPID prepare_for_ramming(core); for (thread = 0; thread < 4; thread++ ) @@ -541,11 +532,9 @@ p9_cme_stop_entry() } } -// turn_off_ram_mode (core); - - #endif // tlbie stop workaround + PK_TRACE_INF("SE.2A: Core[%d] PCB Mux Granted", core); //============================= @@ -577,11 +566,10 @@ p9_cme_stop_entry() PK_TRACE_INF("SE.2B: Interfaces Quiesced"); -#if HW402407_NDD1_TLBIE_STOP_WORKAROUND -// Restore thread's LPIDs +#if HW402407_NDD1_TLBIE_STOP_WORKAROUND -// prepare_for_ramming(core); + // Restore thread's LPIDs for (thread = 0; thread < 4; thread++ ) { @@ -623,9 +611,25 @@ p9_cme_stop_entry() #endif turn_off_ram_mode (core); - #endif // tlbie stop workaround + // Permanent workaround for HW407385 + + PK_TRACE("HW407385: Drop pm_exit via SICR[4/5]"); + out32(CME_LCL_SICR_CLR, core << SHIFT32(5)); + + PK_TRACE("HW407385: Polling for core to stop(pm_active=1) via EINR[20/21]"); + + while((~(in32(CME_LCL_EINR))) & (core << SHIFT32(21))); + + PK_TRACE("HW407385: Clear pm_active status via EISR[20/21]"); + out32(CME_LCL_EISR_CLR, core << SHIFT32(21)); + + PK_TRACE("HW407385: Drop block interrupt to PC via SICR[2/3]"); + out32(CME_LCL_SICR_CLR, core << SHIFT32(3)); + + // end of HW407385 + //========================== MARK_TRAP(SE_STOP_CORE_CLKS) //========================== diff --git a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c index 1f8eea82..f5a15fcc 100644 --- a/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c +++ b/import/chips/p9/procedures/ppe_closed/cme/stop_cme/p9_cme_stop_exit.c @@ -288,8 +288,10 @@ void p9_cme_stop_exit_lv2(uint32_t core) // do this after assert glsmux so glitch can have time to resolve // catchup to stop2 exit will acquire here -#ifdef HW405292_NDD1_PCBMUX_SAVIOR +#if HW405292_NDD1_PCBMUX_SAVIOR + p9_cme_pcbmux_savior_prologue(core); + #endif PK_TRACE("SX.20: Request PCB mux via SICR[10/11]"); @@ -301,12 +303,9 @@ void p9_cme_stop_exit_lv2(uint32_t core) PK_TRACE("SX.20: PCB Mux Granted on Core[%d]", core); -#ifdef HW405292_NDD1_PCBMUX_SAVIOR +#if HW405292_NDD1_PCBMUX_SAVIOR - if (1) - { - p9_cme_pcbmux_savior_epilogue(core); - } + p9_cme_pcbmux_savior_epilogue(core); #endif @@ -606,8 +605,10 @@ p9_cme_stop_exit() // Can't do the read of cplt_stat after flipping the mux before the core is powered on // catchup to stop4 exit will acquire here -#ifdef HW405292_NDD1_PCBMUX_SAVIOR +#if HW405292_NDD1_PCBMUX_SAVIOR + p9_cme_pcbmux_savior_prologue(core); + #endif PK_TRACE("SX.40: Request PCB mux via SICR[10/11]"); @@ -619,14 +620,7 @@ p9_cme_stop_exit() PK_TRACE("SX.40: PCB Mux Granted on Core[%d]", core); -#ifdef HW405292_NDD1_PCBMUX_SAVIOR - - if (0) - { - p9_cme_pcbmux_savior_epilogue(core); - } - -#endif + // Note: in this case, no need to call p9_cme_pcbmux_savior_epilogue //======================== MARK_TAG(SX_POWERON, core) |
